Freescale i.mx6 Architecture

Transcription

1 Freescale i.mx6 Architecture Course Description Freescale i.mx6 architecture is a 3 days Freescale official course. The course goes into great depth and provides all necessary know-how to develop software for systems based on i.mx6 processor. The first day starts by overviewing the i.mx6x Family and its Target applications, Device architecture (Quad/Dual/Dual-Lite/Solo/Solo-Lite/SoloX), and family roadmap. The course continuous with deep dive training of all i.mx6 internal blocks and accelerators such as memory system and DDR controller (MMDC), USB, SATA, PCI-E, emmc/sd, NAND controller, Audio subsystem, clocking and reset, and power management unit. The second day covers the Cortex-A9 MPCore architecture and capabilities, the smart DMA (SDMA), I/O muxing (with IOMUX tool), and GPMI and NAND interface subsystem, 1G Ethernet + IEEE1588, and MIPI display and sensor interface. The third day covers the boot process (including secured boot with HAB) and boot devices, security features and hardware blocks, Image Processing Unit (IPU), Video Processing Unit (VPU), Graphics Processing Unit (GPU), and HDMI. The course ends with an overview of embedded board solutions (COM and SOM). Course Duration 3 day

2 Goals 1. Become familiar with i.mx6 architecture 2. Become familiar with Cortex-A9 MPCore architecture 3. Choose the right DDR device and configure the right mode 4. Connect efficiently cameras, displays and audio devices/codecs 5. Design clock, reset and power management strategy 6. Configure the SDMA and load scripts 7. Configure I/Os with IOMUX tool 8. Choose NAND interface and configure ECC with BCH 9. Decide how to Boot and use secure boot with HAB 10. Secure your system with security hardware blocks and TrustZone 11. Encode/Decode video streams with VPU 12. Enhance image processing with IPU 13. Combine 2D and 3D graphics 14. Choose the right embedded board solution Target Audience Software engineers that would like developing software and BSP for platforms based on i.mx6 SoC Prerequisites Computer architecture background Rich OS experience (Linux, WINCE, Android) Experience in developing embedded systems

3 Agenda Main Topics: Main features and road map i.mx6 series overview Device architecture overview Memory system and DDR controller i.mx6 interfaces overview Cortex-A9 MPCore platform overview Clocking and reset Power management Cortex-A9 MPCore architecture and capabilities deep dive SDMA I/O muxing GPMI and NAND interface subsystem 1GbE MIPI sensor and display i.mx6 Boot i.mx6 security Image Processing Unit (IPU) Video Processing Unit (VPU) Graphics Processing Unit (GPU) Embedded board solutions

4 Day #1 Introduction to the i.mx6 architecture i.mx6 Family Roadmap o i.mx5x, i.mx6x, i.mx7x, i.mx8x o Cortex-A50 series partnership o Freescale s product longevity program i.mx6 Market Applications Overview o Platform strategy o Smart devices examples i.mx6 Series Overview o One Platform, differentiated products o Differentiated features o Scalability & compatibility from Solo to Quad core o Intelligent integration of multimedia o Triple-Play graphics support o Quad/Dual/DualLite/Solo/SoloLite/SoloX block diagrams o Part number definition and packaging options o Development boards o Yocto and Android roadmaps Device Architecture Overview o SoC block diagram o Cortex-A9 platform o Dual and quad core advantages o Video & graphics systems o Display support and muxing o Video encode, decode capabilities o Vector graphics, 2D composition engine and opengl/opencl GPU engines Memory System & DDR Controller o Multi-Mode DDR Controller (MMDC) main features o MMDC block diagram o MMDC highlights o MMDC control: low power o MMDC calibration o MMDC configuration examples o Low latency and guaranteed bandwidth o MMDC configuration in memory map o DDR channels and address mapping o MMDC modes and basic settings o DDR3 DLL OFF mode o Two channel interleaving

5 o Bus system and QoS o DDR arbiter o MMDC debug o Bus/DDR profiling o DDR power saving modes i.mx6 Interfaces o Memory & mass storage interfaces o SD/eMMC o SATA II o USB o Ethernet controller o PCIe 2.0 o Audio system o UART, ecspi, keypad, one-wire, GPT, PWM, I2C, GPIO o Camera interface and displays Introduction to the Cortex-A9 MPCore Architecture o Cortex-A9 MPCore platform overview o Platform configuration o Core configuration o L2 Cache configuration i.mx6 Clocking & Reset o Clock generation scheme o Clock generation deep dive o Clock management system block diagram o PLL control & status functions o Clock Control Module (CCM) o Low Power Clock Gating (LPCG) o Clock configuration o Clock change procedure o System Reset Controller (SRC) o Power-On reset & power sequencing o SRC functional description o POR, Cold and Warm reset i.mx6 Power Management o Power management system o Integrated PMU components o General Power Controller (GPC) o Power-up/down sequence o Logic state retention o Voltage domain management o DVFS examples o Standby Leakage Reduction (SLR) o System power tree

6 o Freescale PF series PMIC (PFUZE) o Processor power needs o PF0100 overview o Low power modes o Wake-up events o Power saving techniques o Temperature monitor o Balance high performance and low power o Main memory power management o ONOFF button support i.mx6 architecture Deep Dive Day #2 Cortex-A9 MPCore Features & Capabilities o ARM processors overview o Cortex-A9 programmers model Instruction sets Processor modes Register set Co-processors o Cortex-A9 functional description Cortex-A9 block diagram Cortex-A9 MPCore Energy efficiency features Pipeline description Register renaming Branch prediction Fast loop mode Performance Monitoring Unit (PMU) NEON technology VFPv3 vector floating point L1 memory system L1 cache memory Write buffer Data prefetching L2 cache controller (PL310) Memory Management Unit (MMU) TLB Memory access permissions Memory ordering Memory types in ARMv7 Cortex-A9 MPCore cache coherency Enabling Snoop Control Unit (SCU)

7 MESI protocol o Global Interrupt Controller (GIC) GIC architecture GIC basic initialization o System debug Embedded cross triggering Debug scheme SDMA o SDMA block diagram o SDMA core deep dive o Scheduler functional description o Scheduler use case examples o Context switching o Burst and peripheral DMA o Security support o OnCE & PCU debug states o SDMA programming model o Address space o Hardware reset effect o Standard boot sequence o Script loading & context initialization IOMux Controller o Introduction o IOMUX features o Choosing signals and resolving pin conflicts o Ensuring voltage consistency per module o Alternate IOMux views o Demonstration on IOMUX tool GPMI & NAND Interface o NAND controller overview o General Purpose Media Interface (GPMI) o GPMI NAND mode o Multiple NAND support o Hardware BCH interface o 40-bit correcting ECC accelerator (BCH) o BCH limitations and assumptions o NAND bottlenecks 1G Ethernet o MAC-NET features o MAC-NET block diagram o IP protocol performance optimization features o IEEE 1588 features o Media independent interface

8 o Ethernet clock generation MIPI Display & Sensor Interfaces o MIPI DSI o MIPI DBI o MIPI CSI-2 o MIPI HSI HDMI o General features o Block diagram and supported formats o Audio DMA interface o HDCP (secured HDMI) o CEC hardware engine i.mx6 Boot, Security & Multimedia Day #3 i.mx6 Boot o System Boot overview o Boot modes and boot sources o Boot mode pin settings o Boot from fuses o Serial downloader o Internal boot o Boot security settings o GPIO override pads o Multi-core Boot flow o Boot block activation o Enabling MMU and caches o Program image o High Assurance Boot (HAB) o Secure Boot components o Encrypted image support o USB low power Boot Security o i.mx6 security features o Security subsystem block diagram o Common security attacks o TrustZone: CPU secure & non secure worlds o Boot ROM o Cryptographic Acceleration and Assurance Module (CAAM) o Secure memory

9 o Algorithm acceleration o Secure non-volatile storage (SNVS) o Secure JTAG Controller (SJC) o Memory & peripheral isolation for TrustZone support Image Processing Unit (IPU) o Video sources o Display sources o IPU block diagram o The display port o Access modes (synchronous/asynchronous) o Display Interface (DI) o Display Controller (DC) o Display Multi-FIFO Controller (DMFC) o Image DMA Controller (IDMAC) o Display Processor (DP) o Image Converter (IC) o Image Rotator (IRT) o Video De-Interlace or Combiner (VDIC) o Basic combining capabilities o Off-line combining o Maximal on-the-fly combining to a single and multi-displays o IPU programming steps o Camera Sensor Interface (CSI) o 16 bit camera support o MIPI CSI-2 o Control Module (CM) o Display Content Integrity Checker (DCIC) Video Processing Unit (VPU) o The multimedia processing chain o Decoder o Encoder o Multi-streams o On-the-fly transcoding o Full duplex HW Codec o Codec licensing o VPU architecture overview (BIT processor) o Normal and Low power modes o VPU initialization (Boot) o VPU-IPU interface o Bandwidth for typical worse case o VPU driver API o VPU software structure

10 Graphics Processing Unit (GPU) o Graphics processing units (Vivante GC2000, GC320, GC355, GC880) o Graphics processing advantages o Composition engine GPU o OpenVG vector graphics processor o OpenGL ES 3D engine o GPU architecture o GPU SDK o GPU application development o OpenCL Embedded Board Solutions o Freescale partners o Make vs buy decision matrix o SOM/COM standard vs non-standard