Multicore and MIPS: Creating the next generation of SoCs. Jim Whittaker EVP MIPS Business Unit

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1 Multicore and MIPS: Creating the next generation of SoCs Jim Whittaker EVP MIPS Business Unit

2 Many new opportunities Wearables Home wireless for everything Automation & Robotics ADAS and intelligent transport IoT/IoE Health Energy Agriculture Big data & analytics Flexible CPU & heterogeneous processing key to catch the next wave Imagination Technologies Multicore Keynote Sept

3 Imagination s IP portfolio Everything needed to create connected SoC solutions FlowCloud Connectivity Ensigma Communications Processors MIPS General Processors PowerVR Graphics & GPU Compute Processors PowerVR Video & Vision Processors Unified Memory Each IP core is a class leader - when used with any other processors Lowest power - Smallest silicon area Open and customer - centric business model Imagination Technologies Multicore Keynote Sept

4 Why Multicore Number of transistors on a chip far exceeds the number we can use to increase single thread performance Methods used to increase single thread performance result in reduced power efficiency Workload dictates the optimum balance of compute resources Optimised hardware for specific tasks improve performance/power Imagination Technologies Multicore Keynote Sept

5 Momentum - MIPS CPUs Already deployed across the spectrum 32-bit embedded microcontrollers 64-bit advanced networking processors and everything in-between! Imagination Technologies Multicore Keynote Sept

6 MIPS is strong and growing Delivering the architecture Delivering the IP cores Building up the ecosystem Revolutionising security >5B MIPS CPUs shipped Up to 40% smaller than competitors Industry s leading CoreMark performance 64bit CPU IP shipping in volume for 20 years Delivering the most compelling alternative for 64/32bit CPU IP Imagination Technologies Multicore Keynote Sept

7 Now And now the next phase begins I6400: not just the next MIPS CPU core the next era of CPU IP Warrior Series5P MIPS r5 32-bit Aptiv proaptiv interaptiv microaptiv P5600 Warrior Series5M MIPS r5 32-bit M5150 MPU with MMU M5100 MCU Warrior Series6I MIPS r6 64/32-bit I6400 Imagination Technologies Multicore Keynote Sept

8 I6400: Broad feature set for a wide range of applications Automotive/ Embedded DTV/STB Mobile Enterprise SMT, Virtualization, SIMD, Heterogeneous MC, ECC SMT, Virtualization, SIMD, MC 64-bit, SMT, Virtualization, SIMD, Heterogeneous MC 64-bit, SMT, MC, Multi-Cluster, Virtualization, ECC Broadest set of applications ever addressed by a single MIPS core family Imagination Technologies Multicore Keynote Sept

9 I6400 A MIPS64 AND MIPS32 processor MIPS64 MIPS32 Instructions dealing with 64-bit data MIPS64 Is MIPS32, plus instructions for 64-bit data types Runs MIPS32 software without mode switching MIPS64/32 Release 6 Streamlining a highly efficient architecture Modernization of architecture through: Additional instructions for enhanced execution on modern software workloads = JITs, VMs, PIC, etc. commonly found in Javascript, Browsers, abstracted compiler technologies (i.e. LLVM) MIPS: the ultimate 64/32-bit architecture

10 I6400 Multi-threading A powerful differentiator among IP cores Why MT? A path to higher performance, and higher efficiency 30%-50% higher performance for 10% increase in cluster area* Ex. CoreMark, DMIPS, SPECint2000 Decades of multi-threading expertise in MIPS and Imagination Easy to use programming model is same as multi-core A thread looks like a core to standard SMP OSs Simultaneous multi-threading (SMT) execution Multiple threads execute in a given pipeline stage per cycle, or Superscalar execution on a single thread Thread execution can switch dynamically per cycle * Preliminary performance benefit on popular benchmarks for adding a 2 nd thread in I6400 processor, with silicon area cost Thread 1 I6400 Thread 2 Thread 3 Hardware Scheduler Thread 4 Instruction Queues Execution Queues Imagination Technologies Multicore Keynote Sept

11 MIPS64 I hardware virtualization highlights Rich set of Trusted Execution Environment features and benefits Secure Root is the secure hypervisor/kernel Guest access rights controlled by Root Full VZ using Root/Guest TLB Scalable Supports up to 15 Guests (OS and/or Apps) SoC virtualization support Virtualized GIC (interrupt controller) and IOMMU Bus transactions to other IP include Guest ID Benefits Ease of use - no modification required to Guest OS Reliability corrupted/crashed OS1 cannot affect OS2 Performance intelligent resource allocation Security multi-domain support in hardware Secure/non-Secure OS/Apps App OS1 App App App OS2 Hypervisor/Secure Kernel MIPS core App Guests Root Imagination Technologies Multicore Keynote Sept

12 MIPS64 I6400 base core microarchitecture Optimized for efficiency and maximizing pipeline utilization Optional L1 Instr Cache (32-64 KB, 4 way) Branch Predict BHT, JRC, RPS Execution Pipes MDU Pipe ALU Pipe Snoop Trace Bus Interface Unit Instruction Fetch Unit ALU Pipe EJTAG MCP I/F (128-bit to CM) Thread1 Thread2 Thread3 Thread4 TAP Instruction Issue Unit MT SIMD Integer and SP/DP FPU Graduation Unit Power Mgmt Unit (PMU) Branch Pipe Branch Resolution and Store Data Pipe Mem Mgmt Unit 4-entry I & D utlbs per VC 64/96 Entry VTLB 512 Entry FTLB Memory Pipe Load/ Store Address L1 Data Cache (32-64 KB, 4 way) Dual-issue In-Order design with MT Compact, balanced 9-stage pipeline Dual issue 128b SIMD (Int, SP/DP FPU) IEEE compliant FPU Instruction bonding on integer, FP ops Doubles throughput on memcopies Instruction and Data L1 caches w/ ECC 64 byte cache lines Advanced Branch Prediction Low latency 128b core:cm interface On Chip Trace I/F Debug Off-chip Trace I/F

13 MIPS64 I6400 multi-core features Leverages new coherency architecture GCRs Custom GCRs Global Interrupt Controller (GIC) Cluster Power Controller (CPC) Trace Funnel Core 0 Low Power High Performance Core 1 Core 3 Coherency Mgr. with L2$ (Directory-based) Core 4 Core 5 Core 2 IOCU 0 IOCU 1 IO Subsystem 128 bits ACE/AXI4 To System 128 bits 256 bits Coherent cluster, up to 6 cores Directory-based coherency improves power, performance and scalability PowerGearing for MIPS Virtualized GIC and IOMMUs Integrated L2 Cache (L2$) 512KB 8MB (16-way) with ECC Low L2$ hit latencies HW prefetch lowers latency to memory AXI4 -> ACE System Interface Multi-cluster, heterogeneous scalability Imagination Technologies Multicore Keynote Sept

14 Building systems:- Threads, cores and clusters 1 Thread Core 2-4 Thread Core 2-6 Core Cluster 2-64 Cluster Node Imagination Technologies Multicore Keynote Sept

15 Building systems:- Threads, cores and clusters 1 Thread Core 2-4 Thread Core 2-6 Core Cluster 2-64 Cluster Node SoC Fabric Wide range of CPU configurations Hardware virtualization based security PowerGearing power management Imagination Technologies Multicore Keynote Sept

16 Flexible configuration for flexible needs Hardware multi-threading 30%-50% more performance for 10% more area Multi-core Mix of cores/configurations Multi-cluster Mix of heterogeneous CPU clusters Embedded Consumer/STB Mobile Server Storage Dataplane Imagination Technologies Multicore Keynote Sept

17 It s not just CPUs true heterogeneous processing Single Thread Multi- Thread Core Multi-Core CPU Cluster Multi-Core GPU Cluster Imagination Technologies Multicore Keynote Sept

18 IP Platforms: Heterogeneous Network Processors MIPS leads the way in security, hardware multi-threading, coherency and efficiency Ensigma NPU 10/40/100Gbps Offload MIPS Coherent Multicore Cluster Ensigma NPU Crypto Offload Terabit Coherent Fabric MIPS Coherent Multicore Cluster Customer Differentiating System IP PowerVR Multicore GPU Compute Unified Memory Up to 40% better processor area for multi-core Comprehensive support for hardware multi-threading Coherency across thread, core, cluster Imagination Technologies Multicore Keynote Sept

19 IP Platforms: Heterogeneous IoT Device Processors High end feature set for deeply embedded = scales perfectly from high end Ensigma RPU BT Smart Low Power Wi-Fi Customer Differentiating System IP SoC Fabric MIPS M-Class MCU On-chip Flash On-chip RAM Hardware Virtualization Tightly integrated, low power communications Class-leading single thread performance Imagination Technologies Multicore Keynote Sept

20 Conclusions Multicore is not just about multiple cores Threads, cores and clusters and not just CPUs The application space is getting wider Flexible cluster configuration for power management and burst performance needs many options MIPS Series6 Warrior cores deliver a compelling alternative for multi thread/core/cluster CPU IP Not just for CPUs, but for heterogeneous SoCs Imagination Technologies Multicore Keynote Sept

21 Multicore and MIPS: Creating the next generation of SoCs Jim Whittaker EVP MIPS Business Unit