Engineer-to-Engineer Note EE-245 Technicl notes on using Anlog Devices DSPs, processors nd development tools Contct our technicl support t dsp.support@nlog.com nd t dsptools.support@nlog.com Or visit our on-line resources http://www.nlog.com/ee-notes nd http://www.nlog.com/processors Interfcing AD7276 High-Speed Dt Converters to ADSP-BF535 Blckfin Processors Contributed by Aseem Vsudev Prbhugonkr Rev 1 October 4, 2004 Introduction This ppliction note explins how to interfce AD7276 high-speed dt converters to Blckfin processors. This ppliction note lso provides exmple code to demonstrte how the Blckfin processor's seril ports (SPI nd SPORTs) cn be progrmmed to receive dt from AD7276 devices in core nd DMA modes. The power-down scheme for AD7276 ADCs between conversions in DMA mode is lso described. The interfce is chieved using n ADSP-BF535 EZ-KIT Lite bord. About AD7276/7277/7278 ADCs The AD7276/AD7277/AD7278 devices re 12-, 10-, nd 8-bit, high-speed, low-power, successive-pproximtion ADCs, respectively. The prts operte from single 2.35 V to 3.6 V power supply nd feture throughput rtes up to 3 million smples per second (MSPS). The conversion process nd dt cquisition re controlled using the /CS signl nd the seril clock, llowing the devices to interfce with vriety of microprocessors or DSPs. The input signl is smpled on the flling edge of /CS, nd the conversion is lso initited t this point. There re no pipeline delys ssocited with the prt. The AD7276/AD7277/AD7278 ADCs use dvnced design techniques to chieve very low power dissiption t high throughput rtes. The reference for the prt is tken internlly from VDD. This llows the widest dynmic input rnge to the ADC. Thus, the nlog input rnge for the prt is from 0 V to VDD. The conversion rte is determined by the seril clock SCLK. AD7276/7277/7278 Product Highlights 3 MSPS ADCs in 6-led TSOT pckge Pin comptible to AD7476/7477/7478 nd AD7476A/7477A/7478A prts High throughput with low power consumption Flexible power / seril clock speed mngement The conversion rte is determined by the seril clock. Incresing the seril clock speed reduces the conversion time. This reduces verge power consumption while in powerdown mode (i.e., while not converting). The prt lso fetures power-down mode to mximize power efficiency t lower throughput rtes. Current consumption is 1 µa mx in power-down mode. Reference derived from the power supply No pipeline dely The prts feture stndrd successive pproximtion ADC with ccurte control of the smpling instnt vi /CS input nd onceoff conversion control. Copyright 2004, Anlog Devices, Inc. All rights reserved. Anlog Devices ssumes no responsibility for customer product design or the use or ppliction of customers products or for ny infringements of ptents or rights of others which my result from Anlog Devices ssistnce. All trdemrks nd logos re property of their respective holders. Informtion furnished by Anlog Devices pplictions nd development tools engineers is believed to be ccurte nd relible, however no responsibility is ssumed by Anlog Devices regrding technicl ccurcy nd topiclity of the content provided in Anlog Devices Engineer-to-Engineer Notes.
AD7276/7277/7278 A/D Applictions AD7276/7277/7278 pplictions include: Bttery-Powered Systems Personl Digitl Assistnts Medicl Instruments Mobile Communictions Instrumenttion nd Control Systems Dt Acquisition Systems High-Speed Modems Opticl Sensors About ADSP-BF535 Processors The ADSP-BF535 processor is the first member of the Blckfin fmily ADI's newest fmily of high-performnce processors bsed on the Micro Signl Architecture (MSA). ADSP-BF535 prts feture dul-macs, high clock rtes, nd dynmic power mngement, llowing for optimiztion of system performnce nd power consumption. Additionlly, through the dvntges of clen, orthogonl RISC instruction set, ADSP-BF535 processors re optimized for progrmming in high-level lnguges such s C/C++, resulting in extremely dense code. Blckfin Processor Applictions Trget pplictions of Blckfin processor include: Automotive Brodbnd Home Gtewys Centrl Office/Network Switches Digitl Imging nd Printing Globl Positioning Systems Home Networking Internet Applinces Modem Solutions Personl Digitl Assistnts Video Conferencing VoIP Phone Solutions PDAs nd other portble/hnd-held devices AD7276-to-ADSP-BF535 Interfce This ppliction note focuses on the interfce to n AD7276 high-speed dt converter. AD7277 nd AD8278 converters interfce the sme wy. The ADCs hve seril interfce for DSPs nd micro-controllers for trnsferring 12-bit digitized dt. The ADCs support SPI (Seril Peripherl Interfce) nd SPORT (DSP Seril Port) interfce protocols. Blckfin processors cn connect to n AD7276 over their SPI or SPORT interfces. The seril interfce of AD7276 comprises three signls. /CS Chip Select is n ctive low input. This signl initites A-to-D conversion nd frmes the seril dt trnsfer. SDATA The AD7276 drives conversion results onto this pin. The dt bits re clocked out on the flling edge of the seril clock. SCLK Seril clock is n input to the ADC. The converter clocks the dt bits out on the flling seril clock edges. The flling edge of /CS puts trck-nd-hold into hold mode nd initites conversion. For comptibility with the 16-bit word length supported by SPI, the ADC outputs 16-bits. The first two bits (zeros) re followed by 12 vlid dt bits nd two zero bits t the end of the seril dt strem. Though the ADC dt is 12 bits, ech word is trnsferred s 16-bit word. This ensures comptibility with the SPI stndrd, configurble to word lengths of 8 or 16 bits on Blckfin devices. When interfced to SPORT modules, the seril word length cn be configured to 14 bits; hence, the lst two bits cn be ignored. On the 14 th SCLK rising edge, the converter logic chnges bck to trck mode. Interfcing AD7276 High-Speed Dt Converters to ADSP-BF535 Blckfin Processors (EE-245) Pge 2 of 6
ADSP-BF535 SPI port PF2 SCK0 /CS SCLK AD7276 12-bit seril AD converter MISO SDATA Figure 1. AD7276 Seril Interfce Timing Digrm Refer to the AD7276 dt sheet for detiled informtion bout the timing specifictions. SPI Interfce Detils This section discusses the AD7276 interfce with SPI port using n ADSP-BF535 EZ-KIT Lite bord. ADSP-BF535 Blckfin processors feture two independent Seril Peripherl Interfce (SPI) ports (SPI0 nd SPI1) tht provide n I/O interfce to wide vriety of SPI-comptible peripherl devices including codecs, dt converters, nd smple rte converters. Ech SPI port hs set of control registers nd dt buffers. The ADSP-BF535 processor s SPI module is n industry-stndrd synchronous seril link tht supports communiction with multiple SPIcomptible devices. The SPI peripherl is synchronous, 4-wire interfce consisting of two dt pins (MOSI nd MISO), one device select pin (/SPISS), nd gted clock pin (SCK). The ADSP- BF535 SPI supports the following fetures: Full duplex opertion Mster-slve mode multi-mster environment Open drin outputs Progrmmble bit rtes, clock polrities, nd phses Slve opertions with nother mster SPI device The ADSP-BF535 processor is n SPI mster for this interfce, supplying seril bit clock nd the chip select /CS to the AD7276 ADC. The processor receives dt on its MISO pin. Refer to Figure 2 for interfce detils. Figure 2. ADSP-BF535 SPI Interfce with AD7276 The ADSP-BF535 SPI nd AD7276 interfce cn be ccomplished using CPHASE=0, CPOL=1 mode s well s the CPHASE=1, CPOL=1 mode. These modes hve been tested with seril clock frequency of bout 6 MHz. The dvntge of CPHASE=0 mode over CPHASE=1 mode is tht CPHASE=0 mode cn be used with the DMA mode of opertion. For CPHASE=1 mode, the slve device select (PFx) must be sserted nd desserted mnully. For CPHASE=0 mode, the slve device select (/CS for AD7276) is controlled by the Blckfin processor s SPI hrdwre, nd hence, it is utomted. The code supplied long with this ppliction note includes core s well DMA SPI modes of opertion. In core nd DMA mode of SPI opertion, the SPI is configured for 16-bit word length by setting the SIZE bit in the SPI0_CTL register. CPHASE=0, CPOL=1 SPI Modes Core s well s DMA SPI modes of opertion re possible with CPHASE=0. Refer to Figure 3 for timing detils. In CPHASE=0, CPOL=1 mode, the received word must be right-shifted by 2 bits before being stored in internl memory. This is done becuse the lst 2 bits re zero. The dt is driven on the flling edge of the seril clock. The ADSP- BF535 SPI smples the dt on the seril clock's flling edges. The AD7276 converter's dt hold time specifiction enbles this scheme. Refer to Figure 4 for timing informtion regrding hold time. Interfcing AD7276 High-Speed Dt Converters to ADSP-BF535 Blckfin Processors (EE-245) Pge 3 of 6
Figure 3. CPHASE=0, CPOL=1 in Core Mode. Figure 4. CPHASE=0, CPOL=1 in Core Mode AD7276 Hold Time CPHASE=1, CPOL=1 SPI Modes When CPHASE=1, only core mode is possible s the device chip select must be controlled mnully. Refer to Figure 5 for timing informtion. In CPHASE=1, CPOL=1 mode, the received word must be right-shifted by 3 bits before being storing in internl memory. Since the SPI smples the seril dt on the seril clock's rising edge, the second bit ltched is not the second zero bit driven by the ADC. It is the first vlid MSB driven by the converter. Figure 5. CPHASE=1, CPOL=1 in Core Mode AD7276 Power-Down Mode AD7276/7277/7278 converters feture powerdown mode for power-sensitive designs. This llows power svings between conversions. To enter the power-down mode, the conversion process must be interrupted by desserting /CS between the second flling edge of SCLK nd the 10 th flling edge of SCLK. This feture is demonstrted in the ccompnying code, showing the DMA mode of opertion. Inside the DMA completion interrupt, the SPI is configured for n 8-bit dt word length. A dummy write is performed, ensuring tht the /CS is brought high before the 10 th SCLK. This drives the ADC into power-down mode. Figure 6. AD7276 Power-Down Mode Interfcing AD7276 High-Speed Dt Converters to ADSP-BF535 Blckfin Processors (EE-245) Pge 4 of 6
SPORT Interfce Detils The ADSP-BF535 processor hs two identicl synchronous seril ports (SPORTs) which support vriety of seril dt communictions protocols nd cn provide direct connection between processors in multiprocessor system. Ech SPORT is full-duplex device, cpble of simultneous dt trnsfer in two directions. Ech SPORT hs one group of pins (dt, clock, nd frme sync) for trnsmit opertion nd second set of pins for receive opertion. The receive nd trnsmit functions re progrmmed seprtely. The SPORTs cn be progrmmed for bit rte, frme sync, nd bits per word, by writing to memory-mpped registers. AD7276 ADCs cn be interfced to the ADSP- BF53x processor's seril port. The interfce works with both erly nd lte frme sync modes. The seril port is configured for internl frme sync nd internl seril port clock. Configure the seril port for 14-bit word length. Potentilly, this increses the A/D converter's throughput by not hving to pd two triling zero bits t the end of the 12-bit word. Since the SPORT is configured for 14-bit word length, bit shifting is not required, unlike the cse of SPI. Refer to Figure 7 for interfce detils. sync. Dt cn be smpled t the seril clock's rising or flling edges. Refer to Figure 8 for timing detils. Figure 8. SPORT Erly Frme Sync Option, Rising Clock Edge Smpling - Core Mode Lte Frme Sync Option When progrmmed for lte frme sync, configure the frme sync s n ctive low frme sync. Dt cn be smpled t the seril clock's rising or flling edges. Refer to Figure 9 for the timing detils. ADSP-BF535 SPORT RFS0 RCLK0 /CS SCLK AD7276 12-bit seril AD converter DR0 SDATA Figure 7. SPORT Interfce with AD7276 ADC The code supplied with this ppliction note includes both erly nd lte frme sync options. Erly Frme Sync Option When progrmmed for n erly frme sync, configure the frme sync s n ctive high frme Figure 9. SPORT Lte Frme Sync Option, Rising Clock Edge Smpling Core Mode Interfcing AD7276 High-Speed Dt Converters to ADSP-BF535 Blckfin Processors (EE-245) Pge 5 of 6
Summry As seen in this ppliction note, one cn interfce AD7276/7277/7278 ADCs to ADSP- BF535 Blckfin processors gluelessly nd use vriety of interfce methods nd modes. Appendix Refer to the code in the ttched ZIP file for vrious modes of opertion. References [1] ADSP-BF535 Blckfin Processor Hrdwre Reference Mnul. Rev 2.0, April 2003. Anlog Devices, Inc. [2] AD7276 Preliminry Technicl Dt Sheet. Rev PrF, June 2004. Anlog Devices, Inc. [3] ADSP-BF535 EZ-KIT Lite Evlution System Mnul. Rev 2.1, April 2003. Anlog Devices, Inc. Document History Revision Rev 1 October 04, 2004 by Aseem Vsudev Prbhugonkr Description Initil Relese Interfcing AD7276 High-Speed Dt Converters to ADSP-BF535 Blckfin Processors (EE-245) Pge 6 of 6