A Routing Algorithm for Flip-Chip Design

Transcription

1 A Rouing Algorihm for Flip-hip Design Jia-Wei Fang, I-Jye Lin, and Yao-Wen hang, Graduae Insiue of Elecronics Engineering, Naional Taiwan Universiy, Taipei Deparmen of Elecrical Engineering, Naional Taiwan Universiy, Taipei Absrac The flip-chip package gives he highes chip densiy of any packaging mehod o suppor he pad-limied Applicaion- Specific Inegraed ircui (ASI) designs. In his paper, we propose he firs rouer for he flip-chip package. The rouer can redisribue nes from wire-bonding pads o bump pads and hen roue each of hem. The rouer adops a wo-sage echnique of global rouing followed by deailed rouing. In global rouing, we use he nework flow algorihm o solve he assignmen problem from he wire-bonding pads o he bump pads, and hen creae he global rouing pah for each ne. The deailed rouing consiss of hree sages, cross poin assignmen, ne ordering deerminaion, and rack assignmen, o complee he rouing. Experimenal resuls based on seven real designs from he indusry demonsrae ha he rouer can reduce he oal wirelengh by 0.%, he criical wirelengh by.%, and he signal skews by.9%, compared wih a heurisic algorihm currenly used in indusry. Inroducion. Flip-hip Design Due o he increasing complexiy and decreasing feaure size of Very Large Scale Inegraion (VLSI) designs, he demand of more I/O pads has become a significan problem of package echnologies. Hence a relaively new packaging echnology, he flip chip (F) package, as shown in Figure, is creaed for higher inegraion densiy and rising power consumpion. Flip-chip bonding was firs developed by IBM in 960 s. I gives he highes chip densiy of any packaging mehod o suppor he pad-limied ASI designs. Flip-chip is no a specific package, or even a package ype (like PGA or BGA). Flip-chip describes he mehod of elecrically connecing he die o he package carrier. The package carrier, eiher a subsrae or a lead-frame, provides he connecion from he die o he ouside devices of he package. The die is aached o he carrier face up, and laer a wire is bonded firs o he die, hen looped and bonded o he carrier. In conras, he inerconnecion beween he die and carrier in he flip-chip package is made hrough a conducive bump ball ha is placed direcly on he die surface. Finally, he bumped die is flipped over and placed face down, wih he bump balls connecing o he carrier direcly. The flip-chip echnology is he choice in high clock speed applicaions because of he following advanages: reduced signal inducance (high speed), reduced power/ground inducance (low power), higher signal densiy, die shrink, reduced package fooprin, and lower hermal effec. However, in recen I designs, he I/O pads are sill placed along he boundary of he die. This placemen does no sui for he flip-chip package. As a resul, we use he op meal or an exra meal layer, called Re-Disribued Layer (RDL) as shown in Figure, o redisribue he wire-bonding pads o he bump pads wihou changing he placemen of he I/O pads. Since he RDL is he op meal layer of he die, he rouing angle in RDL canno be any-angle. Bump balls are placed on RDL and use he RDL o connec o wire-bonding pads by bump pads. Bump Top Meal Oher rouing under bump PASV(L) Redisribued Layer ore cells (Top Meal) M7 M IO buffer Wire-bonding Pad Die Bump Pad Figure : ross Secion of RDL Solder Ball Bump Ball Mold ap Rigid Laminae Figure : A Flip hip. A Flip hip Package. The flip-chip package is generally classified ino wo ypes: he peripheral array as shown in Figure and he area array as shown in Figure. In he peripheral array, he bump balls are placed along he boundary of he flip-chip package. The disadvanage of he peripheral array is ha we only have he limied number of bump balls. In he area array, he bump balls are placed in he whole area of he flip-chip package. The advanage of he area array is ha he number of bump balls is much more han ha of he peripheral array, so i is more suiable for modern VLSI designs. Since he flip-chip design is for high speed circuis, he issue of signal skews is also imporan. Thus a special rouer, he Redisribuion Layer (RDL) rouer [5], is needed o reroue he peripheral wire-bonding pads o he bump pads and hen connec he bump pads o he bump balls. onsidering he rouing of muli-pin nes and he minimizaion of oal wirelenh and he signal skews are also needed for an RDL rouer. Figure (c) shows one RDL rouing resul for an area-array flip chip.. Previous Work To he bes knowledge of he auhors, here is no previous work in he lieraure on he rouing problem for flip-chip

2 Die Bump Ball (c) Figure : A Peripheral Array. An Area Array. (c) An RDL Rouing Resul. designs. Similar works are he rouing for ball grid array (BGA) packages and pin grid array (PGA) packages, including [5], [], [], [], [6], [8] and [9]. The work [8] used he geomeric and symmeric aribues of he pin posiions in he BGA packages o assign pins of he BGA. However, in flip-chip designs he posiions of wire-bonding pads and bump pads do no always have hese geomeric and symmeric aribues. The works [5] and [] presened PGA rouers while [] provided a BGA rouer. These hree rouers are any-angle and muli-layer rouers wihou considering he pin assignmen problem. They did no consider single-layer rouing and oal wirelengh minimizaion. The works [6] and [9] applied he min-cos nework flow algorihm o solve he I/O pin rouing problems. All hese rouers focused only on rouabiliy and did no consider mulipin nes and signal skews. Furhermore, hey assumed ha wires can be any-angle, so heir mehods are no suiable for he RDL rouing, ypically wih 90-degree angle rouing.. Our onribuions To our bes knowledge, his paper is he firs work o propose an RDL rouer o handle he rouing problem of flip-chip designs wih real indusry applicaions. We propose a unified neworkflow formulaion o simulaneously consider he assignmen of he wire-bonding pads o he bump pads and he rouing beween hem. Our algorihm consiss of wo phases. The firs phase is he global rouing ha assigns each wire-bonding pad o a unique bump pad. By formulaing he assignmen as a maximum flow problem and applying he min-cos maximum-flow algorihm, we are able o guaranee 00% rouing compleion afer he assignmen. The second phase is he deail rouing ha efficienly disribues he rouing poins beween wo bump pads and assigns wires ino racks. In addiion o he radiional single-layer rouing wih only rouabiliy opimizaion, our RDL rouer also ries o opimize he oal wirelengh and he signal skews beween a pair of signal nes under he 00% rouing compleion consrain. Experimenal resuls based on seven real designs from he indusry demonsrae ha he rouer can reduce he oal wirelengh by 0.%, he criical wirelengh by.%, and he signal skews by.9%, compared wih a heurisic algorihm currenly used in indusry. The res of his paper is organized as follows. Secion gives he formulaion of he RDL rouing problems. In Secion, we deail our algorihm, including he global rouing and he deailed rouing. Secion shows he experimenal resuls. Finally, conclusions are given in secion 5. Problem Formulaion We inroduce he noaions used in his paper and formally define he rouing problem for flip-chip package. Figure shows he modeling of he rouing srucure of he flip-chip package. Le P be he se of wire-bonding pads, and B be he se of bump pads. For pracical applicaion, he number of bump pads is larger han or equal o he number of wire-bonding pads, i.e., B P, and each bump pad can be assigned o more han one wire-bonding pad. Le R b = {r,r b,..,r b m} b be a se of m bump pad rings in he cener of he package, and le R p = {r p,rp,..,rp k } be a se of k wire-bonding pad rings a he boundary of he package. Each bump pad ring ri b consiss of a se of q bump pads {bi,b i,..,b i q}, and each wire-bonding pad r p j consiss of l wire-bonding pads {p j,pj,..,pj l }. Le N be he se of nes for rouing. Each ne n in N is defined by a se of wire-bonding pads and a se of bump pads ha should be conneced. Thus n can be a muli-pin ne. Since he RDL rouing for curren echnology is ypically on a single layer, i does no allow wire crossings, for which wo wires inersecs each oher in he rouing layer. As shown in Figure, based on he wo diagonals of he flip-chip package, we pariion he whole package ino four secors: Eas = {P E,B E,Rp E,Rb E}, Wes = {P W,B W,Rp W,Rb W }, Souh = {P S,B S,Rp S,Rb S}, and Norh = {P N,B N,Rp N,Rb N }. For pracical applicaions, he wire-bonding pads in one secor connecs only o he bump pads in he same secor. Eas b r b r Wire-bonding Pad Norh b r Bump Pad Souh Diagonal p r Wes p r Figure : Four Secors in a Flip-hip Package. We define an inerval o be he segmen beween wo adjacen bump pads in he same ring ri b or he segmen beween wo adjacen wire-bonding pads in he same ring r p j. Given a flip-chip rouing insance, here are wo ypes of rouing, he monoonic rouing and he non-monoonic rouing. A monoonic rouing can be formally defined as he follows: Definiion A monoonic rouing is a rouing such ha for each ne n connecing from a wire-bonding pad p o a bump pad b,

3 n inersecs exacly one inerval in each ring ri b and exacly one inerval in each ring r p j. As showing in Figure 5, he nes n and n are monoonic roues. If we exchange he posiions of wo bump pads b and b, he rouing of n and n are non-monoonic rouing as shown in Figure 5. A good flip-chip package rouing should be a monoonic rouing because he monoonic rouing resuls in smaller oal wirelengh and higher rouing compleion, compared o he non-monoonic rouing. Global Rouing Two-pin Nes Handling Wire-bounding Pad lis Bump Pad Lis Ne Lis Add Inermediae Nodes & Tile Nodes onsruc Graph Deailed Rouing ross Poin Assignmen Ne Ordering Deerminaion Diagonal Ring Ring Ring Assign os and apaciy Track Assignmen Ring 6 Run Two-pin Nes Rouing Ring Muli-pin Nes? No Design Rule hecker Ring Muli-pin Nes Handling Yes Run Muli-pin Nes Rouing Diagonal Figure 5: Monoonic Rouing. Non-monoonic Rouing. Based on he definiion above, he rouing problem can be formally defined as he follows: Problem The single-layer flip-chip rouing problem is o connec a se of p P and a se of b B so ha no wire crosses each oher and he rouing is monoonic, he oal wirelengh is minimized, and he signal skew is minimized. The Rouing Algorihm In his secion, we presen our rouing algorihm. Firs we give he overview of our algorihm. Then we deail he mehods used in each phase.. Algorihm Overview According o he rouing flow shown in Figure 6, our algorihm consiss of wo phases: () he global rouing based on he mincos max-flow (MMF) algorihm [], and () he deailed rouing based on he cross poin assignmen, ne ordering deerminaion, and he rack assignmen. In he firs phase, we consruc four flow neworks G E, G W, G N, and G S, one for each secor, o solve he assignmen of he wire-bonding pads o he bump pads. Since we only have 0 Figure 6: The RDL Rouing Flow one layer for rouing, he assignmen should no creae any wire crossings. We avoid he wire crossings by resricing he edges in he neworks no o inersec each oher. We firs consider -pin nes and hen muli-pin nes. The reason is ha -pin nes have less freedom o choose he rouing pah, so i needs o be considered firs. Afer applying MMF, we obain he flows denoing he roues from wiring-bonding pads o bump pads for he nes. Those flows give he global pahs for he nes. In he second phase, we use he cross poin assignmen, ne ordering deerminaion, and he rack assignmen o achieve fas deailed rouing. A cross poin is he poin for a ne o pass hrough an inerval. Firs, we find he cross poins for all nes passing hrough he same inerval. For all nes ha pass hrough he same inerval, we evenly disribue hese cross poins. Second, we use he ne ordering deerminaion echnique presened in [7] o creae he rouing sequence beween wo adjacen rings so ha we can guaranee o roue all nes. Finally, we assign a leas one rack o each ne based on he rouing sequence obained from he ne ordering deerminaion algorihm. Figure 7 shows he overview of our rouing algorihm.. Global Rouing In his subsecion, we firs show he basic flow nework formulaion. Then we deail he capaciy of each edge, he inermediae nodes, he ile nodes, and he cos of each edge. Finally, we discuss how o handle he muli-pin nes... Basic Nework Formulaion We describe how o consruc he flow nework G S o perform he assignmen for he Souh secor. The oher hree secors can be processed similarly. As shown in Figure 8, we define D S = {d S,d S,..,d S h } o be a se of h inermediae nodes. Each inermediae node represens an inerval (b i x,b i x+) ((p j y,p j y+ )) in a bump pad ring (wire-bonding pad ring). T S = { S, S,.., S u} is a se of u ile nodes. Each ile node represens a ile (b i x,b i x+,b i+ x,bi+ x + ) ((pj y,p j y+,pj+ y,pj+ y + )) beween wo

4 Algorihm: RDL Rouing(P, B, N) P : se of all wire-bonding pads; B: se of all bump pads; N: se of all nes; begin onsruc four graphs G E, G W, G N, G S wih only -pin nes; Apply MMF o find he assignmen of each p P o b B 5 in he same secor and he global pah for each -pin ne; 6 Add addiional edges o represen he muli-pin ne in he 7 four graphs; 8 Apply MMF o find he assignmen of each p P o b B 9 in he same secor and he global pah for each muli-pin ne; 0 Find all cross poins in all inervals for each ne n N; for he ouermos ring r p i o he innermos ring rb j S Ne Ordering Deerminaion(); // S conains he rouing sequence; Assign rack(s); 5 end Bump Pad Wire-bonding Pad i+ b x ' i b x u d k i+ b x ' + i bx + j p y j p y ' Tile Node d l v j py + j p y ' + Inermediae Node b r i p r j D S B S E S P S T S Figure 7: Overview of he RDL Rouing Algorihm. adjacen bump pad rings (wire-bonding pad rings). We consruc a graph G S = (P S D S B S T S,E) and add a source node s and a arge node o G S. Each inermediae node has a capaciy, where represens he maximum number of nes ha are allowed o pass hrough an inerval. Each ile node has a capaciy L, where L represens he maximum number of nes ha are allowed o pass hrough a ile. We will deail how o handle he capaciy of he inermediae nodes and he ile nodes so ha MMF can be applied in Secion... There are eigh ypes of edges:. edges from a wire-bonding pad o a bump pad,. edges from a wire-bonding pad o an inermediae node,. edges from an inermediae node o a bump pad,. edges from an inermediae node o anoher inermediae node, 5. edges from an inermediae node o a ile node, 6. edges from a wire-bonding pad o a ile node, 7. edges from a ile node o a bump pad, and 8. edges from a ile node o an inermediae node. The source s has an edge o every node in P S, and here is an edge from every node in B S o he arge. Each edge is associaed wih a (cos,capaciy) uple o be described in he following subsecions. Recall ha we do no allow wire crossings for all wires. Since E represens he possible global pahs for all nes, we can guaranee ha no wire crossings will occur if here are no any crossings in edges. Thus, we consruc all he edges and avoid crossings of all edges a he same ime. Figure 8 shows an example flow nework G S for he Souh secor. We can solve MMF in ime O(V E ) []. Theorem Given a flow nework wih he verex se V and edge se E, he global rouing problem can be solved in O( V E ) ime. Figure 8: Inermediae Nodes and Tile Nodes. Flow Nework for he Souh Secor... apaciy Assignmen and Node onsrucion Now we inroduce he capaciy of each edge, he inermediae nodes, and he ile nodes. For an edge e, if e is from a wirebonding pad o a bump pad or an inermediae node or a ile node, he capaciy of e is se o. If e is from an inermediae node or a ile node o a bump pad, hen he capaciy of e is se o M, where M is he maximum number of nes ha are allowed o connec o he bump pad. Recall ha an inermediae node has he capaciy of, where is he maximum number of nes ha are allowed o pass hrough his inermediae node. This means ha he summaion of all ougoing edges of an inermediae node d is equal o. The same condiion holds for all incoming edges of d. As shown in Figure 9, in order o model his siuaion, we decompose each inermediae node d ino wo inermediae nodes d and d and an edge is conneced from d o d wih capaciy. All ougoing edges of d are now conneced from d wih capaciy, and all incoming edges of d are now conneced o d wih capaciy. In Figure 0, a ile node is also decomposed ino wo ile nodes and, and he capaciy of a ile node is se o L, where L is he maximum number of nes ha are allowed o pass hrough his ile node. The capaciy of he edges from he source node o he wire-bonding pads is se o, and he capaciy of he edges from he bump pads o he sink node is se o M. There are hree wors cases of congesion in a ile, as shown in Figure. The four nodes in he hree figures are all bump pads. In Figures and, he maximum number of nes passing hrough he ile is. In Figure (c), he maximum number of nes passing hrough he ile is. If we do no use he ile node, he maximum number of nes in Figures,, and (c) could exceed he capaciy of a ile ( > L or > L). Since he capaciy of each ile node is well modeled in our flow nework, we can oally avoid his congesion problem.

5 / / d d / os/apaciy d 0/ / Figure 9: apaciy and os on Inermediae Nodes. / L (c) / L Figure : Three inds of ongesion in a Tile. / L os/apaciy 0/ L / L Figure 0: apaciy and os on Tile Nodes... The os of Edges The cos funcion of each edge is defined by he following equaion: os = α WL, () where W L denoes he Manhaan disance beween wo erminals of an edge, and α is an adapive parameer o adjus he cos of differen ypes of edges. We assign he smalles α o he edge ha connecs an inermediae node and a bump pad o assure ha he inermediae nodes are assigned o bump pads firs. The edges which connec a ile node and a bump pad are also assigned he smalles α. The edge ha connecs wo inermediae nodes or an inermediae node o a ile node is assigned he larges α. By adjusing he value of α, we can conrol he wirelengh of each ne o avoid large signal skews beween differen nes. The cos of he edges from he source node o he wire-bonding pads and he cos of he edges from he bump pads o he sink node are boh se o 0. Figure shows he capaciy and cos for all four ypes of edges... Muli-pin Ne Handling Finally, we describe how o deal wih he muli-pin nes. As saed before, we firs assign he -pin nes and hen he muli-pin nes. We only consruc he edges ha are associaed wih he -pin nes and apply MMF for he assignmen. Afer he assignmen, we delee all edges from he source node s and all edges o he arge node. The global pahs of he -pin nes are no deleed and considered as he blockages F when we consruc he edges for he muli-pin nes. Recall ha if here are no edge crossings 0/ / / 0/ M / M / / 0/ M / M / M 7/ 6 s / / 0/ M / 8 / 5 0/ M 5 6/ 9/ M 0/ 0/ 0/ 0/ / / 0 Figure : apaciy and os on Edges. os/apaciy in he flow nework, hen here are no wire crossings in he final rouing soluion. When we consruc he edges for he muli-pin nes, an edge e exiss only if e does no inersec any blockages. Then we add he edges from he source node o he wire-bonding pads associaed wih he muli-pin nes and he edges from he bump pads associaed wih he muli-pin nes o he arge node. Figure illusraes an example. Assume ha a muli-pin ne n consiss of ((p,p,p 5 ),(b,b 9 )), which means ha p, p, and p 5 are free o be assigned o one of he wo bump pads b and b 9. Redundan edges are deleed by F i. For example, he edge from p o he inermediae node beween b 8 and b 9 is deleed because i inersecs he blockage (p,b 8 ). By using MMF, he wirebonding pads and bump pads are grouped ino wo ses: {p,b } and {p,p 5,b 9 }. Since MMF is opimal and we will never assign nes o exceed he capaciy of an inerval or a ile, we will never violae he design rules. Also because we do no allow edge crossings during flow nework consrucion, he final rouing soluion will no generae wire crossings. So afer he assignmen, all global pahs are rouable. Based on above discussions, we have he following heorem. 0/ D B E P T 5

6 Theorem Given a se of wire-bonding pads, a se of bump pads, and a se of nes, if here exiss a feasible soluion compued by he MMF algorihm, we can guaranee 00% rouing compleion. ross Poin 5 s Group : {p, b} Group : {p, p5, b9} Figure : Group Muli-pin Nes. D B E P Redundan Edge. Deailed Rouing In his subsecion, we deail he hree mehods used in our efficien deailed rouing. As shown in Figure, afer he global rouing, each global pah conains only wire-bonding pads, inermediae nodes, and bump pads. The wo global pahs < d k,,d l > and < d k,,b x > which pass rough he ile node are redefined ino < d k,d l > and < d k,b x >. Hence ile nodes are no needed for he final expression of he global pahs because a ile node is jus used o avoid he congesion of a ile. d k dl bx d k dl Figure : Redefined Global Pahs... ross Poin Assignmen Based on he global rouing resul (discussed in Secion.), we use he cross poin assignmen algorihm o evenly disribue each ne which passes hrough he same inerval. We use he example of Figure 5 o describe he process for he cross poin assignmen. As shown in Figure 5, he wo nes from wire-bonding pads p and p pass hrough he same inermediae node. So we spli he inermediae node ino wo cross poins. Theorem The cross poin assignmen problem can be solved in O( B + P R b R p ) ime. b x F i T D B F i T Figure 5: ross Poin Assignmen... Ne Ordering Deerminaion Afer he assignmen of cross poins, each ne has is pah o cross each inerval. For wo adjacen rings, we can rea i as a channel rouing. So we use he ne ordering deerminaion algorihm presened in [7] o generae a rouing sequence S =< (n s,n ),(n s,n ),..,(n s k,n k ) > wih k ne segmens. Each ne segmen n j is represened by a pair (source,arge) = (n s j,n j ). Firs, we generae a circular lis for all erminals ordered couner-clockwise according o heir posiions on he boundaries. Then, a sack is used o check if here exis crossovers among all ne segmens. For each erminal of ne n i, if i is a source, hen we push i ino he sack. Oherwise, if his erminal and he op elemen of he sack belong o he same ne, hen ne n i is mached. We keep searching he circular lis unil all nes are mached. Wih his sequence S, we can guaranee ha each ne segmen beween wo adjacen rings can be roued wihou inersecing each oher. For example, given an insance shown in Figure 6, according o he ne ordering deerminaion algorihm, we can obain he sequence S =< (n,n ),(n 0,n 0 ),(n 9,n 9 ),(n 8,n 8 ),(n 7,n 7 ),(n 6,n 6 ),(n 5,n 5 ), (n,n ),(n,n ),(n,n ) >. Theorem Given a se of nes N, he ne ordering deerminaion problem can be solved in O( N ) ime Rouing Sequence: {(, ), (0, 0), (9, 9), (8, 8), (7, 7), (6, 6), (5, 5), (, ), (, ), (, )} Blocking Poin 0 Track Figure 6: An example for Track Assignmen. Blocking Poin... Track Assignmen Wih he ne ordering, we can use maze rouing o roue all nes for any wo adjacen rings. However, maze rouing is quie slow. q Track 6

7 Algorihm: Track Assignmen(S j, L) S j: a rouing sequence beween ring r j and r j+; L: he maximum number of racks; begin for each ne segmen n i in S j Le (x s i, yi s ) ((x i, yi)) be he coordinae of he source (arge) of n i; 5 6 if ((x s i x i and yi s yi) or (x s i x i and yi s yi)) Find a rack l of L from he op o he boom wihou 7 creaing overlap of oher wires; 8 else 9 Find a rack l of L from boom o op wihou 0 creaing overlap of oher wires; if such l exiss assign l o n i; else for all pre-roued ne n k 5 divide ino wo segmens according o q k ; 6 assign he segmen no overlapping wih q k 7 o he lowes (highes) possible rack; 8 end Figure 7: Algorihm for Track Assignmen. Figure 8: RDL Rouing Soluion of fs900. (For example, for a small es case wih 5 nes, we need 5 minues o complee he deailed rouing.) So we propose a rack assignmen algorihm o assign racks o each ne segmen of any wo adjacen rings. For each ne segmen n i in S, according o he relaive locaions of n s i and n i, we search a rack o be assigned o n i from he op o he boom or from he boom o he op. We search he racks from he op o he boom if n s i is in he op-righ side of n i, or ns i is in he boom-righ side of n i. Oherwise, we search he racks from he boom o he op. If we find a rack l and i does no creae any overlap wih oher wires, hen we assign l o n i. As shown in Figure 6, n is assigned o rack firs, and n 5 is assigned o rack firs. Also we record he blocking poins Q for n i. A blocking segmen is a wire on rack l + (if we search from he op o he boom) or l (if we search from he boom o he op) o sop n i from being assigned o l + or l wihou creaing any overlap wih i. A blocking poin q i is a erminal of he blocking segmen whose projecion on l overlaps wih n i. As shown in Figure 6, he poin q on rack l is he blocking poin for ne n. If we canno find such l, we rip-up and reroue all ne segmens n o n i. For each ne n k o be reroued, we use he concep of he dogleg in he channel rouing o break a segmen ino wo segmens based on he blocking poin q k such as n in Figure 6. Then we assign he segmen ha will no overlap wih q k on he lowes possible rack (if we search from he op o he boom) or on he highes possible rack (if we search from he boom o he op). Afer assigning racks, we record he new blocking poins for n k. Noe ha since now each ne segmen may be assigned wih more han one rack, we may have more han one blocking poin for each ne. Figure 7 summarizes he rack assignmen algorihm. Theorem 5 Given a se of nes N and a consan number of racks L, he rack assignmen problem can be solved in O( N L( R b + R p )) ime. Experimenal Resuls We implemened our algorihm in he ++ programming language on a.ghz SUN Blade 000 worksaion wih 8 GB memory. The benchmark circuis fs90b70, fsa0ac0aa, fsa0ac05aa, fwaa8, fs900, fs6, and fs096 are real indusry designs. In Table, ase name denoes he names of circuis, #Nes denoes he number of nes, #R p denoes he number of wire-bonding pad rings, #p denoes he number of wire-bonding pads, #R b denoes he number of bump pad rings, and #b denoes he number of bump pads. In each of fs900, fs6, and fs096, he number of wire-bonding pads equals he number of bump pads. So each wire-bonding pad needs o be assigned o exacly one bump pad. Hence hese hree cases are more difficul for rouing han he oher four cases. Since here are no flip-chip rouing algorihms in he lieraure, we compared our algorihm wih he following heurisic algorihm currenly used in a design service company. This heurisic is called he neares node connecion (NN) algorihm. In NN, he wires are roued sequenially. If a wire-bonding pad p can find a free bump pad b in a resriced area of he neares bump pad ring rm, b hen i connecs p o b. If here are no free bump pads in rm, b hen we search for a free bump pad in he nex bump pad ring rm+. b This process is repeaed unil we find a free bump pad. The experimenal resuls are shown in Table. We repor he oal wirelengh, he criical wirelengh, he maximum signal skews, and he PU imes. Since he rouabiliy is guaraneed o be 00%, we do no repor i. ompared wih NN, he experimenal resuls show ha our nework flow based algorihm reduces he oal wirelengh by 0.%, he criical wirelengh by.%, and he signal skews by.9% in reasonably longer running ime. Noe ha for fs6 and fs096, NN s o find a rouing soluion. Figure 8 shows he RDL rouing resul of fs900. The experimenal resuls demonsraes he effeciveness of our nework flow based algorihm for he rouing for flip-chip designs. 7

8 ase name fs90b70 fsa0ac0aa # Nes (-pin/muli-pin) 66/0 657/ #Rp #p #Rb 7 7 #b 8 56 fsa0ac05aa 69/ fwaa8 5/ fs / fs6 6/ fs / Table : Tes ases for RDL Rouer. Algorihm Toal wirelengh (μm) riical wirelengh (μm) Skew PU ime (s) ase name NN Our mehod Improve men NN Our mehod Improve men NN Our mehod Improve men NN Our mehod fs90b % % % fsa0ac0aa % % 59 0.% fsa0ac05aa % % 58 9.% fwaa % % % fs % % % fs fs Average 0.%.%.9% Table : RDL Rouing Resuls. 5 onclusion In his paper, we have developed an RDL rouer for he flipchip package. The RDL rouer consiss of he wo sages of global rouing followed by deailed rouing. The global rouing applies he nework flow algorihm o solve he assignmen problem from he wire-bonding pads o he bump pads and hen creaes he global rouing pah for each ne. The deailed rouing uses cross poin assignmen, ne ordering deerminaion, and rack assignmen o complee he rouing. Experimenal resuls show ha our rouer can achieve much beer resuls in rouabiliy, wirelengh, criical wirelengh, and signal skews, compared wih a heurisic algorihm currenly used in indusry. References [] R.. Ahuja, A. V. Goldberg, J. B. Orlin, and R. E. Tarjan, Finding minimum-cos flows by double scaling, Mah. Program., vol. 5, pp. - 66, 99. [] R.. Ahuja, T. L. Magnani, and J. B. Orlin, Nework Flows: Theory, Algorihms, and Applicaions, Prenice Hall, Englewood liffs, N.J., 99. [] D. hang, T. F. Gonzalez, and O. H. Ibarra, A flow based approach o he pin redisribuion problem for muli-chip modules, Proc. GVLSI, pp.- 9, 99. [] B. cherkasssky, Efficien Algorihms for he Maximum Flow Problem, Mahemaical Mehods for he Soluion of Economical Problems, vol. 7, pp.7-6, 977. [5] S.-S. hen, J.-J. hen, S.-J. hen, and.-. Tsai, An Auomaic Rouer for he Pin Grid Array Package, Proc. ASP-DA, pp.-6, 999. [6] T. H. ormen,. E. Leiserson, and R. L. Rives, Inroducion o Algorihms. ambridge, MA: MIT Press, 000. [7].-P. Hsu, General River Rouing Algorihm, Proc. DA, pp , 98. [8] J. Hu and S. S. Sapanekar, A Timing-consrained Algorihm for Simulaneous Global Rouing of Muliple Nes, Proc. IAD, pp.99-0, 000. [9] enningon, Helgason, Algorihms for Nework Programming, John Wiley & Sons, 980. [0] Y. ubo and A. Takahashi, A Global Rouing Mehod for -Layer Ball Grid Array Packages, Proc. ISPD, pp.6-, 005. [] E. S. uh, T.. ashiwabara, and T. Fujisawa, On opimum single row rouing, IEEE Transacions on ompuer-aided Design of Inegraed ircuis and Sysems, vol. 6, pp. 6-68, 979. [] A. Tius, B. Jaiswal, T. J. Dishongh, and A. N. arwrigh, Innovaive ircui Board Level Rouing Designs for BGA Packages, IEEE Transacions on ompuer-aided Design of Inegraed ircuis and Sysems, vol. 7, pp , 00. [].-. Tsai,.-M. Wang, and S.-J. hen, NEWS: A Ne-Even-Wiring Sysem for he Rouing on a Mulilayer PGA Package, IEEE Transacions on ompuer-aided Design of Inegraed ircuis and Sysems, vol. 7, pp.8-89, 998. [] S.-S. hen, J.-J. hen,.-. Tsai, and S.-J. hen, An Even Wiring Approach o he Ball Grid Array Package Rouing, Proc. ID, pp.0-06, 999. [5] UM, 0.µm Flip hip Layou Guideline, pp.6, 00. [6] D. Wang, P. Zhang,.-. hang, and A. Sen, A Performance-Driven I/O Pin Rouing Algorihm, Proc. ASP-DA, pp.9-, 999. [7] X. Xiang, X. Tang, and D.-F. Wang, Min-os Flow-Based Algorihm for Simulaneous Pin Assignmen and Rouing, IEEE Transacions on ompuer-aided Design of Inegraed ircuis and Sysems, Vol., pp , 00. [8] M.-F. Yu and W.-M. Dai, Single-Layer Fanou Rouing and Rouabiliy Analysis for Ball Grid Arrays, Proc. IAD, pp , 995. [9] M.-F. Yu, J. Darnauer and W.-M. Dai, Inerchangeable Pin Rouing wih Applicaion o Package Layou, Proc. IAD, pp ,