FIELD PROGRAMMABLE GATE ARRAY (FPGA) AS A NEW APPROACH TO IMPLEMENT THE CHAOTIC GENERATORS

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1 FIELD PROGRAMMABLE GATE ARRAY (FPGA) AS A NEW APPROACH TO IMPLEMENT THE CHAOTIC GENERATORS Mohammed A. Aseeri and M. I. Sobhy Deparmen of Elecronics, The Universiy of Ken a Canerbury Canerbury, Ken, CT2 7NT, U.K. ABSTRACT In his paper, a new mehod is inroduced o implemen chaoic generaors based on he Henon map and Lorenz chaoic generaors given by he sae equaions using he Field Programmable Gae Array (FPGA). The aim of his mehod is o increase he frequency of he chaoic generaors. The new mehod is based on he MATLAB Sofware, Xilinx Sysem Generaor, Xilinx Alliance ools and Synpliciy Synplify. The oolbox of he Xilinx Sysem Generaor used as a oolbox under he MATLAB Simulink o conver any a MATLAB Simulink model o he Xilinx Sysem Generaor model hen o generae he VHDL code for ha model. The hardware can be used direcly in chaoic communicaion sysems wih high frequencies. 1. INTRODUCTION The Xilinx Sysem Generaor bridges he gap beween concepual archiecural design and he acual implemenaion in a Xilinx field programmable Gae Array (FPGA). The field programmable Gae Array (FPGA) is ype of programmable device. Programmable devices are a class of general-purpose chips ha can be configured for a wide variey of applicaions. They have capabiliy of implemening he logic of no only hundreds bu also housands of discree devices. The Sysem Generaor for Simulink, developed in parnership wih The Mah Works, Inc enables o develop highperformance DSP sysems for Xilinx FPGAs using he popular MATLAB /Simulink producs from The MahWorks, Inc [1]. As a plug-in o he Simulink modeling sofware, he Xilinx Sysem Generaor provides a bi-accurae model of FPGA circuis, and auomaically generaes a synhesizable Hardware Descripion Language (VHDL) code and a esbench. This VHDL design can hen be synhesized for implemenaion in Xilinx Virex -II, Virex, and Sparan -II FPGAs. The Xilinx Blockse enables bi-rue and cycle-rue modeling, wih Xilinx FPGA hardware as he arge. I includes parameric blocks for DSP, arihmeic, and logic funcions like FFTs, FIR Filers, Mulipliers, Memories, and gaeway blocks o communicae wih he MATLAB environmen, where you also have access o he exensive se of Simulink libraries [2]. Bu why we used FPGA insead of analogue circui? The answer is, Analogue chaoic generaors have been used for communicaion sysems [3]. Recovery of he informaion signal depends on how well he receiver is synchronised wih he ransmier. This requires ha he parameers of boh receiver and ransmier be mached o a high degree of accuracy. This requiremen is difficul o achieve in analogue sysems especially ha he values of analogue circui componen are funcions of age and emperaure. The mos obvious soluion is o implemen he generaors using digial hardware. The generaors are firs represened by a se of non-linear equaions and a sysembased model is developed o represen hese equaions direcly. The FPGA overcome of ha enire problem and in he same ime we can ge high frequency. Once he VHDL code generaed and synhesized hen he nelis file will produce, hen hrough he Xilinx Alliance ools he bi file will produce. Once he bi file available hen he impac sofware under he Xilinx Alliance ools [4] will use o download he bi file o arge FPGA device. By his way we can conrol he frequency of he chaoic signal during he FPGA device by using clock, so ha he frequency of he chaoic signal depends on he frequency of he clock for he FPGA device. The main hing he oupu from he FPGA device is digial. To see he analogue oupu we need Digial o analogue (D/A) converer device. In his case he frequency of he sysem depends on he clock sampling rae and he sampling rae of he D/A device and he numbers of D/A bis. The presened mehod is depended on he Xilinx Sysem Generaor, which conver a Simulink model from MATLAB o VHDL code. 2. DESIGN AND IMPLEMENT THE XILINX HENON MAP CHAOTIC GENERATOR In his paper, we design chaoic generaor model using FPGA based on he Henon map and Lorenz chaoic sysems. The seps of he FPGA design are as follows:

2 Develop a sysem model from he sae equaions using he MATLAB Simulink Sofware [4]. Simulae he model o adjus he required frequency. Conver all models by using he Xilinx Sysem Generaor blockse. Run he Simulink model wih he Xilinx Sysem Generaor blockse and compare he resuls wih he model wihou using he Xilinx sysem Generaor blockse. Generae he sysem generaor model o generae avhdl code. Synhesis he VHDL code by using eiher Leonardo specrum or Synpliciy Synplify [5] o produce he nelis file, which we need i o produce he bi file during he Xilinx Alliance ools. Pass a nelis file hrough implemenaion ools Xilinx Alliance ools o generae he bisream file. Download he bisream file on he arge FPGA chip using he PC parallel por. x y n+ 1 = 1 n+ 1 = bx + y n n ax where a and b are consans and a=-1.4 and b=0.3. Simulink hen o Xilinx Sysem Generaor model and he oupu is conrolled by he clock ime which is he sep size of he simulaion. Fig.1 shows he model of he Xilinx Henon map chaoic generaor. To make synchronizaion for he Xilinx Henon map chaoic generaor blocks all he number of bis equals 32 and he binary of he poins equal o 18. The simulaion resuls of he Xilinx Henon map chaoic generaor are shown in Fig.2. The xn-yn aracor of he simulaion resuls is shown in Fig.3. The maximum frequency can be achieved by changing he clock of he simulaion. Here we choose he clock =0.5 x10-10 he maximum frequency can be achieved is 1.00 GHz as shown in Fig.4. Then he VHDL code is generaed using he Xilinx Sysem Block. The Synpliciy Pro is used o produce he nelis file of he VHDL code hen generaed he bi file using he Xilinx Alliance ools. The bi file can be downloaded using he parallel por o he FPGA chip. The hardware resuls are shown in Fig.5. The measured aracor is shown in Fig.6. The maximum frequency can be achieved in his case 5 MHz as shown in Fig.7. 2 n (1) Fig.1 Simulaion model of he Xilinx Henon map chaoic generaor. The sae equaions of he Henon map chaoic generaor convers o a Simulink model using he MATLAB The sae equaions of he Henon map chaoic generaor are given by [6]

3 Fig.2 The Simulaion oupu of he Xilinx Henon map. Fig.5 The measured oupu of he Xilinx Henon map. Fig.3 The simulaion Aracor. Fig.6 The measured aracor Fig.4. The simulaion specrum. Fig.7 Specrum of he Henon map oupu.

4 Fig.8 Simulaion model of he Xilinx Lorenz chaoic generaor. 3. DESIGN AND IMPLEMENT THE XINLINX LORENZ CHAOTIC GENERATOR. Lorenz's equaions are acually hree differenial equaions, a firs order equaion for each of he u, v, and w componens of he rajecories posiion. They are given as [7]: u( ) = A v( ) = B 0 ( v( ) u( )) d u( ) d w ( ) = 5 [ u( ) v( )] d C w ( ) d 0 0 v( ) d u( ) w ( ) d (2) where A, B and C are parameers ha change he behaviour of he sysem. In his case he consans A, B and C were defined as A = 10, B = 28 and C = Similar o he Henon map chaoic generaor echnique he Lorenz sae equaions are convered o SIMULINK MATLAB hen o Xilinx Sysem Generaor model as shown in Fig.8. The model is esed using he simulaion ime saring from 0 o 10 2 and he clock sep size is The simulaion oupus are shown in Fig.9. The Lorenz generaor aracors are ploed using he x-y-z sae variables as shown in Fig.10. The frequency band for his model is conrolled by changing he clock sep ime of he model d where he value of he gain before every inegraor equals As an d example of he changeable band frequency, he simulaion ime is adjused o sar from 0 o 10 4 x d and he clock sep size d=10-2. Fig.11 shows he specrum resuls of he simulaion model of he Lorenz chaoic generaor, which shows he effec on frequency band when he clock sep ime is changed. Then he VHDL code is generaed using he Xilinx Sysem Block. Also he Synpliciy Pro is used o produce he nelis file of he VHDL code hen generaed he bi file using he Xilinx Alliance ools. The bi file can be downloaded using he parallel por o he FPGA chip. The hardware resuls are shown in Fig.12. The measured aracor is shown in Fig.13. The maximum frequency can be achieved in his case 2.50 MHz as shown in Fig.14.

5 Fig.9 Simulaion oupus of Lorenz chaoic. Fig.12 Measured x sae variable. Fig.10 The Aracors of Lorenz chaoic. Fig.13 The Measured aracor. Fig.11 The specrums of Lorenz chaoic. Fig.14 Specrum of x sae variable.

6 4. CONCLUSION A new mehod o design and implemen he chaoic generaor models in real ime is inroduced which is capable of implemening he chaoic sysems ha are given by sae equaions in real ime using Field Programmable Gae Array (FPGA) sysem. The mehod is implemened by MATLAB, SIMULINK, Xilinx Sysem Generaor, Xilinx Alliance ools, Leonardo specrum or Synpliciy Synplify. A clock ime d (he simulaion sep size) o conrol he frequency band is used in his ype of chaoic generaor. The mehod is useful o implemen he chaoic generaors a high frequencies depends on he clock pulse of he hardware and he number of bi of he model and he digial o an analogue converer. Boh coninuous and discree chaoic generaors can be implemened even if he sysem canno be represened by a physical elecronic circui. Modificaion of any sysem is a simple change in he block diagram or he parameer values wihin he block. The randomness appeared in he aracor of he Henon map chaoic generaor due o using he digial o an analogue converer of eigh bis o represen he oupu. If he digial o analogue converer of 32 bis is used o represen he x n sae variable by his numbers of bis he aracor well be he same as in he simulaion. REFERENCES [1] P. Marchand, Graphics and GUIs wih MATLAB: CRC Press, [2] The MahWorks and Xilinx Plans web page: hp:// index.shml [3] T. Masumoo, Chaos in elecronic circuis, Proc. of he IEEE, vol. 75, No. 8, pp , Aug [4] Xilinx Alliance ools web page: hp:// age.jsp?ile=ise+alliance. [5] The Synpliciy s Synplify web page: hp:// [6] M.I. Sobhy, M. A. Aseeri and A. Shehaa, Real ime implemenaion of chaoic models using digial hardware, AMREM 2002, HPEM 13, June [7] L. Pivka, C. W. Wu and A. Huang, Lorenz equaion and Chua s equaion, In. J. of Bifurcaion and Chaos, vol. 6, No. 12B, pp , 1996.