Y. Tsiatouhas. VLSI Systems and Computer Architecture Lab

Transcription

1 CMOS INEGRAED CIRCUI DESIGN ECHNIQUES Universiy of Ioannina Clocking Schemes Dep. of Compuer Science and Engineering Y. siaouhas CMOS Inegraed Circui Design echniques Overview 1. Jier Skew hroughpu Laency 2. Pipeline srucures 3. Clocking schemes 4. Skew oleran design 5. Slack Borrowing 6. ime sealing VLSI Sysems and Compuer Archiecure Lab 1

2 Clock Jier Clock Skew Clock Jier Clock jier is a emporal variaion (uncerainy) of he clock period a a given poin in he chip. he clock period can reduce or expand on a cycle by cycle basis. Clock jier is he inheren inaccuracy of he clock generaion circuiry (e.g. PLLs). Clock Skew Clock skew is a variaion on he arrival ime of a clock signal ransiion due o mismaches and process variaions in he clock pahs and differences in he clock load. Clock skew is he clock inaccuracy inroduced by he clock disribuion nework. Clock skew is consan from cycle o cycle. Clocking Schemes 3 hroughpu Laency Merics for he performance evaluaion of circuis / sysems. hroughpu hroughpu (παραγωγικότητα) is defined as he processing rae of he inpu daa by he circui / sysem. Equivalenly, i is he daa ransfer rae inside he circui. hroughpu is relaed o he clock frequency (clock cycle). Laency Laency (λανθάνων χρόνος) is defined as he ime required by he circui / sysem o complee a compuaion. In case ha he required compuaion ime is available inside a clock cycle, hen laency and hroughpu are conversely proporional beween each oher. Clocking Schemes 4 2

3 Pipeline Srucures Clocking Schemes 5 Pipeline Srucures Ι a Iniial Design a Pipeline Design + log Ou + R R R log R Ou b b min, org c q p_add p_abs p_log su min, pipe c q max p_add,p_abs,p_log su in case ha hen p_add min,pipe p_abs min,org p_log 3 Clocking Schemes 6 3

4 Pipeline Srucures ΙΙ D 0 Q 0 D 1 D 2 D 3 D 4 Q 4 Sage Sage Sage Sage IF ID EX MEM r Regiser Regiser r Q1 Regiser r Q2 Regiser r Q3 r Regiser IF ID EX MEM Clock cycles s Operaions Insrucions IF ID EX MEM IF ID EX MEM IF ID EX IF ID MEM EX Clocking Schemes 7 Single Phase Maser Slave Clocking I Regiser Single Phase Maser Slave D Flip FlopFlop Saic Inpus Oupus Posiive edge riggered D Clocking Schemes 8 4

5 Single Phase Maser Slave Clocking II Clock Cycle Boundary Inpus Oupus c q seup skew logic Available ime for Evaluaion: logic cq seup skew overhead Clocking Schemes 9 Overhead Impac in Pipelines Inpus logic Oupus ' ' l oall ' N sages Inpus N 1 N Oupus logic l oall N... logic overhead laency N logic loall N overhead Clocking Schemes 10 5

6 Single Phase Double Edge Clocking Concurren Regiser and Subsequen Acivaion Regiser Posiive Edge riggered Maser Slave D Flip FlopFlop Posiive or Saic Inpus Oupus Regiser Negaive Edge riggered Maser Slave D Flip FlopFlop Negaive or Saic Clocking Schemes 11 Single Phase wo Level Clocking Concurren and Subsequen Regiser Acivaion Regiser Posiive Level Lach Negaive or Saic Inpus Laches Laches Laches Laches Oupus Skew relaed clock signals overlap in subsequen laches, may resul in flushhrough problems. Regiser Negaive Level Lach Posiive or Saic Clocking Schemes 12 6

7 Single Phase wo Level Clocking Concurren Regiser and Subsequen Acivaion Regiser Posiive Level Lach Posiive or Saic Inpus Laches Laches Laches Laches Oupus! Regiser Negaive Level Lach Negaive or Saic Clocking Schemes 13 Muli Phase Clocking wo Phase Clocking In wo phase clocking sysems wo discree clock phases are uilized, which are generaed by he main clock signal a he las level of he clock disribuion nework. Overlapping clock signals can be used or no. In he firs case higher speeds can be achieved a he risk of increased signal inegriy problems due o skew relaed issues in he clock disribuion. Four Phase Clocking Four phase clocking sysems uilize four discree clock phases. In general, design echniques wih more han wo phases are no very common in sysem developmen. Clocking Schemes 14 7

8 Skew oleran Saic Circuis Lach memory low! Laches Laches _B _B d q d q Available ime for Evaluaion: logic 2 dq Clocking Schemes 15 Skew oleran Domino Circuis I Sandard Design low! Laches Laches low! _B d q _B d q skew skew Available ime for Evaluaion: logic 2 dq 2 skew Clocking Schemes 16 8

9 Skew oleran Domino Circuis II Wave Pipeline Design low! phase 1 phase 2 Available ime for Evaluaion: logic overlap ime! Clocking Schemes 17 Slack Borrowing In he slack borrowing echnique, a logic pariion uilizes ime lef over (slack) by he previous pariion. By definiion his addiional ime is auomaically (volunarily) surrendered wihou circuiry and/or clock arrival ime adjusmens. his echnique is suiable for use in logic wih wo phase, wo level clocking (lach based)designs. Cycle slack borrowing: permis logic o use more han one cycle ime and sill fi wihin a single clock cycle boundary while mainaining he overall machine cycle ime. he ime used for logic evaluaion exceeds one cycle and he machine sill works a speed. he slack ime is borrowed from preceding cycle(s). Phase slack borrowing: permis logic o use more han one phase ime and sill mainain he overall machine cycle ime. he ime used for logic evaluaion in a clock phase exceeds he clock phase ime and he machine sill works a speed. he slack ime is borrowed from preceding phase(s). Clocking Schemes 18 9

10 ypical Operaion wo level double phase clocking Lach low! Clock Cycle Lach Boundary phase boundary phase boundary Evaluaes in Evaluaes in phase ime phase ime a b b c e d e S2a S2 S2b S1a S1 S1b phase ime phase ime Clock Cycle phase ime c sable a sable b sable d sable e sable S2 S1 Clocking Schemes 19 wo level double phase clocking Lach low! Slack Borrowing Evaluaes in phase ime Clock Cycle Lach Boundary phase boundary Evaluaes in phase ime phase boundary Evaluaes in phase ime a b c d e f g S2a S2 S2b S1a S1 S1b a sable phase ime Slack ime Cycle Borrowing S2a phase ime Clock Cycle phase ime d sable b sable c sable e sable S2b S1a f sable g sable S1b Slack ime slack Clocking Schemes Phase Borrowing 20 10

11 Slack Borrowing: Clocking Issues (I) Cycle Slack Borrowing he logic propagaion delay wihin a clock cycle lach boundary is: dcycle S2a S2b S1a S1b he clock cycle ime is: cycle S2b S1a S1b slack he ime difference beween he clock cycle lach boundary and he clock cycle ime, is: dcycle cycle S2a slack S2a(max) dcycle(max) cycle cycle Clocking Schemes 21 Slack Borrowing: Clocking Issues (II) Phase Slack Borrowing he logic propagaion delay wihin an phase lach boundary is: dphase S2a S2b he phase cycle ime is: p S2b S1a he ime difference beween he phase lach boundary and he phase cycle ime, is: dphase p S2a S1a S1a(max) S2a(max) dphase(max) cycle cycle cycle Clocking Schemes 22 11

12 Dead ime and Lach Relaunch Penaly Lach low! Evaluaes in phase ime Clock Cycle Lach Boundary phase boundary Evaluaes in phase ime phase boundary e a b c d S2a S2b S1a S1b f Evaluaes in phase ime g S a sable phase ime S2a b sable phase ime Clock Cycle phase ime d sable Dead ime c sable e sable g sable S2b S1a f sable relaunch_penaly clock_jier + clock_skew Clocking Schemes 23 Lach low! Phase Pariioning Clock Cycle Lach Boundary phase boundary phase boundary Evaluaes in Evaluaes in phase ime phase ime Evaluaes in phase ime e f a b c d g S2a S2b S1a e S2 a S2 bs a sable phase ime S2a b sable phase ime Clock Cycle phase ime Dead ime d sable c sable e sable g g sable S2b S1a S2 a S2 b f sable Slack Available for Clocking Schemes Cycle Borrowing 24 12

13 ime Sealing In he ime sealing echnique, a logic pariion gains evaluaion ime by aking (sealing) i from he nex clock cycle. I is suiable for use in dynamic logic wih wo phase clocking or in logic wih single phase maser slave clocking. he addiional ime is involunarily surrendered and i is obained by adjusing he clock edges arrival imes. Cycle ime sealing: permis logic o use more han one cycle ime and sill fi wihin a single clock cycle boundary while mainaining he overall machine cycle ime. he ime used for logic evaluaion exceeds one cycle and he machine sill works a speed. he ime is solen from he subsequen cycle. Phase ime sealing: permis logic o use more han one phase ime and sill mainain he overall machine cycle ime. he ime used for logic evaluaion in a clock phase exceeds he clock phase ime and he machine sill works a speed. he ime is solen from he subsequen phase. Clocking Schemes 25 wo Phase ypical Lach low! Cycle Boundary 1 Cycle Boundary 2 a Dyn b c d e f g h i Dyn Dyn Dyn Dyn j k Precharges Cycle ime 1 Evaluaes Cycle ime 2 Lach Closed Lach Open (Memory) (ransparency) 2 Evaluaes Precharges Lach Open (ransparency) Lach Closed (Memory) Phase ime Phase ime 0.5 cycle 0.5 cycle 0.5 cycle 0.5 cycle 0.5 cycle wo phase clocking dynamic logic (non overlapping clocks) Clocking Schemes 26 13

14 ime Sealing I Lach low! Cycle Boundary 1 Cycle Boundary 2 a Dyn b c Dyn d e Dyn f g Dyn h i Dyn j k Cycle ime 1 Modified Clocks Cycle ime 2 2 Phase ime Sealing Evaluaion Overlap Cycle ime Sealing * cycle cycle 0.7 cycle 0.5 cycle 0.3 cycle 0.5 cycle Dead ime wo phase clocking dynamic logic Clocking Schemes 27 ime Sealing II Overlap Fixing Cycle Boundary 1 Cycle Boundary 2 a Dyn b c Dyn d e Dyn f g Dyn h i Dyn j k 1 2 Cycle ime 1 Modified clocks Cycle ime Original Edges Phase ime Sealing Cycle ime Sealing 0.5 cycle 0.7 cycle 0.5 cycle 0.3 cycle 0.5 cycle wo phase clocking dynamic logic Clocking Schemes 28 14

15 ime Sealing Maser Slave Flops Cycle 1 Cycle 2 Cycle 3 p Flops Flip a b c d e aic s p Flops Flip aic s p Flops Flip aic s f p Flops Flip g Modified clock Cycle 1 Cycle 2 Cycle 3 Cycle ime Sealing a b c d e f g cycle cycle 1.2 cycle 0.8 cycle cycle Saic logic wih single phase edge riggered (maser slave flip flop) clocking Clocking Schemes 29 References High Speed CMOS Design Syles, K. Bernsein e al, Kluwer, Skew oleran Circui Design, D. Harris, Morgan Kaufmann Pub., Digialg Inegraed Circuis: A Design Perspecive,, J.M. Rabaey, A. Chandrakasan and B. Nikolic, Prenice Hall, CMOS VLSI Design: A Circuis and Sysems Perspecive, N. Wese and D. Harris, Addison Wesley, Clocking Schemes 30 15