A time-space consistency solution for hardware-in-the-loop simulation system

Transcription

1 Inernaional Conference on Advanced Elecronic Science and Technology (AEST 206) A ime-space consisency soluion for hardware-in-he-loop simulaion sysem Zexin Jiang a Elecric Power Research Insiue of Guangdong Power Grid Co.Ld., Guangzhou, P.R.China. CSG KEY Laboraory of Power Grid Auomaion, Guangzhou, P.R.China. Absrac. Time-Space consisency is criical while designing hardware-in-he-loop simulaion (HILS) sysem, due o he HILS sysem s Real-Time performance need. We find ou ha s in HILS sysem can be classified ino wo ypes -- posiive and passive one. And only he posiive would generae Time-Space inconsisency problem. Then, we deeply analyses hree differen phenomena of Time-Space inconsisency generaed by he posiive. A sae mapping soluion is proposed and used in pracise HILS projec. Keywords: Hardware-In-he-Loop Simulaion (HILS); Time-Space inconsisency; access proxy mechanism (DAPM); sae mapping (DSM) soluion. Inroducion Hardware-in-he-loop simulaion (HILS) means s can access o he simulaion sysem and inerac wih i. Compared wih he pure mahemaical simulaion, HILS is more credible and closer o he real world. HILS is widely used o es and verify new sysem. Ref [] and Ref [2] inroduce various HILS applicaions. From ime slo perspecive, he essenial characerisic beween HILS sysem and non-hardwarein-he-loop simulaion (non-hils) sysem is ha: HILS sysem needs o guaranee is real-ime simulaion (RTS) capabiliy while he non-hils does no. RTS means he ime in he simulaion sysem (ermed simulaion ime or logical ime) needs o synchronize wih he ime in he real world (ermed wall clock ime). Because s work in he real world and we are unable o change he real world s clock. On he conrary, models work in he virual simulaion world and we can regulae heir ime advance speed. Viewed from he relaionship beween he simulaion ime and he wall clock ime, here are wo ypes of simulaion sysem faser han real-ime simulaion (FRTS) and slower han real-ime simulaion (SRTS). FRTS defines when he simulaion ime runs faser han he wall clock ime, and SRTS defines he simulaion ime runs slower han he wall clock ime. Paricularly, when he simulaion ime runs synchronize wih he wall clock ime, we called real-ime simulaion (RTS). Le us define r = simulaion ime / wall clock ime, which is he raio of simulaion ime - wall clock ime. This raio represens he sizes of he simulaion ime lapse in a uni wall clock ime. Hence, we has r= for RTS, SRTS for 0<r<, and FRTS for r>. a Corresponding auhor : jiangzexin-08@singhua.org.cn 206. The auhors - Published by Alanis Press 20

2 In FRTS sysem, we can slow down simulaion ime advance speed and guaranee evens causal relaionship order o make r=. Opposiely, SRTS sysem is usually difficul o accelerae is simulaion ime unless o opimize he simulaion sysem s performance. Hence, RTS sysem denoes he simulaion ime can runs equal wih or faser han he wall clock ime. Tha includes wo aspecs capabiliy: one is he simulaion ime advance efficiency in he simulaion sysem, he oher is he capabiliy o real-imely deal he messages come from s ou of he simulaion sysem. As o he firs aspec, references [3-6] are mosly aiming o solve his problem. Their mainly ideas are giving an efficien ime managemen algorihm. Especially in he disribued HILS sysem, here are wo ypes of ime managemen algorihm: Termed conservaive ime synchronizaion algorihm and opimisic ime synchronizaion algorihm. As o he second aspec, he capabiliy of real-imely dealing he messages from s is ignored in hese proposed works. This real-imely dealing message capabiliy depends on simulaion sysem s messages ackle hroughpu and s messages generae hroughpu. Our main conribuion is o deeply analyse hese phenomena and proposes a proper soluion o ackle i. Firs of all, we found ou ha s can be divided ino wo ypes: -- posiive and passive one. Time-space inconsisency problem is prone o be happened when posiive s access o he simulaion sysem. On he conrary, i is easy o keep ime and space consisency when passive s access o he simulaion sysem. Due o passive s never send messages o simulaion sysem before simulaion sysem sends messages o hem. 2 Device access proxy mechanisms Device access proxy mechanism (DAPM) is proposed in reference [], which is wih he virualrealiy inerchange principle. Assume simulaion sysem conains hree modules A, B, C. Each module runs wih a simulaion model or a. Wih DAPM, i is ransparen o model in module A wheher Access proxy in module B connecs o model or. Tha is o say, models in he simulaion sysem canno feel wheher hey are communicaing wih real or virual model, jus like Turing inelligen esing. DAPM provides a mechanism for various hardware s o access o simulaion sysem. Module A Model module B Access proxy module C Access proxy model model inerface Inerface Figure. Diagram of DAPM 2

3 DAPM presens a good approach o implemen HILS. Bu he Time-Space inconsisency problem in HILS sill exiss. And we are focus on solving he Time-Space inconsisency problem by giving a deail inner implemen of access proxy. 3 Time-space inconsisency problem Due o s work in he real world and run wih he wall clock ime coordinae, he sae in s keep simulaneously along he wall clock ime. Simulaion models in he virual world are running wih he virual simulaion ime coordinae. In HILS sysem, we need o synchronize he wall clock ime wih he virual simulaion ime (also ermed logical ime), and hence he simulaion ime advance speed can keep consisen wih he wall clock ime, so he HILS sysem works. In HILS sysem, s send messages o he simulaion sysem and hey would receive messages from he simulaion sysem as well. Message conains a imesamp aribue. As o message sen o he simulaion sysem by s, he imesamp can only be referenced o he wall clock ime. In he conras, as o message from he simulaion sysem (especially in HLA), is imesamp can only be referenced o he simulaion ime. Normally, in RTS sysem, simulaion ime advance speed in simulaion sysem equals wih he speed of wall clock ime lapse, and so messages sen from s can be real-imely received and deal by simulaion sysem. In his case, he sae and is corresponding wall clock imesamp of s keep consisen beween real world and simulaion sysem. However, when a simulaion process in simulaion compuer occurs o suddenly pause or emporary sop, he simulaion virual ime pause while he wall clock real one coninue. The sae and is corresponding imesamp in s could no keep consisen beween real world and simulaion sysem. In order o analyse his problem deeply, we would like o classify s ino wo ypes shown as Fig.2. Simulaion sysem Simulaion sysem msg msg2 msg passive posiive Figure 2. Classificaion of s Passive s refer o hose s ha only send response message msg 2 o simulaion sysem when hey received reques message msg. Such as moors. Posiive s refer o hose s ha auomaically periodically send message o he simulaion sysem wihou any moivae ou from he simulaion sysem, such as same acive sensors. As o passive s, wheher simulaion sysem processes run fas or no, he imesamp of msg and he imesamp of msg 2 ( for msg and 2 for msg 2 ) always be < 2. Msg 2 could be considering being he sae of s when simulaion ime is 2. And s sae and is corresponding imesamp can be perceived wih lile deviaion in he simulaion sysem. As o Posiive s, assume s acively periodiciy send msg o repor heir sa every Δ. However, simulaion sysem can feel he laes sa of s only when he received he msg and deal i. Suppose s send message msg i (i=,2,,n) over a period of ime, and heir corresponding wall clock imesamp in he real world is, +Δ, +2Δ, +(n-) Δ, while heir corresponding simulaion sysem receive ime (simulaion ime) in he virual world is si (i=,2,,n). In normal RT 22

4 simulaion siuaion s(i+) - si =Δ, in oher word, s sae in simulaion sysem keep synchronized wih i in he real word. In abnormal siuaion, if simulaion sysem processes occur o suddenly pause wih wall clock ime inerval δ or emporary sop a si +Δ, hree phenomena of ime-space inconsisen appear. 3. Device messages los phenomenon Assume no messages recepion buffer in access inerface, messages from could be los in he period of simulaion sysem pause of δ. The simulaion sysem misses hose messages and simulaion experimen fails. Take δ = 2Δ as an example, he wall clock ime - simulaion ime relaionship diagram shown as Fig.3. Msg 3 and msg, which are essenial o he simulaion such as ele conrol commands or key sa messages, were los during δ, and he simulaion experimen canno simulae he rue resuls even he opposie resuls. + s simulaion ime msg 7 + s 3 + s 2 msg 5 msg 6 s + msg 2 s msg Wall clock ime Figure 3. Message loss phenomenon diagram 3.2 Device messages lag phenomenon Assume messages recepion buffer (FIFO Queue Buffer) was seup by access inerface in simulaion sysem and s ouside simulaion sysem send messages period wih an inerval ime of Δ. In he real world, messages were sen wih Δ wall clock ime inerval, ha is msg w(n+), msg wn and w(n+) - wn =Δ. In he simulaion world, messages were received and labelled wih si separaely, si means he simulaion ime a he momen when he messages were received. And we could no simply le w = si, due o he causal sequence of evens would be confused in he simulaion sysem [3-6]. w(i+) - wi =Δ si : msg receive a si msg N msg 2 msg msg N+ Peroidly sending wall clock ime wi FIFO Queue Buffer simulaion sysmem simulaion ime si Figure. FIFO in simulaion sysem diagram 23

5 Assume simulaion imesamp of messages are increased by Δ from he imesamp of he laes one. This case is shown as Fig.5, during some reason of pause wih δ, simulaion sysem does nohing in +Δ ~ +3Δ. Unforunaely simulaion sysem a +Δ (he wall clock ime) would deal msg 5 and i deals msg 3, so he simulaion sysem lag o recognize he real one wih 2Δ. Once he sudden pause momen occur frequenly, he expendiure of wall clock ime wih doing nohing would accumulae and ime-space inconsisen phenomenon appear. In fac, i is unwise o mark he simulaion imesamp of msgi+ wih he simulaion imesamps of msg i +Δ (ha is si+ = si +Δ). Once he simulaion sysem performs faser han he real world, i will receive pas messages and is simulaion causal relaionship would be confused. However, if si+ si +Δ, he hird ime-space inconsisen phenomenon appear. + s Simulaion ime msg 5 + s 3 + s 2 msg 3 msg s + msg 2 s msg Wall clock ime Figure 5. Message lagged deal scenario diagram 3.3 Simulaion canno advance phenomenon Assume messages recepion buffer (FIFO Queue Buffer) was seup by he access inerface in simulaion sysem and s ouside simulaion sysem send messages arbirarily. In he real world, messages were sen wih disorder wall clock ime. In he simulaion world, messages were received and we could only label hem wih si separaely, si means simulaion ime a he momen when he message was received. In normal circumsances, due o simulaion ime advances synchronously wih wall clock ime, HILS performs well. This case is shown as Fig.6, during some reason of pause wih δ, simulaion sysem does nohing in +Δ ~ +3Δ. Unforunaely he simulaion sysem a +Δ (he wall clock ime) would receive and deal msg 5, i receives and deals messages in he FIFO Queue buffer orderly. Once he simulaion sysem canno finish all messages in he buffer before +5Δ, messages in he queue buffer may increase. They will be labelled wih he curren simulaion imesamp and so he simulaion sysem has no opporuniy o advance is simulaion ime. The simulaion sysem would deals messages coninually bu simulaion ime pauses. s + simulaion ime msg 2 msg3 msg s msg Wall clock ime + 5 Figure 6. Simulaion ime pausing phenomenon diagram 2

6 Device sae mapping soluion The criical reason of he hree ime-space inconsisency phenomena above is he lack capabiliy o deal messages from s. Wih he framework of DAPM, we propose a sae mapping soluion o reduce messages piling.. Device sae mapping able We define a sae mapping able as Tab., conains hree fields: sae variable name, sae variable value, changed flag. Simulaion sysem reas he able as ouside, while a hread named Device Sae Daemon runs background o receive messages from and change he sae variable value correspondingly. Table. DEVICE sae mapping able variable name variable value changed flag X 0/ X2 0/ X3 0/ Xn 0/.2 Inner archiecure wih DAPM We design he inner archiecure wih DAPM shows as Fig.7. In access proxy, he sae daemon hread receives messages from inerface hrough socke and updaes he sae mapping able. In he simulaion sysem, he simulaion sysem hread insers evens o query he sae mapping able a regular inervals, he even firsly checks he able s changed flag field and ackles all he changed saes. Figure 7. inner archiecure wih DAPM diagram 25

7 Wih his soluion, once simulaion sysem processes in he simulaion compuer occurs o suddenly pause or emporary sop, he sae daemon hread could coninue work and he sae mapping able is changing and updaing when messages come in. When simulaion sysem process recover working, i can deal one even bu los of messages all compleed. There is no message loss, message lag, message pile, and so no ime-space inconsisency problem. The sae mapping soluion is effecive only o hose sysems relaed o saes bu o processes. Because during he pause of he simulaion sysem process, he sae may change several imes and he las sae can be recognized o he simulaion sysem. 5 Conclusions The sae mapping soluion o solve hree ime-space inconsisen problem is used in several applicaions and he resuls show ha i works and performs excellen. References. H.DONG. Design and Implemenaion on Sofware Framework of Hardware-In-he-Loop Simulaion Sysem for High-Speed Railway [D], Beijing: Tsinghua Universiy (2009) 2. Z.JIANG. Design and Implemenaion on a HLA-based Run Time Infrasrucure for Hardware-Inhe-Loop Simulaion [D], Beijing: Tsinghua Universiy (20) 3. H.Zhong. Research on Time-Space Consisency in Large-Scale Disribued Simulaions [D], Changsha: Naional Universiy of Defense Technology (2005). X.Wang. Research on he Time Managemen Technology in Parallel and Disribued Simulaion Sysems [D], Changsha: Naional Universiy of Defense Technology (2006) 5. Y.Yao. Research on he key echnologies of high performance runime infrasrucure of disribued ineracive simulaion [D], Changsha: Naional Universiy of Defense Technology, (2003) 6. Z.JIANG, W.DONG, Y.JI. A conservaive ime managemen model wih opimal degree of parallelism for disribued simulaion [C]. Performance Evaluaion of Compuer & Telecommunicaion Sysems (SPECTS) 20, The Hague, 2 26(20) 26