CS 152 Computer Architecture and Engineering. Lecture 7 - Memory Hierarchy-II
|
|
|
- Daniella Neal
- 5 years ago
- Views:
Transcription
1 CS 152 Compuer Archiecure and Engineering Lecure 7 - Memory Hierarchy-II Krse Asanovic Elecrical Engineering and Compuer Sciences Universiy of California a Berkeley hp:// hp://ins.eecs.berkeley.edu/~cs152 Las ime in Lecure 6 Dynamic RAM (DRAM) is main form of main memory sorage in use oday Holds values on small capaciors, need refreshing (hence dynamic) Slow muli-sep access: precharge, read row, read column Saic RAM (SRAM) is faser bu more expensive Used o build on-chip memory for caches s exploi wo forms of predicabiliy in memory reference sreams Temporal localiy, same locaion likely o be accessed again soon Spaial localiy, neighboring locaion likely o be accessed soon holds small se of values in fas memory (SRAM) close o processor Need o develop search scheme o find values in cache, and replacemen policy o make space for newly accessed locaions 2/17/2009 CS152-Spring!09 2
2 Placemen Policy Block Number Memory Se Number block 12 can be placed Fully (2-way) Se Direc Associaive Associaive Mapped anywhere anywhere in only ino se 0 block 4 (12 mod 4) (12 mod 8) 2/17/2009 CS152-Spring!09 3 Direc-Mapped Index Block Offse V k b Block 2 k lines = HIT Word or Bye 2/17/2009 CS152-Spring!09
3 2-Way Se-Associaive Index Block Offse b V k Block V Block = = Word or Bye HIT 2/17/2009 CS152-Spring!09 Fully Associaive V Block = Block Offse b = = Word or Bye HIT 2/17/2009 CS152-Spring!09
4 Replacemen Policy In an associaive cache, which block from a se should be eviced when he se becomes full? Random Leas Recenly Used (LRU) LRU cache sae mus be updaed on every access rue implemenaion only feasible for small ses (2-way) pseudo-lru binary ree ofen used for 4-8 way Firs In, Firs Ou (FIFO) a.k.a. Round-Robin used in highly associaive caches No Leas Recenly Used (NLRU) FIFO wih excepion for mos recenly used block or blocks This is a second-order effec. Why? Replacemen only happens on misses 2/17/2009 CS152-Spring!09 7 Block Size and Spaial Localiy Block is uni of ransfer beween he cache and memory Word0 Word1 Word2 Word3 4 word block, b=2 Spli CPU address block address offse b 32-b bis b bis 2 b = block size a.k.a line size (in byes) Larger block size has disinc hardware advanages less ag overhead exploi fas burs ransfers from DRAM exploi fas burs ransfers over wide busses Wha are he disadvanages of increasing block size? Fewer blocks => more conflics. Can wase bandwidh. 2/17/2009 CS152-Spring!09 8
5 CPU- Ineracion (5-sage pipeline) PCen PC 0x4 Add addr nop ins hi? Primary Insrucion IR D Decode, Regiser Fech E A B MD1 ALU M Y MD2 we addr Primary rdaa hi? wdaa R Sall enire CPU on daa cache miss To Memory Conrol Refill from Lower Levels of Memory Hierarchy 2/17/2009 CS152-Spring!09 9 Improving Performance Average memory access ime = Hi ime + Miss rae x Miss penaly To improve performance: reduce he hi ime reduce he miss rae reduce he miss penaly Wha is he simples design sraegy? Bigges cache ha doesn increase hi ime pas 1-2 cycles (approx 8-32KB in modern echnology) [ design issues more complex wih ou-of-order superscalar processors ] 2/17/2009 CS152-Spring!09 10
6 Serial-versus-Parallel and Memory access! is HIT RATIO: Fracion of references in cache 1 -! is MISS RATIO: Remaining references Processor Addr CACHE Average access ime for serial search: Addr Main Memory cache + (1 -!) mem Processor Addr CACHE Main Memory Average access ime for parallel search:! cache + (1 -!) mem Savings are usually small, mem >> cache, hi raio! high High bandwidh required for memory pah Complexiy of handling parallel pahs can slow cache 2/17/2009 CS152-Spring!09 Causes for Misses Compulsory: firs-reference o a block a.k.a. cold sar misses - misses ha would occur even wih infinie cache Capaciy: cache is oo small o hold all daa needed by he program - misses ha would occur even under perfec replacemen policy Conflic: misses ha occur because of collisions due o block-placemen sraegy - misses ha would no occur wih full associaiviy 2/17/2009 CS152-Spring!09 12
7 Effec of Parameers on Performance Larger cache size + reduces capaciy and conflic misses - hi ime will increase Higher associaiviy + reduces conflic misses - may increase hi ime Larger block size + reduces compulsory and capaciy (reload) misses - increases conflic misses and miss penaly 2/17/2009 CS152-Spring!09 13 Wrie Policy Choices hi: wrie hrough: wrie boh cache & memory» generally higher raffic bu simplifies cache coherence wrie back: wrie cache only (memory is wrien only when he enry is eviced)» a diry bi per block can furher reduce he raffic miss: no wrie allocae: only wrie o main memory wrie allocae (aka fech on wrie): fech ino cache Common combinaions: wrie hrough and no wrie allocae wrie back wih wrie allocae 2/17/2009 CS152-Spring!09 14
8 Wrie Performance V Index k Block Offse b 2 k lines = WE HIT Word or Bye 2/17/2009 CS152-Spring!09 15 Reducing Wrie Hi Time Problem: Wries ake wo cycles in memory sage, one cycle for ag check plus one cycle for daa wrie if hi Soluions: Design daa RAM ha can perform read and wrie in one cycle, resore old value afer ag miss Fully-associaive (CAM ) caches: Word line only enabled if hi Pipelined wries: Hold wrie daa for sore in single buffer ahead of cache, wrie cache daa during nex sore s ag check 2/17/2009 CS152-Spring!09 16
9 CS152 Adminisrivia 2/17/2009 CS152-Spring!09 17 Pipelining Wries Address and Sore From CPU Index Sore s Delayed Wrie Addr. =? Load/Sore S L Delayed Wrie =? 1 0 Load o CPU Hi? from a sore hi wrien ino daa porion of cache during ag access of subsequen sore 2/17/2009 CS152-Spring!09 18
10 Wrie Buffer o Reduce Read Miss Penaly CPU RF Wrie buffer Unified L2 Eviced diry lines for wrieback cache OR All wries in wriehru cache Processor is no salled on wries, and read misses can go ahead of wrie o main memory Problem: Wrie buffer may hold updaed value of locaion needed by a read miss Simple scheme: on a read miss, wai for he wrie buffer o go empy Faser scheme: Check wrie buffer addresses agains read miss addresses, if no mach, allow read miss o go ahead of wries, else, reurn value in wrie buffer 2/17/2009 CS152-Spring!09 19 Block-level Opimizaions s are oo large, i.e., oo much overhead Simple soluion: Larger blocks, bu miss penaly could be large. Sub-block placemen (aka secor cache) A valid bi added o unis smaller han full block, called sub-blocks Only read a sub-block on a miss If a ag maches, is he word in he cache? /17/2009 CS152-Spring!09 20
11 Se-Associaive RAM- Saus Saus =? =? No energy-efficien A ag and daa word is read from every way Two-phase approach Firs read ags, hen jus read daa from seleced way More energy-efficien Doubles laency in L1 OK, for L2 and above, why? Index Offse 2/17/2009 CS152-Spring!09 21 Mulilevel s A memory canno be large and fas Increasing sizes of cache a each level CPU L1$ L2$ DRAM Local miss rae = misses in cache / accesses o cache Global miss rae = misses in cache / CPU memory accesses Misses per insrucion = misses in cache / number of insrucions 2/17/2009 CS152-Spring!09 22
12 A Typical Memory Hierarchy c.2008 Spli insrucion & daa primary caches (on-chip SRAM) Muliple inerleaved memory banks (off-chip DRAM) CPU RF L1 Insrucion L1 Unified L2 Memory Memory Memory Memory Mulipored regiser file (par of CPU) Large unified secondary cache (on-chip SRAM) 2/17/2009 CS152-Spring!09 23 Presence of L2 influences L1 design Use smaller L1 if here is also L2 Trade increased L1 miss rae for reduced L1 hi ime and reduced L1 miss penaly Reduces average access energy Use simpler wrie-hrough L1 wih on-chip L2 Wrie-back L2 cache absorbs wrie raffic, doesn go off-chip A mos one L1 miss reques per L1 access (no diry vicim wrie back) simplifies pipeline conrol Simplifies coherence issues Simplifies error recovery in L1 (can use jus pariy bis in L1 and reload from L2 when pariy error deeced on L1 read) 2/17/2009 CS152-Spring!09 24
13 Inclusion Policy Inclusive mulilevel cache: Inner cache holds copies of daa in ouer cache Exernal access need only check ouer cache Mos common case Exclusive mulilevel caches: Inner cache may hold daa no in ouer cache Swap lines beween inner/ouer caches on miss Used in AMD Ahlon wih 64KB primary and 256KB secondary cache Why choose one ype or he oher? 2/17/2009 CS152-Spring!09 25 Ianium-2 On-Chip s (Inel/HP, 2002) Level 1: 16KB, 4-way s.a., 64B line, quad-por (2 load+2 sore), single cycle laency Level 2: 256KB, 4-way s.a, 128B line, quad-por (4 load or 4 sore), five cycle laency Level 3: 3MB, 12-way s.a., 128B line, single 32B por, welve cycle laency 2/17/2009 CS152-Spring!09 26
14 Acknowledgemens These slides conain maerial developed and copyrigh by: Arvind (MIT) Krse Asanovic (MIT/UCB) Joel Emer (Inel/MIT) James Hoe (CMU) John Kubiaowicz (UCB) David Paerson (UCB) MIT maerial derived from course UCB maerial derived from course CS252 2/17/2009 CS152-Spring!09 27
CS 152 Computer Architecture and Engineering. Lecture 7 - Memory Hierarchy-II
CS 152 Computer Architecture and Engineering Lecture 7 - Memory Hierarchy-II Krste Asanovic Electrical Engineering and Computer Sciences University of California at Berkeley http://www.eecs.berkeley.edu/~krste!
CS 152 Computer Architecture and Engineering. Lecture 6 - Memory
CS 152 Compuer Archiecure and Engineering Lecure 6 - Memory Krse Asanovic Elecrical Engineering and Compuer Sciences Universiy of California a Berkeley hp://www.eecs.berkeley.edu/~krse hp://ins.eecs.berkeley.edu/~cs152
CS 152 Computer Architecture and Engineering. Lecture 7 - Memory Hierarchy-II
CS 152 Computer Architecture and Engineering Lecture 7 - Memory Hierarchy-II Krste Asanovic Electrical Engineering and Computer Sciences University of California at Berkeley http://www.eecs.berkeley.edu/~krste
CS 152 Computer Architecture and Engineering. Lecture 6 - Memory
CS 152 Compuer Archiecure and Engineering Lecure 6 - Memory Krse Asanovic Elecrical Engineering and Compuer Sciences Universiy of California a Berkeley hp://www.eecs.berkeley.edu/~krse hp://ins.eecs.berkeley.edu/~cs152
Lecture 7 - Memory Hierarchy-II
CS 152 Computer Architecture and Engineering Lecture 7 - Memory Hierarchy-II John Wawrzynek Electrical Engineering and Computer Sciences University of California at Berkeley http://www.eecs.berkeley.edu/~johnw
C 1. Last Time. CSE 490/590 Computer Architecture. Cache I. Branch Delay Slots (expose control hazard to software)
CSE 490/590 Compuer Archiecure Cache I Seve Ko Compuer Sciences and Engineering Universiy a Buffalo Las Time Pipelining hazards Srucural hazards hazards Conrol hazards hazards Sall Bypass Conrol hazards
CS 152 Computer Architecture and Engineering. Lecture 7 - Memory Hierarchy-II
CS 152 Computer Architecture and Engineering Lecture 7 - Memory Hierarchy-II Krste Asanovic Electrical Engineering and Computer Sciences University of California at Berkeley http://www.eecs.berkeley.edu/~krste!
Lecture 11 Cache. Peng Liu.
Lecture 11 Cache Peng Liu liupeng@zju.edu.cn 1 Associative Cache Example 2 Associative Cache Example 3 Associativity Example Compare 4-block caches Direct mapped, 2-way set associative, fully associative
Page 1. Multilevel Memories (Improving performance using a little cash )
Page 1 Multilevel Memories (Improving performance using a little cash ) 1 Page 2 CPU-Memory Bottleneck CPU Memory Performance of high-speed computers is usually limited by memory bandwidth & latency Latency
CS 152 Computer Architecture and Engineering. Lecture 8 - Memory Hierarchy-III
CS 152 Computer Architecture and Engineering Lecture 8 - Memory Hierarchy-III Krste Asanovic Electrical Engineering and Computer Sciences University of California at Berkeley http://www.eecs.berkeley.edu/~krste
CS 152 Computer Architecture and Engineering. Lecture 8 - Memory Hierarchy-III
CS 152 Computer Architecture and Engineering Lecture 8 - Memory Hierarchy-III Krste Asanovic Electrical Engineering and Computer Sciences University of California at Berkeley http://www.eecs.berkeley.edu/~krste!
CS 152 Computer Architecture and Engineering. Lecture 8 - Memory Hierarchy-III
CS 152 Computer Architecture and Engineering Lecture 8 - Memory Hierarchy-III Krste Asanovic Electrical Engineering and Computer Sciences University of California at Berkeley http://www.eecs.berkeley.edu/~krste
CS 152 Computer Architecture and Engineering. Lecture 11 - Virtual Memory and Caches
CS 152 Computer Architecture and Engineering Lecture 11 - Virtual Memory and Caches Krste Asanovic Electrical Engineering and Computer Sciences University of California at Berkeley http://www.eecs.berkeley.edu/~krste
ECE 552 / CPS 550 Advanced Computer Architecture I. Lecture 13 Memory Part 2
ECE 552 / CPS 550 Advanced Computer Architecture I Lecture 13 Memory Part 2 Benjamin Lee Electrical and Computer Engineering Duke University www.duke.edu/~bcl15 www.duke.edu/~bcl15/class/class_ece252fall12.html
EE 660: Computer Architecture Advanced Caches
EE 660: Computer Architecture Advanced Caches Yao Zheng Department of Electrical Engineering University of Hawaiʻi at Mānoa Based on the slides of Prof. David Wentzlaff Agenda Review Three C s Basic Cache
ECE 252 / CPS 220 Advanced Computer Architecture I. Lecture 13 Memory Part 2
ECE 252 / CPS 220 Advanced Computer Architecture I Lecture 13 Memory Part 2 Benjamin Lee Electrical and Computer Engineering Duke University www.duke.edu/~bcl15 www.duke.edu/~bcl15/class/class_ece252fall11.html
! errors caused by signal attenuation, noise.!! receiver detects presence of errors:!
Daa Link Layer! The Daa Link layer can be furher subdivided ino:!.! Logical Link Conrol (LLC): error and flow conrol!.! Media Access Conrol (MAC): framing and media access! differen link proocols may provide
Memory Hierarchy. 2/18/2016 CS 152 Sec6on 5 Colin Schmidt
Memory Hierarchy 2/18/2016 CS 152 Sec6on 5 Colin Schmidt Agenda Review Memory Hierarchy Lab 2 Ques6ons Return Quiz 1 Latencies Comparison Numbers L1 Cache 0.5 ns L2 Cache 7 ns 14x L1 cache Main Memory
PART 1 REFERENCE INFORMATION CONTROL DATA 6400 SYSTEMS CENTRAL PROCESSOR MONITOR
. ~ PART 1 c 0 \,).,,.,, REFERENCE NFORMATON CONTROL DATA 6400 SYSTEMS CENTRAL PROCESSOR MONTOR n CONTROL DATA 6400 Compuer Sysems, sysem funcions are normally handled by he Monior locaed in a Peripheral
Using CANopen Slave Driver
CAN Bus User Manual Using CANopen Slave Driver V1. Table of Conens 1. SDO Communicaion... 1 2. PDO Communicaion... 1 3. TPDO Reading and RPDO Wriing... 2 4. RPDO Reading... 3 5. CANopen Communicaion Parameer
Outline. EECS Components and Design Techniques for Digital Systems. Lec 06 Using FSMs Review: Typical Controller: state
Ouline EECS 5 - Componens and Design Techniques for Digial Sysems Lec 6 Using FSMs 9-3-7 Review FSMs Mapping o FPGAs Typical uses of FSMs Synchronous Seq. Circuis safe composiion Timing FSMs in verilog
Multilevel Memories. Joel Emer Computer Science and Artificial Intelligence Laboratory Massachusetts Institute of Technology
1 Multilevel Memories Computer Science and Artificial Intelligence Laboratory Massachusetts Institute of Technology Based on the material prepared by Krste Asanovic and Arvind CPU-Memory Bottleneck 6.823
COSC 3213: Computer Networks I Chapter 6 Handout # 7
COSC 3213: Compuer Neworks I Chaper 6 Handou # 7 Insrucor: Dr. Marvin Mandelbaum Deparmen of Compuer Science York Universiy F05 Secion A Medium Access Conrol (MAC) Topics: 1. Muliple Access Communicaions:
Improving Cache Performance and Memory Management: From Absolute Addresses to Demand Paging. Highly-Associative Caches
Improving Cache Performance and Memory Management: From Absolute Addresses to Demand Paging 6.823, L8--1 Asanovic Laboratory for Computer Science M.I.T. http://www.csg.lcs.mit.edu/6.823 Highly-Associative
CS 152 Computer Architecture and Engineering. Lecture 6 - Memory
CS 152 Computer Architecture and Engineering Lecture 6 - Memory Krste Asanovic Electrical Engineering and Computer Sciences University of California at Berkeley http://www.eecs.berkeley.edu/~krste! http://inst.eecs.berkeley.edu/~cs152!
CS 152 Computer Architecture and Engineering. Lecture 9 - Address Translation
CS 152 Computer Architecture and Engineering Lecture 9 - Address Translation Krste Asanovic Electrical Engineering and Computer Sciences University of California at Berkeley http://www.eecs.berkeley.edu/~krste!
CS 152 Computer Architecture and Engineering. Lecture 9 - Address Translation
CS 152 Computer Architecture and Engineering Lecture 9 - Address Translation Krste Asanovic Electrical Engineering and Computer Sciences University of California at Berkeley http://www.eecs.berkeley.edu/~krste
EECS151/251A Spring 2018 Digital Design and Integrated Circuits. Instructors: John Wawrzynek and Nick Weaver. Lecture 19: Caches EE141
EECS151/251A Spring 2018 Digital Design and Integrated Circuits Instructors: John Wawrzynek and Nick Weaver Lecture 19: Caches Cache Introduction 40% of this ARM CPU is devoted to SRAM cache. But the role
Network management and QoS provisioning - QoS in Frame Relay. . packet switching with virtual circuit service (virtual circuits are bidirectional);
QoS in Frame Relay Frame relay characerisics are:. packe swiching wih virual circui service (virual circuis are bidirecional);. labels are called DLCI (Daa Link Connecion Idenifier);. for connecion is
Data Structures and Algorithms. The material for this lecture is drawn, in part, from The Practice of Programming (Kernighan & Pike) Chapter 2
Daa Srucures and Algorihms The maerial for his lecure is drawn, in par, from The Pracice of Programming (Kernighan & Pike) Chaper 2 1 Moivaing Quoaion Every program depends on algorihms and daa srucures,
CS 152 Computer Architecture and Engineering. Lecture 9 - Virtual Memory
CS 152 Computer Architecture and Engineering Lecture 9 - Virtual Memory Krste Asanovic Electrical Engineering and Computer Sciences University of California at Berkeley http://www.eecs.berkeley.edu/~krste!
Memory Hierarchy. Slides contents from:
Memory Hierarchy Slides contents from: Hennessy & Patterson, 5ed Appendix B and Chapter 2 David Wentzlaff, ELE 475 Computer Architecture MJT, High Performance Computing, NPTEL Memory Performance Gap Memory
Memory Hierarchy. Slides contents from:
Memory Hierarchy Slides contents from: Hennessy & Patterson, 5ed Appendix B and Chapter 2 David Wentzlaff, ELE 475 Computer Architecture MJT, High Performance Computing, NPTEL Memory Performance Gap Memory
CS 152 Computer Architecture and Engineering. Lecture 8 - Address Translation
CS 152 Computer Architecture and Engineering Lecture 8 - Translation Krste Asanovic Electrical Engineering and Computer Sciences University of California at Berkeley http://www.eecs.berkeley.edu/~krste!
4 Error Control. 4.1 Issues with Reliable Protocols
4 Error Conrol Jus abou all communicaion sysems aemp o ensure ha he daa ges o he oher end of he link wihou errors. Since i s impossible o build an error-free physical layer (alhough some shor links can
CS 152 Computer Architecture and Engineering CS252 Graduate Computer Architecture. Lecture 7 Memory III
CS 152 Computer Architecture and Engineering CS252 Graduate Computer Architecture Lecture 7 Memory III Krste Asanovic Electrical Engineering and Computer Sciences University of California at Berkeley http://www.eecs.berkeley.edu/~krste
Optimal Crane Scheduling
Opimal Crane Scheduling Samid Hoda, John Hooker Laife Genc Kaya, Ben Peerson Carnegie Mellon Universiy Iiro Harjunkoski ABB Corporae Research EWO - 13 November 2007 1/16 Problem Track-mouned cranes move
CS 152 Computer Architecture and Engineering. Lecture 8 - Address Translation
CS 152 Computer Architecture and Engineering Lecture 8 - Translation Krste Asanovic Electrical Engineering and Computer Sciences University of California at Berkeley http://www.eecs.berkeley.edu/~krste!
EC 513 Computer Architecture
EC 513 Computer Architecture Cache Organization Prof. Michel A. Kinsy The course has 4 modules Module 1 Instruction Set Architecture (ISA) Simple Pipelining and Hazards Module 2 Superscalar Architectures
Memory hier ar hier ch ar y ch rev re i v e i w e ECE 154B Dmitri Struko Struk v o
Memory hierarchy review ECE 154B Dmitri Strukov Outline Cache motivation Cache basics Opteron example Cache performance Six basic optimizations Virtual memory Processor DRAM gap (latency) Four issue superscalar
COMP26120: Algorithms and Imperative Programming
COMP26120 ecure C3 1/48 COMP26120: Algorihms and Imperaive Programming ecure C3: C - Recursive Daa Srucures Pee Jinks School of Compuer Science, Universiy of Mancheser Auumn 2011 COMP26120 ecure C3 2/48
Y. Tsiatouhas. VLSI Systems and Computer Architecture Lab
CMOS INEGRAED CIRCUI DESIGN ECHNIQUES Universiy of Ioannina Clocking Schemes Dep. of Compuer Science and Engineering Y. siaouhas CMOS Inegraed Circui Design echniques Overview 1. Jier Skew hroughpu Laency
CSC 631: High-Performance Computer Architecture
CSC 631: High-Performance Computer Architecture Spring 2017 Lecture 10: Memory Part II CSC 631: High-Performance Computer Architecture 1 Two predictable properties of memory references: Temporal Locality:
Memory Hierarchy. Jinkyu Jeong Computer Systems Laboratory Sungkyunkwan University
Memory Hierarchy Jinkyu Jeong (jinkyu@skku.edu) Computer Systems Laboratory Sungkyunkwan University http://csl.skku.edu EEE3050: Theory on Computer Architectures, Spring 2017, Jinkyu Jeong (jinkyu@skku.edu)
4. Minimax and planning problems
CS/ECE/ISyE 524 Inroducion o Opimizaion Spring 2017 18 4. Minima and planning problems ˆ Opimizing piecewise linear funcions ˆ Minima problems ˆ Eample: Chebyshev cener ˆ Muli-period planning problems
Agenda. EE 260: Introduction to Digital Design Memory. Naive Register File. Agenda. Memory Arrays: SRAM. Memory Arrays: Register File
EE 260: Introduction to Digital Design Technology Yao Zheng Department of Electrical Engineering University of Hawaiʻi at Mānoa 2 Technology Naive Register File Write Read clk Decoder Read Write 3 4 Arrays:
CS 152 Computer Architecture and Engineering. Lecture 19: Directory- Based Cache Protocols. Recap: Snoopy Cache Protocols
CS 152 Computer Architecture and Engineering Lecture 19: Directory- Based Protocols Krste Asanovic Electrical Engineering and Computer Sciences University of California, Berkeley hap://www.eecs.berkeley.edu/~krste
The Difference-bit Cache*
The Difference-bi Cache* Toni Juan, Tomas Lang~ and Juan J. Navarro Deparmen of Compuer Archiecure Deparmen of Elecrical and Universia Poli&cnica de Caalunya Compuer Engineering Gran CapiiJ s/n, Modul
Lecture 9 - Virtual Memory
CS 152 Computer Architecture and Engineering Lecture 9 - Virtual Memory Dr. George Michelogiannakis EECS, University of California at Berkeley CRD, Lawrence Berkeley National Laboratory http://inst.eecs.berkeley.edu/~cs152
CS 152 Computer Architecture and Engineering. Lecture 19: Directory-Based Cache Protocols
CS 152 Computer Architecture and Engineering Lecture 19: Directory-Based Cache Protocols Krste Asanovic Electrical Engineering and Computer Sciences University of California, Berkeley http://www.eecs.berkeley.edu/~krste
Lecture 6 - Memory. Dr. George Michelogiannakis EECS, University of California at Berkeley CRD, Lawrence Berkeley National Laboratory
CS 152 Computer Architecture and Engineering Lecture 6 - Memory Dr. George Michelogiannakis EECS, University of California at Berkeley CRD, Lawrence Berkeley National Laboratory http://inst.eecs.berkeley.edu/~cs152
Scheduling. Scheduling. EDA421/DIT171 - Parallel and Distributed Real-Time Systems, Chalmers/GU, 2011/2012 Lecture #4 Updated March 16, 2012
EDA421/DIT171 - Parallel and Disribued Real-Time Sysems, Chalmers/GU, 2011/2012 Lecure #4 Updaed March 16, 2012 Aemps o mee applicaion consrains should be done in a proacive way hrough scheduling. Schedule
Dimmer time switch AlphaLux³ D / 27
Dimmer ime swich AlphaLux³ D2 426 26 / 27! Safey noes This produc should be insalled in line wih insallaion rules, preferably by a qualified elecrician. Incorrec insallaion and use can lead o risk of elecric
Chapter 5. Large and Fast: Exploiting Memory Hierarchy
Chapter 5 Large and Fast: Exploiting Memory Hierarchy Memory Technology Static RAM (SRAM) 0.5ns 2.5ns, $2000 $5000 per GB Dynamic RAM (DRAM) 50ns 70ns, $20 $75 per GB Magnetic disk 5ms 20ms, $0.20 $2 per
Lecture 11 Cache and Virtual Memory
Lecture 11 Cache and Virtual Memory Peng Liu liupeng@zju.edu.cn 1 Associative Cache Example 2 Tag & Index with Set-Associative Caches Assume a 2 n -byte cache with 2 m -byte blocks that is 2 a set-associative
Utility-Based Hybrid Memory Management
Uiliy-Based Hybrid Memory Managemen Yang Li Saugaa Ghose Jongmoo Choi Jin Sun Hui Wang Onur Mulu Carnegie Mellon Universiy Dankook Universiy Beihang Universiy ETH Zürich While he memory fooprins of cloud
Chapter 8 LOCATION SERVICES
Disribued Compuing Group Chaper 8 LOCATION SERVICES Mobile Compuing Winer 2005 / 2006 Overview Mobile IP Moivaion Daa ransfer Encapsulaion Locaion Services & Rouing Classificaion of locaion services Home
Computer Architecture Computer Science & Engineering. Chapter 5. Memory Hierachy BK TP.HCM
Computer Architecture Computer Science & Engineering Chapter 5 Memory Hierachy Memory Technology Static RAM (SRAM) 0.5ns 2.5ns, $2000 $5000 per GB Dynamic RAM (DRAM) 50ns 70ns, $20 $75 per GB Magnetic
Exercise 3: Bluetooth BR/EDR
Wireless Communicaions, M. Rupf. Exercise 3: Blueooh BR/EDR Problem 1: Blueooh Daa Raes. Consider he ACL packe 3-DH5 wih a maximum user payload of 1021 byes. a) Deermine he maximum achievable daa rae in
Data Structures and Algorithms
Daa Srucures and Algorihms The maerial for his lecure is drawn, in ar, from The Pracice of Programming (Kernighan & Pike) Chaer 2 1 Goals of his Lecure Hel you learn (or refresh your memory) abou: Common
CS252 Spring 2017 Graduate Computer Architecture. Lecture 11: Memory
CS252 Spring 2017 Graduate Computer Architecture Lecture 11: Memory Lisa Wu, Krste Asanovic http://inst.eecs.berkeley.edu/~cs252/sp17 WU UCB CS252 SP17 Logistics for the 15-min meeting next Tuesday Email
Chapter 5. Large and Fast: Exploiting Memory Hierarchy
Chapter 5 Large and Fast: Exploiting Memory Hierarchy Principle of Locality Programs access a small proportion of their address space at any time Temporal locality Items accessed recently are likely to
USBFC (USB Function Controller)
USBFC () EIFUFAL501 User s Manual Doc #: 88-02-E01 Revision: 2.0 Dae: 03/24/98 (USBFC) 1. Highlighs... 4 1.1 Feaures... 4 1.2 Overview... 4 1.3 USBFC Block Diagram... 5 1.4 USBFC Typical Sysem Block Diagram...
CS 61C: Great Ideas in Computer Architecture (Machine Structures) Caches Part 3
CS 61C: Great Ideas in Computer Architecture (Machine Structures) Caches Part 3 Instructors: Krste Asanovic & Vladimir Stojanovic hfp://inst.eecs.berkeley.edu/~cs61c/ Parallel Requests Assigned to computer
CS 61C: Great Ideas in Computer Architecture (Machine Structures) Caches Part 3
CS 61C: Great Ideas in Computer Architecture (Machine Structures) Caches Part 3 Instructors: Krste Asanovic & Vladimir Stojanovic hcp://inst.eecs.berkeley.edu/~cs61c/ So$ware Parallel Requests Assigned
CS 152 Computer Architecture and Engineering. Lecture 19: Directory-Based Cache Protocols
CS 152 Computer Architecture and Engineering Lecture 19: Directory-Based Cache Protocols Krste Asanovic Electrical Engineering and Computer Sciences University of California, Berkeley http://www.eecs.berkeley.edu/~krste
Memory hierarchy review. ECE 154B Dmitri Strukov
Memory hierarchy review ECE 154B Dmitri Strukov Outline Cache motivation Cache basics Six basic optimizations Virtual memory Cache performance Opteron example Processor-DRAM gap in latency Q1. How to deal
Chapter 4 Sequential Instructions
Chaper 4 Sequenial Insrucions The sequenial insrucions of FBs-PLC shown in his chaper are also lised in secion 3.. Please refer o Chaper, "PLC Ladder diagram and he Coding rules of Mnemonic insrucion",
Midterm Exam Announcements
Miderm Exam Noe: This was a challenging exam. CSCI 4: Principles o Programming Languages Lecure 1: Excepions Insrucor: Dan Barowy Miderm Exam Scores 18 16 14 12 10 needs improvemen 8 6 4 2 0 0-49 50-59
CS 61C: Great Ideas in Computer Architecture (Machine Structures) Caches Part 2
CS 61C: Great Ideas in Computer Architecture (Machine Structures) Caches Part 2 Instructors: John Wawrzynek & Vladimir Stojanovic http://insteecsberkeleyedu/~cs61c/ Typical Memory Hierarchy Datapath On-Chip
Video streaming over Vajda Tamás
Video sreaming over 802.11 Vajda Tamás Video No all bis are creaed equal Group of Picures (GoP) Video Sequence Slice Macroblock Picure (Frame) Inra (I) frames, Prediced (P) Frames or Bidirecional (B) Frames.
Gauss-Jordan Algorithm
Gauss-Jordan Algorihm The Gauss-Jordan algorihm is a sep by sep procedure for solving a sysem of linear equaions which may conain any number of variables and any number of equaions. The algorihm is carried
The Memory Hierarchy & Cache Review of Memory Hierarchy & Cache Basics (from 350):
The Memory Hierarchy & Cache Review of Memory Hierarchy & Cache Basics (from 350): Motivation for The Memory Hierarchy: { CPU/Memory Performance Gap The Principle Of Locality Cache $$$$$ Cache Basics:
Why not experiment with the system itself? Ways to study a system System. Application areas. Different kinds of systems
Simulaion Wha is simulaion? Simple synonym: imiaion We are ineresed in sudying a Insead of experimening wih he iself we experimen wih a model of he Experimen wih he Acual Ways o sudy a Sysem Experimen
Motor Control. 5. Control. Motor Control. Motor Control
5. Conrol In his chaper we will do: Feedback Conrol On/Off Conroller PID Conroller Moor Conrol Why use conrol a all? Correc or wrong? Supplying a cerain volage / pulsewidh will make he moor spin a a cerain
An Adaptive Spatial Depth Filter for 3D Rendering IP
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.3, NO. 4, DECEMBER, 23 175 An Adapive Spaial Deph Filer for 3D Rendering IP Chang-Hyo Yu and Lee-Sup Kim Absrac In his paper, we presen a new mehod
CMPSC 311- Introduction to Systems Programming Module: Caching
CMPSC 311- Introduction to Systems Programming Module: Caching Professor Patrick McDaniel Fall 2016 Reminder: Memory Hierarchy L0: Registers CPU registers hold words retrieved from L1 cache Smaller, faster,
Chapter 5. Large and Fast: Exploiting Memory Hierarchy
Chapter 5 Large and Fast: Exploiting Memory Hierarchy Processor-Memory Performance Gap 10000 µproc 55%/year (2X/1.5yr) Performance 1000 100 10 1 1980 1983 1986 1989 Moore s Law Processor-Memory Performance
CENG 477 Introduction to Computer Graphics. Modeling Transformations
CENG 477 Inroducion o Compuer Graphics Modeling Transformaions Modeling Transformaions Model coordinaes o World coordinaes: Model coordinaes: All shapes wih heir local coordinaes and sies. world World
The Memory Hierarchy. Cache, Main Memory, and Virtual Memory (Part 2)
The Memory Hierarchy Cache, Main Memory, and Virtual Memory (Part 2) Lecture for CPSC 5155 Edward Bosworth, Ph.D. Computer Science Department Columbus State University Cache Line Replacement The cache
Chapter 3 MEDIA ACCESS CONTROL
Chaper 3 MEDIA ACCESS CONTROL Overview Moivaion SDMA, FDMA, TDMA Aloha Adapive Aloha Backoff proocols Reservaion schemes Polling Disribued Compuing Group Mobile Compuing Summer 2003 Disribued Compuing
ECE 4750 Computer Architecture, Fall 2014 T05 FSM and Pipelined Cache Memories
ECE 4750 Computer Architecture, Fall 2014 T05 FSM and Pipelined Cache Memories School of Electrical and Computer Engineering Cornell University revision: 2014-10-08-02-02 1 FSM Set-Associative Cache Memory
Memory Hierarchy. Maurizio Palesi. Maurizio Palesi 1
Memory Hierarchy Maurizio Palesi Maurizio Palesi 1 References John L. Hennessy and David A. Patterson, Computer Architecture a Quantitative Approach, second edition, Morgan Kaufmann Chapter 5 Maurizio
Test - Accredited Configuration Engineer (ACE) Exam - PAN-OS 6.0 Version
Tes - Accredied Configuraion Engineer (ACE) Exam - PAN-OS 6.0 Version ACE Exam Quesion 1 of 50. Which of he following saemens is NOT abou Palo Alo Neworks firewalls? Sysem defauls may be resored by performing
14:332:331. Week 13 Basics of Cache
14:332:331 Computer Architecture and Assembly Language Fall 2003 Week 13 Basics of Cache [Adapted from Dave Patterson s UCB CS152 slides and Mary Jane Irwin s PSU CSE331 slides] 331 Lec20.1 Fall 2003 Head
CS 152, Spring 2011 Section 8
CS 152, Spring 2011 Section 8 Christopher Celio University of California, Berkeley Agenda Grades Upcoming Quiz 3 What it covers OOO processors VLIW Branch Prediction Intel Core 2 Duo (Penryn) Vs. NVidia
COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface. 5 th. Edition. Chapter 5. Large and Fast: Exploiting Memory Hierarchy
COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition Chapter 5 Large and Fast: Exploiting Memory Hierarchy Principle of Locality Programs access a small proportion of their address
Lecture 14: Cache Innovations and DRAM. Today: cache access basics and innovations, DRAM (Sections )
Lecture 14: Cache Innovations and DRAM Today: cache access basics and innovations, DRAM (Sections 5.1-5.3) 1 Reducing Miss Rate Large block size reduces compulsory misses, reduces miss penalty in case
Computer Systems and Networks. ECPE 170 Jeff Shafer University of the Pacific $$$ $$$ Cache Memory 2 $$$
ECPE 170 Jeff Shafer University of the Pacific $$$ $$$ Cache Memory 2 $$$ 2 Schedule This week Chapter 6 Memory systems (caches) Next Tuesday Exam 2 Tuesday, Nov 1 st Next Thursday Chapter 6 Virtual memory
FIELD PROGRAMMABLE GATE ARRAY (FPGA) AS A NEW APPROACH TO IMPLEMENT THE CHAOTIC GENERATORS
FIELD PROGRAMMABLE GATE ARRAY (FPGA) AS A NEW APPROACH TO IMPLEMENT THE CHAOTIC GENERATORS Mohammed A. Aseeri and M. I. Sobhy Deparmen of Elecronics, The Universiy of Ken a Canerbury Canerbury, Ken, CT2
Caches Part 1. Instructor: Sören Schwertfeger. School of Information Science and Technology SIST
CS 110 Computer Architecture Caches Part 1 Instructor: Sören Schwertfeger http://shtech.org/courses/ca/ School of Information Science and Technology SIST ShanghaiTech University Slides based on UC Berkley's
Chapter 5. Large and Fast: Exploiting Memory Hierarchy
Chapter 5 Large and Fast: Exploiting Memory Hierarchy Memory Technology Static RAM (SRAM) 0.5ns 2.5ns, $2000 $5000 per GB Dynamic RAM (DRAM) 50ns 70ns, $20 $75 per GB Magnetic disk 5ms 20ms, $0.20 $2 per
Chapter 5. Large and Fast: Exploiting Memory Hierarchy
Chapter 5 Large and Fast: Exploiting Memory Hierarchy Processor-Memory Performance Gap 10000 µproc 55%/year (2X/1.5yr) Performance 1000 100 10 1 1980 1983 1986 1989 Moore s Law Processor-Memory Performance
CS 152 Computer Architecture and Engineering. Lecture 6 - Memory. Last =me in Lecture 5
CS 152 Computer Architecture and Engineering Lecture 6 - Memory Krste Asanovic Electrical Engineering and Computer Sciences University of California at Berkeley http://www.eecs.berkeley.edu/~krste! http://inst.eecs.berkeley.edu/~cs152!
Advanced Computer Architecture
ECE 563 Advanced Computer Architecture Fall 2009 Lecture 3: Memory Hierarchy Review: Caches 563 L03.1 Fall 2010 Since 1980, CPU has outpaced DRAM... Four-issue 2GHz superscalar accessing 100ns DRAM could
Chapter 5A. Large and Fast: Exploiting Memory Hierarchy
Chapter 5A Large and Fast: Exploiting Memory Hierarchy Memory Technology Static RAM (SRAM) Fast, expensive Dynamic RAM (DRAM) In between Magnetic disk Slow, inexpensive Ideal memory Access time of SRAM
CMPSC 274: Transac0on Processing Lecture #6: Concurrency Control Protocols
CMPSC 274: Transac0on Processing Lecure #6: Concurrency Conrol Proocols Divy Agrawal Deparmen of Compuer Science UC Sana Barbara 4.4.1 Timesamp Ordering 4.4.2 Serializa0on Graph Tes0ng 4.4.3 Op0mis0c Proocols
Announcements. TCP Congestion Control. Goals of Today s Lecture. State Diagrams. TCP State Diagram
nnouncemens TCP Congesion Conrol Projec #3 should be ou onigh Can do individual or in a eam of 2 people Firs phase due November 16 - no slip days Exercise good (beer) ime managemen EE 122: Inro o Communicaion
Mo Money, No Problems: Caches #2...
Mo Money, No Problems: Caches #2... 1 Reminder: Cache Terms... Cache: A small and fast memory used to increase the performance of accessing a big and slow memory Uses temporal locality: The tendency to
CS 152 Computer Architecture and Engineering
CS 152 Computer Architecture and Engineering Lecture 18: Directory-Based Cache Protocols John Wawrzynek EECS, University of California at Berkeley http://inst.eecs.berkeley.edu/~cs152 Administrivia 2 Recap: