Let s get physical - EDA Tools for Mobility
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1 Le s ge physical - EDA Tools for Mobiliy Aging and Reliabiliy Communicaion Mobile and Green Mobiliy - Smar and Safe Frank Oppenheimer OFFIS Insiue for Informaion Technology
2 OFFIS a a glance Applicaion-oriened + Technology Leadership = Susainabiliy Applicaion-Know-How concenraed in R&D-Divisions ICT-Know-How concenraed in inerdisciplinary Technology Clusers Ambien Healh Technologies Analyical Informaion Sysems Dependable Sysems Embedded Sysem Design Auomaion Human Machine Ineracion ICT for Smar Grids
3 Source: hp:// 3 Socio-economic drivers for embedded sysems of he fuure Mega ciies Indusry 4.0 Smar grid Smar mobiliy Sysem of cyber physical sysems (CPS) CPS CPS Compuing plaform Embedded sysem
4 4 Vision: Technologies for Smarer Mobiliy Informaion on curren siuaion is used by road users in real-ime for safe, efficien, environmenally sound and comforable mobiliy. Applicaion examples: Auonomous driving Muli-modal mobiliy The car ha cares Adapive rouing up o 4D harmonizaion Requiremens for real-ime informaion processing and conrol increase. Requiremens on compuing densiy (no. applicaions/compuing plaform) increases significanly. Physical properies of compuing plaforms need o become analyzable and predicable o guaranee real-ime, power, and reliabiliy requiremens of he applicaions.
5 5 The Imporance of Exra-funcional Properies Influence on he developmen of sysems reliabiloy fmax [MHz] variaion energy Vmax [km/h] energy
6 6 Challenge I: Communicaion - Mobile and Green Overview Smar mobiliy
7 7 Communicaion - Mobile and Green Ever increasing demand for (compuaional) power Exra-funcional properies limi he power of modern communicaion equipmen and infrasrucure
8 8 HW/SW power & iming esimaion wih back-annoaion C OMPLEX Execuable ask model Archiecure/resource model CPU MEM Bus IP-core ASIC Arbier Task mapping Communicaion graph Mapped & annoaed ask model C C C C Esimaion & back-annoaion Number of cycles Swiched capaciance C Communicaion SW esimaion IP esimaion HW esimaion Power and Timing Esimaion ools wih back-annoaion Conrol Daa Flow Graph Exra-funcional Timing & Power model Compuaion Basic Block Branch
9 Memory IF IF Mem Power model Power model TLM 2 rouer IF IF Mem Power model 9 Virual Sysem Generaion C OMPLEX SW (CPU) T0 Iniiaor CPU Exra-funcional properies such as energy consumpion, baery life cooling reliabiliy availabiliy MEM Bus Arbier Virual sysem generaion HW (FPGA) Targe PSM FPGA ASIC T1 Mapped & annoaed ask model limi he capabiliies of modern communicaions equipmen and infrasrucure. New sysem design mehodologies mus be able o suppor exra-funcional propery closure hrough a formal represenaion of exra-funcional consrains (promise and assumpion), HW (ASIC) represening Targe Targe exra-funcional properies in execuable or analyical T2 prooypes and Memory o enable a formal mach of he consrains agains implemenaion PSM properies.
10 10 Challenge II: Aging and Reliabiliy Overview Communicaion and energy Smar mobiliy Funcion, iming & energy demand under variaion and aging
11 Wha drives Technology and wha s nex? NMOS VDD ISC 100µm 0 1 delay, area CMOS Icap VDD 0 energy (per compuaion) CFS Igae VDD IGIDL 1 Gnd 10µm Gnd power (saic consumpion) process variaion aging 1 0 I sub reliabiliy high-k Vh Gnd FinFET IGIDL 1µm Isub Isub 100nm 10nm 1nm
12 12 Reliabiliy by design Sae-of-he-ar design: (Over-)Designed Sysem (Over-)Designed Sysem (Over-)Designed Sysem Sysem Requiremens overdesign Sysem Requiremens producion Sysem Requiremens PTV Variaions aging Sysem Requiremens Degraded Sysem Wih PTV + aging predicion, regarding adapive echniques (as DVFS) and redundancies: Sysem Requiremens adapive design Designed Sysem Sysem Requiremens producion Wors-Case PTV Sysem Requiremens aging Designed Sysem Sysem Requiremens Degraded Sysem
13 Memory IF IF Mem Power model Power model TLM 2 rouer IF IF Mem Power model 13 Sysem level reliabiliy modeling puing i all ogeher SW (CPU) HW (FPGA) T0 Iniiaor Targe T1 HW (ASIC) Targe Targe Opimize longerm reliabiliy needs undersanding T2 degradaion effecs: Memory combine muliple exra-funcional model for aging predicion PSM inroduce adapive echniques PSM already a design enry o reduce overdesign cos Use fas aging predicion o pick he bes soluion SysemC + power & iming models dynamic power over ime races execuion herm
14 14 Challenge III: Inegraed Mobiliy - Smar and Safe Overview Smar mobiliy Source: hp://
15 15 Auonomous mobiliy Then and now Source: Universiä der Bundeswehr, Munich Source: Team Vicor Tango (Virginia Tech and TORC Technologies) CC Embedded Sysem Design Auomaion January, 29h 2013
16 16 Sae-of-he-ar in mixed-criical sysem design Fully disribued wih dedicaed HW/SW plaforms for differen criicaliies F1 F2 F3 CPU Memory HW IP... CPU Memory HW IP... F1 F2 F3 d 2->3 d 4->5 (Safey-criical) Embedded Applicaion Hard deadline d 2->3 Sof power consrains Sof emperaure consrains Mobile Mulimedia Applicaion Sof deadline d 4->5 Hard power consrains Hard emperaure consrains
17 17 Segregaion on shared compuaion plaforms Guaranee exra-funcional properies per applicaion on shared plaform resources F1 F2 F3 (Safey-criical) Embedded Applicaion Mobile Mulimedia Applicaion F1 F2 F3? d 2->3 d 4->5 F1 F2 F3? CPU 1 CPU 2 Memory Muli-core archiecure HW IP...? running block/susp. shared var. comm. d 2->3 d 4->5
18 18 Segregaion on shared compuaion plaforms Guaranee exra-funcional properies per applicaion on shared plaform resources F1 F2 F3 F1 F2 F3? d 2->3 d 4->5 F1 F2 F3? CPU 1 CPU 2 Memory Muli-core archiecure HW IP...? running block/susp. shared var. comm. d 2->3 d 4->5 Source: hp://rcmagazine.com/aricles/view/102791
19 19 Goal: Composiional analysis of power and emperaure in mixed-criical sysems F1 F2 F3 CPU Memory HW IP... CPU Memory HW IP... <<virual>> <<virual>> <<virual>> <<virual>> <<virual>> <<virual>> F1 F2 F3 d 2->3 d 4->5 F1 F2 F3 CPU 1 CPU 2 Memory Muli-core archiecure HW IP... running block/susp. shared var. comm. d 2->3 d 4->5 Source: hp://rcmagazine.com/aricles/view/102791
20 20 Goal: Composiional analysis of power and emperaure in mixed-criical sysems F1 F2 F3 CPU Memory HW IP... CPU Memory HW IP... <<virual>> <<virual>> <<virual>> <<virual>> <<virual>> <<virual>> F1 F2 F3 d 2->3 d 4->5 F1 F2 F3 CPU 1 CPU 2 Memory Muli-core archiecure HW IP... running block/susp. shared var. comm. d 2->3 d 4->5
21 21 Goal: Composiional analysis of power and emperaure in mixed-criical sysems F1 F2 F3 F1 F2 F3 F1 F2 F3 CPU Memory HW IP... CPU Memory HW IP... <<virual>> <<virual>> <<virual>> <<virual>> <<virual>> <<virual>> Necessary increase in he funcion densiy (= more funcions in less ECUs) due o limied space weigh requiremens energy efficiency cos availabiliy d 2->3 promoes he use of muli-core processors. d 2->3 d 4->5... running Managemen of muli-core s CPU 1 shared CPU 2resources Memory o HW guaranee IP emporal and spaial segregaion of safey-criical applicaions. Bu a he same ime enabling Muli-core archiecure composiional power and emperaure analysis and managemen. block/susp. shared var. comm. d 4->5
22 22 Driving Challenges Summary I) Communicaion - Mobile and Green: billion mobile communicaion devices - Power consumpion/hea of infrasrucure limis bandwidh and QoS - Power consumpion of mobile devices limis service usabiliy, funcionaliy and availabiliy (-> baery lifeime) II) Aging and reliabiliy: - Shrinking feaure size increase variaion and degradaion - Aging and reliabiliy become he nex limiing exra-funcional propery. III) Mobiliy - Smar and Safe: - Combinaion of mobile, mulimedia and (safey-criical) embedded services on he same device. - Muli-cores enable higher funcional densiy bu cos predicabiliy
23 23 Y-char 2.0 An EDA coordinae sysem for exra-funcional properies Sysem Processor Logic Circui Srucure (nelis) Behavior (funcion) Physical (layou)
24 Conac informaion Prof. Dr.-Ing. Wolfgang Nebel Chairman of he Board Mail: Tel: Dr. Frank Oppenheimer Direcor R&D Division Transporaion Mail: Tel:
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