Huamao Huang, Jinyong Hu, and Hong Wang. 1. Introduction

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1 e Scientific World Journal, Article ID , 6 pages Research Article Light-Output Enhancement of GaN-Based Light-Emitting Diodes with Three-Dimensional Backside Reflectors Patterned by Microscale Cone Array Huamao Huang, Jinyong Hu, and Hong Wang Engineering Research Center for Optoelectronics of Guangdong Province, Department of Physics, School of Science, South China University of Technology, Guangzhou, Guangdong , China Correspondence should be addressed to Hong Wang; phhwang@scut.edu.cn Received 10 April 2014; Accepted 1 July 2014; Published 15 July 2014 Academic Editor: Paolo Colantonio Copyright 2014 Huamao Huang et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. Three-dimensional (3D) backside reflector, compared with flat reflectors, can improve the probability of finding the escape cone for reflecting lights and thus enhance the light-extraction efficiency (LEE) for GaN-based light-emitting diode (LED) chips. A triangle-lattice of microscale SiO 2 cone array followed by a 16-pair Ti 3 O 5 /SiO 2 distributed Bragg reflector (16-DBR) was proposed to be attached on the backside of sapphire substrate, and the light-output enhancement was demonstrated by numerical simulation and experiments. The LED chips with flat reflectors or 3D reflectors were simulated using Monte Carlo ray tracing method. It is shown that the LEE increases as the reflectivity of backside reflector increases, and the light-output can be significantly improved by 3D reflectors compared to flat counterparts. It can also be observed that the LEE decreases as the refractive index of the cone material increases. The 3D 16-DBR patterned by microscale SiO 2 cone array benefits large enhancement of LEE. This microscale pattern was prepared by standard photolithography and wet-etching technique. Measurement results show that the 3D 16-DBR can provide 12.1% enhancement of wall-plug efficiency, which is consistent with the simulated value of 11.73% for the enhancement of LEE. 1. Introduction Low light-output efficiency is one of the biggest obstacles for the extensive use of GaN-based light-emitting diodes (LEDs) in general lighting. To enhance the light-output of the top side in LED chips, a backside reflector is used [1 3]. However, the extensively used reflector always consists of multiple thinfilms, with which the LED chip makes up planar optical waveguides. Thus, lights outside the critical angle would be confinedwithinthedeviceandberepeatedlyreflectedby the GaN/air interface. These lights would be absorbed by semiconductor materials, multiple quantum well, and metal electrodes, which would finally convert to heat. Therefore, the light-output efficiency is suppressed. In order to break the planar structure, three-dimensional (3D) reflectors can be used. The microscale tetragonal-lattice of SiO 2 pyramid with silver (Ag) mirror was first proposed to be placed on the surface of p-gan in flip-chip LEDs[4]. In conventional LED chips, the metal mirror was also adopted. After the sapphire substrate was wet-etched in hot acid, an Ag layer was deposited on the backside of the textured sapphire as 3D reflector [5]. However, the metal Ag thin-film is not advisable to be directly attached on sapphire substrate because of the poor adhesion performance [6], while the distributed Bragg reflector (DBR) composed of dielectric multilayer films is preferred. Before the DBR is fabricated, the textured sapphire can also be created by laser interference lithography followed by dry-etching [7]. However, the etching of sapphire substrate is not easy no matter whether the wet-etching [5] ordryetching [7] was employed. Alternatively, SiO 2 nanostructures were used to form the pattern, and then the mirror layer was deposited on the 3D surface [8 10]. The SiO 2 nanospheres were spun-casted on a benzocyclobutene (BCB) layer and thebottomhalfofthenanosphereswereembeddedinbcb after annealing; subsequently, nanoscale convex or concave

2 2 The Scientific World Journal SiO 2 P-Pad ITO p-gan p-algan N-Pad MQW n-gan u-gan Buffer Sapphire DBR SiO 2 DBR Figure 1: Schematic structure of LED chips with flat DBR and 3D reflector. Monitor p-gan n-gan Monitor p-gan n-gan Sapphire Sapphire Cone array Figure 2: Sketch of side-view of simulation model with flat reflector and 3D reflector. pattern can be created on the condition that the nanospheres remained or were wiped off [8]. The SiO 2 nanosphere monolayer can also be covered by a thick SiO 2 layer, and the fluctuated surface is the pattern for 3D reflector [9, 10]. However, the nanosphere lithography is hard to realize wafer-scale SiO 2 monolayer pattern in mature production line. Thus, the microscale structures defined by traditional photolithography are more suitable for mass production. A microscale pyramid array of DBR embedded in epilayer was studied [11]. However, this approach would affect the epitaxial process. In this paper, a SiO 2 thin-film was prepared at the backside of sapphire substrates. Then, the triangle-lattice of microscale SiO 2 cone array was patterned by standard photolithography and wet-etching technique. After that, a 16- pair Ti 3 O 5 /SiO 2 DBR was deposited to build 3D reflector. The light-output enhancement is demonstrated by numerical simulation and experiments. 2. Materials and Methods Figure 1 shows the LED chip with conventional flat reflector and that with our proposed 3D reflector. For conventional flat reflector in Figure 1, a16-pairdbrlayerisdirectly deposited on the backside of sapphire substrate. For our proposed 3D reflector in Figure 1, a triangle-lattice of SiO 2 cone array is placed on the backside of sapphire substrate at firstandfollowedbythe16-pairdbrlater Simulation. The side-view of simulation model is sketched in Figure 2. The chip size is 254μm (width) μm (length) μm (height), in which the height of cone array is not reckoned. In order to reduce the computation resource, this 3D model only consists of three layers,includingthesapphiresubstrate,then-typegan(n- GaN), and the p-type GaN (p-gan). The thicknesses of these three layers are h sapphire = 100 μm, h n-gan = 6μm, and

3 The Scientific World Journal 3 Table 1: Material parameters used in the simulation. Refractive index Extinction coefficient p-gan n-gan Sapphire SiO Polystyrene ZnO Ti 3 O # Ti 3 O Al Ag Parameters of Ti 3 O 5 used for materials of cone array. # Parameters of Ti 3 O 5 used for materials of Ti 3 O 5 /SiO 2 DBR. h p-gan = 0.3 μm,respectively.theconearrayisinthe form of triangle-lattice, and the major radius, minor radius, height, and periodicity are 1.5 μm, 1μm, 0.5μm, and 6μm, respectively. The multiple quantum well (MQW) layer is simplified as the interface between the two GaN layers, and the effect of the backside reflector is taken into account by applying their reflectance spectra as the surface property of the backside of sapphire substrate. The reflectance spectra can be calculated using multiple thin-film theory [12], and the thickness of each layer in DBR is set to be quarterwavelength. The power monitor is placed at 1 μm distance fromthetopsurfaceofp-ganlayer,andthelight-extraction efficiency (LEE) is estimated by LEE =P monitor /P MQW,where P monitor is the power detected by the monitor and P MQW is the total power emitted from the MQW. The material parameters used in our simulation are shown in Table 1, includingthe materials for GaN-based LED chips (i.e., p-gan, n-gan, and sapphire), those for cone array (i.e., SiO 2,polystyrene, sapphire,zno,andti 3 O 5 ), and those for reflectors (i.e., SiO 2, Ti 3 O 5, aluminium (Al), and Ag). The LED chips with various materials of cone array and different types of reflectors are studied to optimize the LEE. The 3D models are simulated using Monte Carlo ray tracing method [13, 14]. The ray tracing method is generally used in the case of λ m l s,whereλ m is the wavelength in the material and l s is the shortest optical-length in the structure. However, it can be also used to predict the trends in the case of λ m that is in the same order of l s,sincethe results are similar to those estimated by 3D finite-difference time-domain (FDTD) method for nanostructures [13]. In our simulation, light rays are randomly generated from MQW at the wavelength of 460 nm and the angular distribution is Lambertian. The total number of light rays is , and the light rays would annihilate if their energy attenuates to be less than 5% of the initial values Experiment. The fabricated LED chips are sketched in Figure 1, and the fabrication processes are described as follows. Firstly, the epilayer was selectively etched by inductively coupled plasma (ICP) to expose the n-gan layer. Secondly, asio 2 layer was deposited by plasma-enhanced chemical vapor deposition (PECVD) as electrical barrier layer. Then, the indium-tin-oxide (ITO) transparent conductive layer was E-beam evaporated, wet-etched, and thermally annealed. Thereafter, the metal lift-off technology was used to fabricate the p-electrode and n-electrode. After that, a SiO 2 layer was deposited by PECVD for passivation and was wet-etched to expose the p-electrode and n-electrode. Finally, the sapphire substrate was lapped and polished, and then the backside reflectorwouldbefabricatedonthebottomofthesubstrate. The 3D backside reflector consists of a triangle-lattice of SiO 2 cone array and a Ti 3 O 5 /SiO 2 DBR. After the sapphire substrate is lapped down to about 200 μm, a SiO 2 layer with the thickness of 500 nm is deposited by PECVD on the polished substrate. Then, the top side of the epilayer is protected by spin-coating a photoresist layer and hardbaking for 30 min at the temperature of 140 C. After that, the SiO 2 array on the bottom of the substrate can be prepared by standard photolithography and wet-etching. The triangle-lattice in the photolithography mask is composed of hollow circles with a diameter of 3 μm and a periodicity of 6 μm. These parameters of triangle-lattice are limited by the resolution of standard ultraviolet lithography due to the Fresnel diffraction effect [15]. After 5 min wet-etching using buffered oxide etchant (BOE), the SiO 2 cone array can be obtained. The surface shown in Figure 3 taken by 3D optical profiler or scanning electron microscope (SEM) is the reflecting surface, since the 16-pair Ti 3 O 5 /SiO 2 DBR would be deposited later to cover this SiO 2 pattern. The diameters of the bottom surface and the top surface of SiO 2 cone are about 2.8 μmand1.8μm, respectively. The difference between the diameters of fabricated microstructures and the nominal values in the photolithography mask can be attributed to the overetching. The nonvertical sidewall with downward slope is the natural formation of long time wet-etching, since the upper part of the sidewall gets more reaction time with the etchant. Finally, the 16-pair Ti 3 O 5 /SiO 2 DBR was deposited by ion-assisted E-beam evaporation on the backside of the SiO 2 pattern. In the measurements, the emission pictures observed by microscope can be used to develop the intuition of the effects of 3D reflector compared to flat reflector. The detailed optical and electrical performance are measured through probestationandintegratingsphere. 3. Results and Discussion 3.1. Simulation. Figure4 showstheangularreflectivityofflat Al mirror, flat Ag mirror, and flat 16-pair Ti 3 O 5 /SiO 2 DBR (16-DBR) at the wavelength of 460 nm. It is shown that the 16- DBR exhibits higher reflectivity than the two metal mirrors, especially in the range from normal incidence to the incident angle of 30. Take the case of normal incidence as an example; the reflectivity of flat Al mirror, flat Ag mirror, and flat 16- DBR is 87.6%, 90.0%, and 99.7%, respectively. The LEE of LED chips with Al mirror, Ag mirror, 16- DBR, and perfect reflector is shown in Figure 5. Aperfect reflector is an imaginary mirror with the reflectivity of 100% at any wavelength and any angle. The LEE of LED chips with

4 4 The Scientific World Journal 2.8 μm μm 90 Reflectivity, R (%) Incident angle, θ ( ) Al Ag 16-DBR Figure 4: The angular reflectivity of various flat reflectors. The incident angle is measured from normal to substrate, and the reflectance spectra are calculated at the wavelength of 460 nm. Figure 3: Microscope photography of fabricated SiO 2 array taken by 3D optical profiler and SEM. Al mirror, Ag mirror, 16-DBR, and perfect reflector of the flat type is 13.19%, 13.41%, 13.72%, and 14.29%, respectively, and that of the 3D type is 14.18%, 14.49%, 15.32%, and 15.87%, respectively. It is shown that the LEE increases as the reflectivity of backside reflector increases, and it can be significantly improved by 3D reflectors compared to flat counterparts. The enhancement factor, which is defined as the ratio of LEE for LED chips with 3D reflectors and that with flat counterparts, is also shown in Figure 5.Theenhancement factors for Al mirror, Ag mirror, 16-DBR, and perfect mirror are7.48%,8.07%,11.73%,and11.01%,respectively.the3d DBR exhibits the highest LEE and the highest enhancement factor compared to the two metal mirrors. The LEE of LED chips with 3D perfect mirror patterned by cone array with different material is also studied and shown in Figure 6. The refractive indices are tabulate in Table 1 and also shown in Figure 6. In the simulation, the extinction coefficient of Ti 3 O 5 used for the materials of cone arrayissettobe0.thisisforthesakeofcomparisonsince othermaterialsforconearrayhavenoloss.itcanbeobserved that the LEE decreases as the refractive index of the cone material increases. The 3D DBRs patterned by SiO 2 cone array exhibit the highest LEE compared to those patterned by other materials Experiment. Figure 7 shows the emission pictures of LED chips with flat DBR and 3D DBR patterned by SiO 2 cone array under the injection current of 0.1 ma. It is clearly shown that the LED chip with 3D DBR is brighter than that with flat DBR. Light extraction efficiency (%) Al Ag 16-DBR Perfect Flat reflector 3D reflector Mirror Type Figure 5: The light-extraction efficiency (left) and the enhancement factor of 3D reflectors compared to flat reflectors (right) in simulation models with different types of mirror. The light-output power and the forward voltage at different injection current are shown in Figure 8. Under the injection current of 20 ma, the light-output power and the forward voltage of the LED chip with flat DBR are mw and V, while those with our proposed 3D reflector are mw and V, respectively. It is shown that the lightoutput power is enhanced by 12.2%, which is attributed to the larger probability of finding the escape cone for the light reflected by the 3D DBR compared to the flat DBR. On the otherhand,theforwardvoltagehasalmostnoshift.this indicates that the fabrication process of the 3D reflector has little effects on the electrical performance. Thus, the 3D DBR Enhancement factor (%)

5 The Scientific World Journal Light extraction efficiency (%) Refractive index Light output power (mw) Forward voltage (V) 13.5 SiO 2 Polystyrene Sapphire ZnO 1 Ti 3 O 5 Cone material Figure 6: The light-extraction efficiency (left) and the refractive index (right) for different materials of cone array in simulation model Flat DBR 3D DBR Injection current (ma) Figure 8: The light-output power (left) and forward voltage (right) of fabricated samples under different injection currents. 80 Figure 7: Emission pictures of LED chips with flat DBR and 3D DBR. Wall-plug efficiency (%) Injection current (ma) can also provide 12.1% enhancement of wall-plug efficiency, which is shown in Figure 9. The enhancement factor of wallplug efficiency from experiments is slightly larger than that of LEE from simulation. The reason can be attributed to the improvement of internal quantum efficiency because of reduced heat generation, the single-wavelength simulation at 460nm,andtheerrorinmeasurements. 4. Conclusion In summary, the LED chips with 3D reflector patterned by a triangle-lattice of cone array were simulated using Monte Carlo ray tracing method. Several types of mirrors and various materials for cone array were studied to optimize the LEE. Simulation results show that the 3D 16-DBR patterned by SiO 2 cone array benefits large enhancement of LEE, and thus the 3D 16-DBR was fabricated and tested. Measurement results show that the 3D 16-DBR can provide 12.1% enhancement of wall-plug efficiency, which is consistent with the simulated value of 11.73% enhancement of LEE. The geometry Flat DBR 3D DBR Figure 9: The wall-plug efficiency of fabricated samples under different injection currents. parameters, such as shape, size, and periodicity, of SiO 2 cone array can be tuned to optimize the LEE further. Conflict of Interests The authors declare that there is no conflict of interests regarding the publication of this paper. Acknowledgments This work was supported by the National High Technology Research and Development Program of China (863 Program) (no. 2014AA032609), Strategic Emerging Industry Special Funds of Guangdong Province (no. 2010A , no.

6 6 The Scientific World Journal 2011A , and no. 2012A ), and the Fundamental Research Funds for the Central Universities (no. 2013ZM093 and no. 2013ZP0017). References [1] C.-S. Chang, S.-J. Chang, Y.-K. Su et al., Nitride based power chip with indium-tin-oxide p-contact and Al back-side reflector, Japanese Applied Physics, vol. 44, no. 4, pp , [2] Y.P.Hsu,S.J.Chang,Y.K.Suetal., InGaN/GaNlight-emitting diodes with a reflector at the backside of sapphire substrates, Electronic Materials,vol.32,no.5,pp ,2003. [3] H. Kim, S.-N. Lee, Y. Park, K.-K. Kim, J. S. Kwak, and T.- Y. Seong, Light extraction enhancement of GaN-based light emitting diodes using MgF 2 /Al omnidirectional reflectors, Applied Physics, vol. 104, no. 5, Article ID , [4] J.-Q.Xi,H.Luo,A.J.Pasquale,J.K.Kim,andE.F.Schubert, Enhanced light extraction in GaInN light-emitting diode with pyramid reflector, IEEE Photonics Technology Letters, vol.18, no.22,pp ,2006. [5]Y.Lee,C.Lee,andC.Chen, Effectofsurfacetextureand backside patterned reflector on the AlGaInP light-emitting diode: high extraction of waveguided light, IEEE Quantum Electronics, vol. 47, no. 5, pp , [6]Y.S.Zhao,D.L.Hibbard,H.P.Lee,K.Ma,W.So,andH. Liu, Efficiency enhancement of InGaN/GaN light-emitting diodes with a back-surface distributed Bragg reflector, Journal of Electronic Materials, vol. 32, no. 12, pp , [7] C. Huang, H. Ku, and S. Chao, Light extraction enhancement for InGaN/GaN LED by three dimensional auto-cloned photonics crystal, Optics Express, vol. 17, no. 26, pp , [8] B.J.Kim,H.Jung,S.H.Kim,J.Bang,andJ.Kim, GaN-based light-emitting diode with three-dimensional silver reflectors, IEEE Photonics Technology Letters, vol. 21, no. 11, pp , [9]Y.Chang,J.Liou,andW.Liu, Improvedlightextraction efficiency of a high-power GaN-based light-emitting diode with a three-dimensional-photonic crystal (3-D-PhC) backside reflector, IEEE Electron Device Letters, vol. 34, no. 6, pp , [10] J.-K. Liou, P.-C. Chou, C.-C. Chen et al., Implementation of high-power GaN-based LEDs with a textured 3-D backside reflector formed by inserting a self-assembled SiO 2 nanosphere monolayer, IEEE Transactions on Electron Devices, vol. 61, pp , [11] W. Lin, D. Wuu, S. Huang, and R. Horng, Enhanced output power of near-ultraviolet InGaN/AlGaN LEDs with patterned distributed Bragg reflectors, IEEE Transactions on Electron Devices,vol.58,no.1,pp ,2011. [12] J. K. Kim, J.-Q. Xi, and E. F. Schubert, Omni-directional reflectors for light-emitting diodes, in 10th Light-Emitting Diodes: Research, Manufacturing, and Applications,K.P.Streubel,H.W. Yao,andE.F.Schubert,Eds.,vol.6134ofProceedings of SPIE, [13] J.-W. Pan, P.-J. Tsai, K.-D. Chang, and Y.-Y. Chang, Light extraction efficiency analysis of GaN-based light-emitting diodes with nanopatterned sapphire substrates, Applied Optics, vol.52,no.7,pp ,2013. [14] X. Chen, F. Kong, K. Li, Q. Ding, M. Zhang, and W. Li, Study of light extraction efficiency of flip-chip GaN-based LEDs with different periodic arrays, Optics Communications, vol.314,pp , [15] P. Wang, B. Cao, W. Wei, Z. Gan, and S. Liu, Improved light extraction of GaN-based light-emitting diodes by ITO patterning with optimization design, Solid-State Electronics, vol.54,no.3,pp ,2010.

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