Architecture multi-asip pour turbo décodeur multi-standard. Amer Baghdadi.

Transcription

1 Architecture multi-asip pour turbo décodeur multi-standard Amer Baghdadi Télécom Bretagne Technopôle Brest-Iroise - CS Brest Cedex 3 - FRANCE GDR-ISIS, Paris. 4 janvier, Outline Introduction Forward error correction and flexibility requirements Convolution turbo codes Turbo decoding iterative principle BCJR SISO Algorithm Parallelism levels classification ASIP design for flexible turbo decoding Parameters of flexibility Overall ASIP Architecture Basic Computational Blocs Instruction Set Sample illustration program NoC-based multi-asip turbo decoding Multi-ASIP platform Adaptive NoC architecture Prototyping and on-board validation Conclusion and perspectives page A.Baghdadi, Télécom Bretagne Journée GDR-ISIS, Paris, 4 Jan

2 Flexibility requirements in standards for forward error correction codes Standard Codes Rates States Bloc-size Throughput EDGE CC 6/7, / bps UMTS CC btc /, /3 / up to 3 bps up to Mbps LTE CC btc /3 / up to Mbps HSDPA btc / - 3/ up to 4.4 Mbps CDMA CC btc / - /6 / - / up to 38 bps up to Mbps IEEE8. (WLAN) CC CC LDPC / - 3/4 /3 / - 5/ up to Mbps - up to 45Mbps IEEE8.6 (WiMax) CC dbtc LDPC / - 7/8 /3,/,/3,3/4, 5/6 / - 3/ up to 4 up to 48 up to 34 - up to 75 Mbps up to 75 Mbps Inmarsat btc / 6 up to 68 up to 64 bps DVB-S LDPC /4-9/ - 6,64 up to 55 Mbps CC: Conv olutional Code btc: binary Turbo Code dbtc: duo-binary Turbo Code LDPC: Low-density parity -chec code page 3 A.Baghdadi, Télécom Bretagne Journée GDR-ISIS, Paris, 4 Jan Application Convolutional turbo codes Code parameters Number of States Input bits (M-binary) d i, s i, s i, s i,3 c i, c i, R=/, 8 state, binary Code rate Puncturing Polynomials R=/3, 8 states, duo-binary d i, d i, s i, s i, s i,3 c i, c i, Parallel concatenation of recursive systematic convolutional codes Turbo principle in receiver Source Interleaver Encoder Encoder systematic redundancy redundancy c i,3 Modulator page 4 A.Baghdadi, Télécom Bretagne Journée GDR-ISIS, Paris, 4 Jan

3 Convolutional turbo decoding Iterative decoding of concatenated convolutional codes SISO module (Soft Input Soft Output) Exchange of probabilistic information between decoders MAP algorithm: BCJR or Forward Bacward red sys Component Decoder natural order red Π Π Π - Component Decoder interleaved order Output (Hard decision) Improve convergence speed using parallelism page 5 A.Baghdadi, Télécom Bretagne Journée GDR-ISIS, Paris, 4 Jan BCJR SISO algorithm max-log-map computations SI BCJR-SISO. MAP γ α extrinsic SO Bit - 3 α Bit Bit + () 3 Trellis of a 4-states binary code γ(,) + () 3 Bit + 3 α ( ) max s = ( α ( s ) + ( s γ, s) ) ( ) max s = ( + ( s ) + γ + ( s, s )) S' max ex L ( d i ) = ( s', s)/ d( s', s) i ex ( α ( s ) + γ ( s, s) + ( s) ) page 6 A.Baghdadi, Télécom Bretagne Journée GDR-ISIS, Paris, 4 Jan S ' 3

4 BCJR Metric Level Parallelism (level ) Parallelism of trellis transitions SI BCJR-SISO. MAP α Parallelism of BCJR computations (recursions, extrinsic information) Bloc N α γ extrinsic SO extrinsic Bloc N α Bit Bit + α() 3 Trellis of a 4-states binary code extrinsic γ(,) () 3 T time T/ time page 7 A.Baghdadi, Télécom Bretagne Journée GDR-ISIS, Paris, 4 Jan BCJR-SISO Decoder Level Parallelism (level ) Component-decoder parallelism Classical (serial) decoding Shuffled decoding Component decoder Component decoder Sub-bloc parallelism Bloc N Bloc BCJR-SISO N?α? N d?α??α? Sub-bloc BCJR-SISO Sub-bloc BCJR-SISO Sub-bloc BCJR-SISO Sub-bloc BCJR-SISO page 8 A.Baghdadi, Télécom Bretagne Journée GDR-ISIS, Paris, 4 Jan 4

5 Turbo-decoder Level Parallelism (level 3) Iteration parallelism Frame i Turbo Decoder Frame i- Turbo Decoder Frame i- Turbo Decoder Iteration Iteration Iteration Frame i Turbo Decoder Frame parallelism Iteration Frame i+ Turbo Decoder Iteration page 9 A.Baghdadi, Télécom Bretagne Journée GDR-ISIS, Paris, 4 Jan Classification Parallelism technique classification Level Parallelism Trellis transitions Restricted Optimal BCJR metric BCJR computations BCJR-SISO decoder Sub-blocs Component decoders Parallelism degree Area overhead Turbo-decoder Iterations Frames Unlimited Unaffordable page A.Baghdadi, Télécom Bretagne Journée GDR-ISIS, Paris, 4 Jan 5

6 Outline Introduction Flexibility requirements in forward error correction Convolution turbo codes Turbo decoding iterative principle BCJR SISO Algorithm Parallelism levels classification ASIP design for flexible turbo decoding Parameters of flexibility Overall ASIP Architecture Basic Computational Blocs Instruction Set Sample illustration program NoC-based multi-asip turbo decoding Multi-ASIP platform Adaptive NoC architecture Prototyping and on-board validation Conclusion page A.Baghdadi, Télécom Bretagne Journée GDR-ISIS, Paris, 4 Jan Flexibility requirements in applications using convolutional turbo codes Application Rate Throughput (Mbps) Code Bloc size (bits) CCSDS (deep space) /6 /,6 binary, 6-state UMTS (mobile 3G) /3 binary, 8-state 4 54 CDMA (mobile 3G) /5 / binary, 8-state LTE (mobile) /3 binary, 8-state DVB-RCS (TV) /3 6/7 duo-binary, 8-state DVB-RCT (TV) /, /4 duo-binary, 8-state Inmarsat (multimedia) /,64 binary, 6-state 68 WiMAX / 5/6 75 duo-binary, 8-state Homeplug AV /,6/ duo-binary, 8-state 8, 88, 46 + Trellis, puncturing, interleaver, concatenation, # of component decoders page A.Baghdadi, Télécom Bretagne Journée GDR-ISIS, Paris, 4 Jan 6

7 Design decisions and ASIP flexibility Flexibility Variants Decisions Concatenation Parallel Target parallelism (level ) 3 transitions BCJR units Polynomial Encoder systematic recursive < 6 binary states or 8 duobinary states ASIP Architecture Interleaver All Rate Puncturing Bloc size >= /7 for simple binary and /3 for duo-binary Patterns of 6 bits < symbol (4 windows) Flexibility DSP and lowperformance processor based solutions ASIP Algorithm Iterative process ctrl. Max-log-MAP Fixed iterations # SF for extrinsic info. Dedicated ASIC-target solutions Log (throughput) page 3 A.Baghdadi, Télécom Bretagne Journée GDR-ISIS, Paris, 4 Jan Complete ASIP Architecture Bloc α extrinsic time SIMD architecture, 7-stage pipeline, dedicated and extensible instruction set (~ 3 insts) Maximum internal parallelism IO: pacet interface to exchange information with other processors Supports all standardized turbo codes (single and double binary) decision decision Input data mem top Input data mem bottom TurbASIP Conf iguration memory Program memory Forward recursion unit A ot Bacward recursion unit B Future metrics memory Control unit Cross memory A B Cross memory B A Extrinsic information Extrinsic information Extrinsic inf o mem top Extrinsic inf o mem bottom Past metrics memory page 4 A.Baghdadi, Télécom Bretagne Journée GDR-ISIS, Paris, 4 Jan 7

8 BCJR recursion unit 6 branch metrics, depending on puncturing Up to 3 transitions per processing matrix 8 Max nodes Column wise: state metrics Row wise: extrinsic information decision PR_A DECISION_A RC_A global ALU x6 x6 RG_A BM generator Processing Matrix x6 RMC_A State RIE_A x4 Extrinsic information memory Extrinsic information state metrics state metrics RADD_A RC_A(j) RG_A Max node max max RT_A(i,j) max RMC_A Adder node RADD_A ou RMC_A RADD_A(i,j) page 5 A.Baghdadi, Télécom Bretagne Journée GDR-ISIS, Paris, 4 Jan Adder Node Forward Adder Node Fw/Bw RG_A γ RT_A(i,j) Basic computation blocs RC_A(j) Metric()/Info() α + γ R ADD_A(i,j) RMC_A α S ' max ( α ( s ) + ( s, s) ) α ( s) = γ RG_A γ RT_A(i,j) RC_A(j) Metric()/Info() RMC_A α R ADD_A(i,j) α + γ ex max ( α ( s ) + γ ( s, s) + ( s) ) ( s', s)/ d( s', s) i ex L ( d i ) = RG_B γ RT_A(i,j) RMC_B page 6 A.Baghdadi, Télécom Bretagne Journée GDR-ISIS, Paris, 4 Jan decision max ( + ) ( s) = ( s ) γ ( s, s + + ) S ' RC_B(j) α Metric()/Info() + γ R ADD_B(i,j) State S S S S3 S4 S5 S6 S7 Config for 8 states db Adder Node Bacward Processing Matrix 8

9 Basic computation blocs (Cont.) 4-Input Max Finder max RADD Reg max RMC Reg / RADD Reg max Row Wise (8 x 4-Input MF) Column Wise (8 x 4-Input MF) Processing Matrix max ( + ) ( s) = ( s ) γ ( s, s + + ) S ' max ( α ( s ) + ( s, s) ) α ( s) = γ S ' RMC Reg page 7 A.Baghdadi, Télécom Bretagne Journée GDR-ISIS, Paris, 4 Jan ex max ( α ( s ) ( s, s) ( s) ) ( s ', s )/ ( s ', s ) i + γ + d ex L ( d i ) = Row Wise (6 x -Input MF) Control, pipeline stages, and memories Write Al pha & Beta Init Memory Read Al pha & Beta Init Memory 6 Config. A&B Memor y FE DEC OPF BM BM EXE ST Program Control Pipeline Registers Inst. Decod. Adr. Gen. Pipeline Registers Operand Fetch Pipeline Registers Gamma Computa tion Extrinsic Scaling Pipeline Registers Gamma Cont. Computa tion Pipeline Registers ACS Units Pipeline Registers Extrinsic Info Computa tion NoC Pacet Cons truction Extrinsic Info. Or Hard dec. Out. Multipl exed Output 8 Ext_enabl e Ext_enabl e decision_enabl e 8 6 Program Memor y Cross M etric Memor y 5 7 Input D ata Top & Bottom Interleavi ng Memor y Extrinsic Input D ata Top & Bottom page 8 A.Baghdadi, Télécom Bretagne Journée GDR-ISIS, Paris, 4 Jan 9

10 ASIP instruction set Registers/Memory Transfer Trellis configuration State metric initialization Windowing support Control ZOL Repeat Operative Map Forward/Bacward recursion State metrics Extrinsic info. Hard decisions Max tree Column Max between Inputs Max between 4 Inputs Row Max between Inputs Max between 4 Inputs page 9 A.Baghdadi, Télécom Bretagne Journée GDR-ISIS, Paris, 4 Jan ASIP: application example double binary 8-states code _loop: _LW: _RW: LD_CONFIG LD_CONFIG LD_CONFIG LD_CONFIG 3 SET_SIZE 48 LD_REC ZOLB _LW,_LW,_RW DATA_LEFT add m max m x4 DATA_RIGHT add m max m NO_LD add i x4 max i max i ST_EXT ST_REC jmp _loop single binary 8-states code _loop: _LW: _RW: LD_CONFIG LD_CONFIG SET_SIZE 4 LD_REC ZOLB _LW,_LW,_RW DATA_LEFT add m x max m DATA_RIGHT add m max m NO_LD add i x max i max i ST_EXT ST_REC jmp _loop ~ 3,5 cycles /symbol page A.Baghdadi, Télécom Bretagne Journée GDR-ISIS, Paris, 4 Jan

11 DATA_LEFT add m max m ASIP: application example (cont.) x4 BM computations and accumulation with old state metrics DECISION_A global ALU RC_A x6 Processing Matrix Extrinsic information state metrics All trellis transitions are processed in parallel RG_A γ RC_A(j) Metric()/Info() x6 RG_A BM generator x6 RMC_A x4 RIE_A state metrics (parallelism level : Parallelism of trellis transitions) RT_A(i,j) RMC_A α α + γ R ADD_A(i,j) PR_A Extrinsic info memory EXE pipeline stage page A.Baghdadi, Télécom Bretagne Journée GDR-ISIS, Paris, 4 Jan DATA_LEFT add m max m ASIP: application example (cont.) x4 Select and update state metrics D EC ISION _A global ALU Extrinsic information x6 Use of 4-input Max function in column wise configuration for each state R C _A Processing Matrix state metrics State metrics are saved in RMC registers x6 R G_A BM generator x6 R MC _A R IE_A x4 state metrics PR_A EXE pipeline stage page A.Baghdadi, Télécom Bretagne Journée GDR-ISIS, Paris, 4 Jan

12 Design and verification flows LISA files ASM file (code + memory contents) LISA level Macro assembler, assembler & liner exe file Simulator & debugger HDL optimization options Processor generator Memory-la yout file exetxt HDL level ASIP HDL files HDL simulation memory files Memory-content files (mmap) Simulator HDL Synthesis results Synthesis FPGA memory IP Memory-content files (coe) mmapcoe FPGA level Users constraint files (ucf) Place&Route Chipscope file (cdc) FPGA Chipscope Pro Core Inserter Chipscope Pro Analyser page 3 A.Baghdadi, Télécom Bretagne Journée GDR-ISIS, Paris, 4 Jan Outline Introduction Flexibility requirements in forward error correction Convolution turbo codes Turbo decoding iterative principle BCJR SISO Algorithm Parallelism levels classification ASIP design for flexible turbo decoding Parameters of flexibility Overall ASIP Architecture Basic Computational Blocs Instruction Set Sample illustration program NoC-based multi-asip turbo decoding Multi-ASIP platform Adaptive NoC architecture Prototyping and on-board validation Conclusion page 4 A.Baghdadi, Télécom Bretagne Journée GDR-ISIS, Paris, 4 Jan

13 High-throughput multi-asip turbo decoder 3 dedicated networs I/O networ futur I/O Interface futur Networ interface: interleaver Low latency for the extrinsic information networ Multi-stage interconnecti on networs M canal M canal ASIP futur Mémoires passé ASIP Mémoires passé M info extr M info extr State metric networ M info extr ASIP 3 Mémoires passé futur ASIP Mémoires passé M canal M canal Component decoder Component decoder Extrinsic information networ M info extr page 5 A.Baghdadi, Télécom Bretagne Journée GDR-ISIS, Paris, 4 Jan NoC for flexible turbo decoding Iterative extensive exchanges of interleaved data require a fully flexible on-chip interconnection networ Support of all interleavers avoid communication conflicts ASIP ASIP ASIP ASIP 3 ASIP 4 ASIP 5 Conflict NoC MEM8 MEM 9 MEM MEM MEM MEM3 MEM4 ASIP 8 ASIP 9 ASIP ASIP ASIP ASIP 3 ASI P ASI P ASIP K- ON-CHIP COMMUCATION NETWORK ASIP K A SI PK+ A SI P K- ASIP K- ASIP K- ASIP 6 ME M5 ASIP 4 COMPON ENT DE CODE R COMP ONENT DE CODER ASIP 7 Butterfly topology ASIP 5 Appropriate NoC topologies explored (Butterfly, Benes, De Bruijn) page 6 A.Baghdadi, Télécom Bretagne Journée GDR-ISIS, Paris, 4 Jan 3

14 Results and more information AFANA Project (Application-Field-Aware Adaptive Networ on chip Architecture) ( ) InPixal ANR Architecture du futur 7- page 7 A.Baghdadi, Télécom Bretagne Journée GDR-ISIS, Paris, 4 Jan Prototyping and on-board validation 8-ASIP prototype using a logic emulation board F = 35 MHz 53% of a single FPGA Xilinx Virtex 5 LX33 Turbo decoding: 5 6 iterations With,5 cycle/symbol (a new ASIP ver) 6 itrations ASIP 3 ASIP ASIP 7 ASIP 6 ASIP ASIP 5 ASIP ASIP 4 Target ASIC: Gbps with -ASIP architecture page 8 A.Baghdadi, Télécom Bretagne Journée GDR-ISIS, Paris, 4 Jan 4

15 References Research contributions from my past and current supervised PhD students: Olivier Muller Atif Raza Jafri Hazem Moussa Selected reference publications:. O. Muller, A. Baghdadi, M. Jezequel, From Parallelism Levels to a Multi-ASIP Architecture for Turbo Decoding, IEEE TVLSI, Vol. 7, Issue:, Page(s): 9-, Jan. 9.. O. Muller, A. Baghdadi, and M. Jezequel, From application to ASIP-based FPGA prototype : a case study on turbo decoding, 9th IEEE/IFIP international symposium on Rapid System Prototyping, June H. Moussa, O. Muller, A. Baghdadi, M. Jézéquel, "Butterfly and Benes-Based on-chip Communication Networs for Multiprocessor Turbo Decoding", DATE 7, April O. Muller, A. Baghdadi, and M. Jezequel, On the Parallelism of Convolutional Turbo Decoding and Interleaving Interference, IEEE Global Telecommunications Conference (GLOBECOM 6), November 6. page 9 A.Baghdadi, Télécom Bretagne Journée GDR-ISIS, Paris, 4 Jan Conclusions Flexibility requirements in channel decoding and turbo decoding applications Turbo decoding and parallelism levels Detailed architecture of a typical ASIP for flexible turbo decoding Illustration of decoding process, pipeline, and resources utilization throughout a detailed application example ASIP design and verification flow NoC-based multi-asip turbo decoding page 3 A.Baghdadi, Télécom Bretagne Journée GDR-ISIS, Paris, 4 Jan 5

16 Perspectives on going wor Towards an innovative universal channel decoder architecture Unifying flexibility-oriented and optimization-oriented approaches UDEC Project (Universal channel DECoder) ( ) ANR Architecture du futur 8- page 3 A.Baghdadi, Télécom Bretagne Journée GDR-ISIS, Paris, 4 Jan 6