SEMI Draft Document 4537 Revision to SEMI M PRACTICE FOR DETERMINING WAFER-NEAR-EDGE GEOMETRY USING PARTIAL WAFER SITE FLATNESS

Transcription

1 SEMI Draft Document 4537 Revision to SEMI M PRACTICE FOR DETERMINING WAFER-NEAR-EDGE GEOMETRY USING PARTIAL WAFER SITE FLATNESS Background Statement Note: This background statement is not part of the ballotted item. It is provided solely to assist the recipient in reaching an informed decision based on the rationale of the activity that preceded the creation of this document. Note: Recipients of this document are invited to submit, with their comments, notification of any relevant patented technology or copyrighted items of which they are aware and to provide supporting documentation. In this context, patented technology is defined as technology for which a patent has been issued or has been applied for. In the latter case, only publicly available information on the contents of the patent application is to be provided. The work on this document began with a SNARF submitted by Fritz Passek of Siltronic AG on October 10, The SNARF addressed the removal of the preliminary status of SEMI M The SNARF was approved on October 11, Except for the addition of several terms, definitions and references the document is unchanged from the current version. Note: Additions are indicated by underline. SEMI M70 was distributed in Nov by Kevin Nguyen as a first draft document for discussion in AWG task force during SEMICON Japan. This letter ballot will be reviewed by the International AWG Task Force and adjudicated by the Silicon Wafer Committee at their meetings in San Francisco, CA, during SEMICON West July 2008.

2 SEMI Draft Document 4537 Revision to SEMI M (Preliminary) PRACTICE FOR DETERMINING WAFER-NEAR-EDGE GEOMETRY USING PARTIAL WAFER SITE FLATNESS 1 Purpose 1.1 Wafer near edge geometry can significantly affect the yield of semiconductor device processing. 1.2 Knowledge of near edge geometrical properties can help the producer and consumer to determine if the dimensional characteristics of a wafer satisfy given geometrical requirements. 1.3 This practice is suitable quantifying the near edge geometry of wafers used in semiconductor device processing. 1.4 The PSFQR or PSFQD metric is suitable for quantifying near edge geometry when applying a site pattern that appropriately covers large parts of the wafer edge. NOTE 1: Acronyms beginning with P are the same as those in Appendix 1 of SEMI M1 except that they relate to the partial sites covering the near edge region. 1.5 Flatness metric is well-established therefore partial site flatness can be used as a process control tool as well as a material exchange specification for edge geometry. 1.6 There are other metrics i.e. ZDD, ESFQR, ROA, some of which quantify more specific aspects of edge geometry. NOTE 2: ERO is frequently employed as a more general term for describing near edge geometry, but as of the approval date of this standard there are no standardized conditions or test procedures for it. As such a general term, ERO is included in the keywords for this standard, even though it is outside the scope of the standard. 2 Scope 2.1 This practice covers calculation of the near edge geometry metrics PSFQR and PSFQD. 2.2 SFQR and SFQD are well known parameters and described in detailed in SEMI MF1530. In contrast to SEMI MF1530 the present practice is dealing exclusively with the non-full sites (i.e., the partial sites). The practice is focused only and specifically on near edge geometry applications. 2.3 The metrics calculated by this practice are based on a thickness data array (see also SEMI MF1530). This array represents the front surface of the wafer when the back surface of the wafer is ideally flat, as when pulled down onto an ideally clean flat chuck. 2.4 This practice is suitable for polished, epitaxial, SOI, or other layer condition. 2.5 The practice is applicable to notched 200 and 300 mm diameter wafers having dimensions in accordance with wafer categories and 1.15 of SEMI M This practice does not cover acquisition of the thickness data array. However, it gives the required characteristics of the thickness data array. NOTICE: This standard does not purport to address safety issues, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory or other limitations prior to use. 3 Limitations 3.1 Deficiencies of data such as inadequate spatial resolution, mispositioning, noise, etc. in the thickness data array used to calculate the metrics may lead to erroneous results. 3.2 The calculations of this practice do not remove wafer shape and therefore are not applicable to data obtained from unclamped wafer single-surface data. 3.3 The reference plane used in the calculation is dependent on the x- and y-length of the sites and the x- and y-offset of the site pattern. Page 2 Doc SEMI

3 4 Referenced Standards and Documents 4.1 SEMI Standards SEMI M1 Specifications for Polished Monocrystalline Silicon Wafers SEMI M20 Practice for Establishing a Wafer Coordinate System SEMI M49 Guide for Specifying Geometry Measurement Equipment for Silicon Wafers for the 130 nm to 65 nm Technology Generations SEMI M59 Terminology for Silicon Technology SEMI M67 (Preliminary Standard) Practice for Determining Wafer Near-Edge Geometry from a Measured Thickness Data Array Using the ESFQR and ESFQD Metrics SEMI M68 (Preliminary Standard) Practice for Determining Wafer Near-Edge Geometry from a Measured Height Data Array Using a Curvature Metric, ZDD SEMI M69 (Preliminary Standard) Practice for Determining Wafer Near-Edge Geometry Using Roll-Off Amount, ROA SEMI MF1530 Test Method for Measuring Flatness, Thickness, and Total Thickness Variation on Silicon Wafers by Automated Non-Contact Scanning NOTICE: Unless otherwise indicated, all documents cited shall be the latest published versions. 5 Terminology 5.1 Many terms used in silicon wafer technology are defined in SEMI M Other Definitions edge roll off (ERO) surface deviations of a large-diameter silicon wafer near the edge, but excluding effects due to wafer edge profiling and surface roughness near edge geometry the topography of a surface of a large diameter silicon wafer in the outer region of the fixed quality area (FQA) partial site a site as defined in SEMI M59 but with some of its area outside the FQA ESFQR near-edge silicon wafer geometry flatness metric similar to SFQR (see Appendix 1 of SEMI M1) that relates to the range of the reference plane deviation within a sector ROA (edge roll off amount) the displacement from the reference line at the measurement point in the nearedge region of an un-chucked silicon wafer. ROA is defined as positive in the direction away from the reference line. (modified as noted from M69) ZDD measure of near-edge curvature of a silicon wafer equal to the radial double derivative of the coordinate z perpendicular to the median plane of the wafer. 6 Summary of Practice 6.1 All partial sites are used for metric calculation. Partial sites are defined by FQA, the site size and offset. Required exclusions are defined. 6.2 A thickness data array is acquired. 6.3 The data array is used to construct a reference plane in each site. 6.4 PSFQR for each site is calculated as the range of the reference plane deviation within the site. 6.5 PSFQD for each site is calculated as the reference plane deviation within the site having the largest absolute value within the site while retaining the sign. 6.6 Recipe parameters are reported. 6.7 PSFQR and PSFQD are reported for each site. Statistical quantities for these parameters are also calculated and reported for each wafer. 7 Apparatus 7.1 Measuring Equipment Suitable for acquiring the thickness data array and transferring it to the calculation software. Page 3 Doc SEMI

4 NOTE 3: A test method for acquiring a suitable thickness data array is being considered for development by the Silicon Wafer Committee The equipment shall perform all necessary calculations and corrections needed to produce the thickness data array internally and automatically, including instrument-dependent exclusion areas. The equipment shall be equipped with a means of detecting and either deleting or identifying invalid data (over-range signal) Thickness resolution shall be 10 nm or smaller Thickness array data point spacing shall be 1 mm or less in two orthogonal directions in the plane of the wafer. The thickness data array coordinate system is per SEMI M The spatial resolution of the thickness data array shall be specified The thickness data array must cover the entire area of the partial sites including the FQA boundary (except in exclusion areas). 7.2 Calculation Software To perform the calculations of this practice and to provide outputs of the results, including statistical parameters as agreed upon by the parties to the test. 8 Procedure 8.1 Define recipe for calculation: Select the fixed quality area (FQA) by specifying the nominal edge exclusion EE. The FQA radius, R FQA = R NOM EE Select the site length L x and length L y. Recommended site lengths are: L x = L y = 20 mm Select the site pattern s x-offset OS x and y-offset OS y Construct a site pattern with N partial sites on the wafer front surface (see Figure 1). 8.2 Determine statistics to be reported for each wafer. As a minimum, these shall include maximum, average, range, standard deviation, and 95 th percentile and any other statistics agreed upon between parties to the test. Acquire the thickness data array in accordance with a method agreed upon by all parties to the practice (see Note 3). 9 Calculations NOTE 4: The following calculations are performed automatically within the calculation equipment. An outline of the calculation structures is provided here to indicate the nature of the procedure 9.1 For each site, 9.2 Generate thickness data for all partial sites based on values from the thickness data array. 9.3 Construct a front surface least-squares reference plane from all the data within the partial site. 9.4 Determine the most positive d max and the most negative d min differences between the thickness data array values and the reference plane within the partial site. 9.5 Record PSFQR for the partial site as d max + d min (peak-to-valley). 9.6 Record PSFQD for the partial site as the larger of d max or d min, maintaining the sign of the original deviation. 9.7 Calculate statistics for each wafer using PSFQR and PSFQD for each partial site on the wafer. 9.8 For tests where the wafer is measured more than once, calculate the maximum, minimum, sample standard deviation, average, and range of all individual partial sites on the sample. 9.9 Record sample standard deviation and other statistical parameters as agreed upon between the parties to the practice. Page 4 Doc SEMI

5 NOTE 1: Recommended partial site pattern on a 300 mm wafer front surface providing 32 partial sites (dark grey color) at FQA radius R FQA = 149 mm, for calculating PSFQR and PSFQD (site lengths L x = L y = 20 mm and x-offset OS x = y-offset OS y = 10 mm). NOTE 2: The coordinate system associated with the sector configuration is consistent with the wafer coordinate system of SEMI M20. Figure 1 Illustration of Partial Sites 10 Report 10.1 Report the following information: 10.2 Date, time of test, 10.3 Identification of operator, 10.4 Location (laboratory) of test, 10.5 Identification of measuring instruments including measuring equipment and calculation equipment (identification of maker, model, software version, etc.), 10.6 Acquisition Spatial Resolution and data point spacing, 10.7 Lot identification and wafer identification, 10.8 Description of sampling plan, if any and 10.9 Recipe: FQA diameter, Site length, L x, L y and Site pattern offset, OS x, OS y Data for each wafer measured PSFQR: Per partial site, and Statistics per wafer (e.g., average, range, standard deviation, other) PSFQD: Per partial site, and Statistics per wafer (e.g., average, range, standard deviation, other) For multi-measurement tests the report shall also include the standard deviation of each set of wafer measurements and such other statistical parameters as have been agreed to by the parties to the test. 11 Keywords ERO; PSFQD; PSFQD; near edge geometry; semiconductor; silicon; wafer Page 5 Doc SEMI

6 NOTICE: SEMI makes no warranties or representations as to the suitability of the standard(s) set forth herein for any particular application. The determination of the suitability of the standard(s) is solely the responsibility of the user. Users are cautioned to refer to manufacturer s instructions, product labels, product data sheets, and other relevant literature respecting any materials or equipment mentioned herein. These standards are subject to change without notice. By publication of this standard, Semiconductor Equipment and Materials International (SEMI) takes no position respecting the validity of any patent rights or copyrights asserted in connection with any item mentioned in this standard. Users of this standard are expressly advised that determination of any such patent rights or copyrights, and the risk of infringement of such rights are entirely their own responsibility. Page 6 Doc SEMI