Research Article Particle Filtering: The Need for Speed

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1 Hindawi Publishing Corporaion EURASIP Journal on Advances in Signal Processing Volume 2010, Aricle ID , 9 pages doi: /2010/ Research Aricle Paricle Filering: The Need for Speed Gusaf Hendeby, 1 Rickard Karlsson, 2 and Fredrik Gusafsson (EURASIP Member) 3 1 Deparmen of Augmened Vision, German Research Cener for Arificial Inelligence, Kaiserslaern, Germany 2 NIRA Dynamics AB, Teknikringen 6, Linköping, Sweden 3 Deparmen of Elecrical Engineering, Linköping Universiy, Linköping, Sweden Correspondence should be addressed o Rickard Karlsson, rickard@isy.liu.se Received 22 February 2010; Acceped 26 May 2010 Academic Edior: Abdelak Zoubir Copyrigh 2010 Gusaf Hendeby e al. This is an open access aricle disribued under he Creaive Commons Aribuion License, which permis unresriced use, disribuion, and reproducion in any medium, provided he original work is properly cied. The paricle filer (PF) has during he las decade been proposed for a wide range of localizaion and racking applicaions. There is a general need in such embedded sysem o have a plaform for efficien and scalable implemenaion of he PF. One such plaform is he graphics processing uni (GPU), originally aimed o be used for fas rendering of graphics. To achieve his, GPUs are equipped wih a parallel archiecure which can be exploied for general-purpose compuing on GPU (GPGPU) as a complemen o he cenral processing uni (CPU). In his paper, GPGPU echniques are used o make a parallel recursive Bayesian esimaion implemenaion using paricle filers. The modificaions made o obain a parallel paricle filer, especially for he resampling sep, are discussed and he performance of he resuling GPU implemenaion is compared o he one achieved wih a radiional CPU implemenaion. The comparison is made using a minimal sensor nework wih bearings-only sensors. The resuling GPU filer, which is he firs complee GPU implemenaion of a PF published o his dae, is faser han he CPU filer when many paricles are used, mainaining he same accuracy. The parallelizaion uilizes ideas ha can be applicable for oher applicaions. 1. Inroducion The signal processing communiy has for a long ime been relying on Moore s law, which in shor says ha he compuer capaciy doubles for each 18 monhs. This echnological evoluion has been possible by down-scaling elecronics where he number of ransisors has doubled every 18 monhs, which in urn has enabled more sophisicaed insrucions and an increase in clock frequency. The indusry has now reached a phase where he power and heaing problems have become limiing facors. The increase in processing speed of he CPU (cenral processing uni) has been exponenial since he firs microprocessor was inroduced in 1971 and in oal i has increased one million imes since hen. However, his rendsalledacoupleofyearsago.thenewrendisodouble he number of cores in CMP (chip mulicore processing), and he number of cores is expeced o follow Moore s law for he nex en years [1]. The sofware communiy is now looking for new programming ools o uilize he parallelism of CMPs, which is no an easy ask [2]. The signal processing communiy has also sared o focus more on disribued and parallel implemenaions of he core algorihms. In his conribuion, he focus is on disribued paricle filer (PF) implemenaions. The paricle filer has since is inroducion in is modern form [3] urned ino a sandard algorihm for nonlinear filering, and is hus a working horse in many curren and fuure applicaions. The paricle filer is someimes believed o be rivially parallelizable, since each core can be responsible for he operaions associaed wih one or more paricles. This is rue for he mos characerisic seps in he PF algorihm applied o each paricle, bu no for he ineracion seps. Furher, as is perhaps less well known, he bole neck compuaion even on CPU s is ofen no he paricle operaions bu he resampling [4], and his is no obvious o parallelize, bu possible. The main seps in he PF and heir complexiy as a funcion of he number N of paricles are summarized below, and all deails are given in Secion 3.

2 2 EURASIP Journal on Advances in Signal Processing (i) Iniializaion: each paricle is sampled from a given iniial disribuion and he weighs are iniialized o a consan; parallelizable and hus O(1). (ii) Measuremen updae: he likelihood of he observaion is compued condiional on he paricle; parallelizable and hus O(1). (iii) Weigh normalizaion: he sum of he weigh is needed for normalizaion. A hierarchical evaluaion of he sum is possible, which leads o complexiy O(log(N)). (iv) Esimaion: he weighed mean is compued. This requires ineracion. Again, a hierarchical sum evaluaion leads o complexiy O(log(N)). (v) Resampling: his sep firs requires explicily or implicily a cumulaive disribuion funcion (CDF) o be compued from he weighs. There are differen ways o solve his, bu i is no obvious how o parallelize i. I is possible o make his a O(log(N)) operaion. There are oher ineracion seps here commened on in more deail laer on. (vi) Predicion: each paricle is propagaed hrough a common proposal densiy, parallelizable and hus O(1). (vii) Opional seps of Rao-Blackwellizaion: if he model has a linear Gaussian subsrucure, par of he sae vecor can be updaed wih he Kalman filer. This is done locally for each paricle, and hus O(1). (viii) Opional sep of compuing marginal disribuion of he sae (he filer soluion) raher han he sae rajecory disribuion. This is O(N 2 ) on a single core processor, bu parallelizable o O(N). I also requires massive communicaion beween he paricles. This suggess he following basic funcions of complexiy for he exreme cases single core, M = 1, and complee parallelizaion, M/N 1: Single-core : f 1 (N) = c 1 + c 2 N, ( ) M Mulicore N 1 : f M (N) = c 3 + c 4 log(n). For a fixed number of paricles and sufficienly large number of cores he parallel implemenaion will always be more efficien. In he fuure, we migh be able o use N = M. However, for he N ha he applicaion requires, he bes soluion depends on he consans. One can here define a break-even number N = sol N (1) { f1 (N) = f M (N) }. (2) This number depends on he relaive processing speed of he single and mulicore processors, bu also on how efficien he implemenaion is. I is he purpose of his conribuion o discuss hese imporan issues in more deail, wih a focus on general purpose graphical processing unis (GPGPUs). We also provide Table 1: Table describing how he number of pipelines in he GPU has changed. (The laes generaion of graphics cards form he wo main manufacurers, NVIDIA, and ATI, have unified shaders insead of specialized ones. These are marked wih.) Model Verex pipes Frag. pipes Year NVIDIA GeForce 6800 Ulra ATI Radeon X850 XT PE NVIDIA Geforce 7900 GTX NVIDIA Geforce 7950 GX ATI Radeon X1900 XTX NVIDIA GeForce 8800 Ulra ATI Radeon HD 2900 XT NVIDIA GeForce 9800 GTX ATI Radeon HD 4870 X NVIDIA GeForce 9800 GT NVIDIA GeForce 295 GTX ATI Radeon HD NVIDIA GeForce 380 GTX he firs complee GPGPU implemenaions of he PF, and use his example as a ground for a discussion of N. Mulicore implemenaions of he PF has only recenly been sudied. For insance, [5] presens a GPU PF for visual 2d racking, [6] focusing on doing parallel resampling on a FPGA, and [7, 8] relaing o his work. To he bes of he auhors knowledge no successful complee implemenaion of a general PF algorihm on a GPU has previously been repored. The organizaion is as follows. Since parallel programming may be unfamiliar o many researchers in he signal processing communiy, we sar wih a brief uorial in Secion 2, where background maerial for parallel programming, paricularly using he graphics card, is reviewed. In Secion 3 recursive Bayesian esimaion uilizing he paricle filer is presened for a GPU implemenaion. In Secion 4 a simulaion sudy is presened comparing CPU and GPU performance. Finally, Secion 5 summarizes he resuls. 2. Parallel Programming Nowadays, here are many ypes of parallel hardware available; examples include mulicore processors, fieldprogrammablegaearrays(fpgas), compuer clusers, and GPUs. GPUs offer low-cos and easily accessible single insrucion muliple daa (SIMD) parallel hardware almos every new compuer comes wih a decen graphics card. Hence, GPUs are an ineresing opion no only for speeding up algorihms bu also for esing parallel implemenaions. The GPU archiecure is also aracive since here is a lo of developmen going on in his area, and suppor srucures are being implemened. One example of his is Marix Algebra on GPU and Mulicore Archiecures (MAGMAs), [9], which brings he funcionaliy of LAPACK o he GPU. There are also many success sories, where CUDA implemenaions of various algorihms have proved several imes faser han normal implemenaions [10].

3 EURASIP Journal on Advances in Signal Processing 3 Texures Iniialize GPU Verex daa Verex processor Raserizer Fragmen processor Frame buffer(s) Figure 1: The graphics pipeline. The verex and fragmen processors can be programmed wih user code which will be evaluaed in parallel on several pipelines. In he laes GPUs hese shaders are unified insead of specialized as depiced Graphics Hardware. Graphics cards are designed o primarily produce graphics, which makes heir design differen from general purpose hardware, such as he CPU. One such difference is ha GPUs are designed o handle huge amouns of daa abou an ofen complex scene in real ime. To achieve his, he GPU is equipped wih a SIMD parallel insrucion se archiecure. The GPU is designed around he sandardized graphics pipeline [11] depiced in Figure 1. I consiss of hree processing seps, which all have heir own purpose when i comes o producing graphics, and some dedicaed memory unis. From having predeermined funcionaliy, GPUs have moved owards providing more freedom for he programmer. Graphics cards allow for cusomized code in wo ou of he hree compuaional unis: he verex shader and he fragmen shader (hese wo seps can also be unified in one shader). As a side-effec, generalpurpose compuing on graphics processing unis (GPGPUs) has emerged o uilize his new source of compuaional power [11 13]. For highly parallelizable algorihms he GPU may ouperform he sequenial CPU Programming he GPU. Thewoprogrammableseps in he graphics pipeline are he verex processor and he fragmen processor, or if hese are unified. Boh hese processors can be conrolled wih programs called shaders. Shaders, or GPU programs, were inroduced o replace fixed funcionaliy in he graphics pipeline wih more flexible programmable processors. Some prominen differences beween regular programming and GPU programming are he basic daa ypes which are available, colors and exures. In newer generaions of GPUs 32 bi floaing poin operaions are suppored, bu he rounding unis do no fully conform o he IEEE floaing poin sandard, hence providing somewha poorer numerical accuracy. Inernally he GPU works wih quadruples of floaing poin numbers ha represen colors (red, green, blue, and alpha) and daa is passed o he GPU as exures. Texures are inended o be picures ha are mapped ono surfaces given by he verices. In order o use he GPU for general purpose calculaions, a ypical GPGPU applicaion has a program srucure similar o Figure 2. Upload program Upload suiable shader code o verex and fragmen shaders Upload daa Upload exures conaining he daa o be processed o he GPU Run program Draw a recangle covering as many pixels as here are parallel compuaions o do Download daa Download he resul from he render buffer o he CPU Figure 2: Work flow for GPGPU programming using he OpenGL shading language (GLSL) GPU Programming Language. There are various ways o access he GPU resources as a programmer. Some of he available alernaives are (i) OpenGL [14] using he OpenGL Shading Language (GLSL) [15], (ii) Cforgraphics(Cg) [16], (iii) DirecX High-Level Shader Language (HLSL) [17], (iv) CUDA [18] if using a NVIDIA graphics card. Shor descripions of he alernaives are given in [8], and more informaion abou hese and oher alernaives can be found in [11, 13, 16]. CUDA presens he user wih a C language for direc applicaion developmen on NVIDIA GPUs. The developmen in his paper has been conduced using GLSL. 3. A GPU Paricle Filer 3.1. Background. The paricle filer (PF) [3] hasproveno be a versaile ool applicable o surveillance [19], fusion of mixed sensors in wireless neworks [20], cell phone localizaion [21], indoor localizaion [22], and simulaneous localizaion and mapping (SLAM) [23]. I exends o problems where nonlineariies may cause problems for radiional mehods, such as he Kalman filer (KF) [24] or banks of KFs [25, 26].Themaindrawbackisisinheren compuaional complexiy. This can, however, be handled by parallelizaion. The survey in [27] deails a general PF framework for localizaion and racking, and i also poins ou he imporance of uilizing model srucure using he Rao-Blackwellized paricle filer (RBPF), also denoed marginalized paricle filer (MPF) [28, 29]. The resul is a

4 4 EURASIP Journal on Advances in Signal Processing PF applied o a lowdimensional sae vecor, where a KF is aached o each paricle enabling efficien and real-ime implemenaions. Sill, boh he PF and RBPF are compuer inensive algorihms requiring powerful processors The Paricle Filer Algorihm. The general nonlinear filering problem is o esimae he sae, x, of a sae-space sysem x +1 = f (x, w ), y = h(x ) + e, where y is he measuremen and w p w (w )ande p e (e ) are he process and measuremen noise, respecively. The funcion f describes he dynamics of he sysem, h he measuremens, and p w and p e are probabiliy densiy funcions (PDFs) of he involved noise. For he imporan special case of linear-gaussian dynamics and linear-gaussian observaions he Kalman filer [24, 30] solves he esimaion problem in an opimal way. A more general soluion is he paricle filer (PF) [3, 31, 32] which approximaely solves he Bayesian inference for he poserior sae disribuion [33] given by p(x +1 Y ) = p(x +1 x )p(x Y )dx, p(x Y ) = p( y x ) p(x Y 1 ) p ( y Y 1 ), where Y ={y i } i=1 is he se of available measuremens. The PF uses saisical mehods o approximae he inegrals. The basic PF algorihm is given in Algorihm 1. To implemen a parallel paricle filer on a GPU here are several aspecs of Algorihm 1 ha require special aenion. Resampling is he mos challenging sep o implemen in parallel since all paricles and heir weighs inerac wih each oher. The main difficulies are cumulaive summaion, and selecion and redisribuion of paricles. In he following secions, soluions suiable for parallel implemenaion are proposed for hese asks. Anoher imporan issue is how random numbers are generaed, since his can consume a subsanial par of he ime spen in he paricle filer. The remaining seps, likelihood evaluaion as par of he measuremen updae and sae propagaion as par of he ime updae, are only briefly discussed since hey are parallel in heir naure. The resuling parallel GPU implemenaion is illusraed in Figure 3. The seps are discussed in more deail in his secion GPU PF: Random Number Generaion. Sae-of-he-ar graphics cards do no have sufficien suppor for random number generaion for direc usage in a paricle filer, since he saisical properies of he buil-in generaors are oo poor. The algorihm in his paper herefore relies on random numbers generaed on he CPU o be passed o he GPU. This inroduces subsanial daa ransfer, as several random (3) (4) (1) Le := 0, generae N paricles: {x (i) 0 } N i=1 p(x 0 ). (2) Measuremen updae: Compue he paricle weighs ω (i) = p(y x (i) )/ N j=1 p(y x (j) ). (3) Resample: (a) Generae N uniform random numbers {u (i) } N i=1 U(0, 1). (b) Compue he cumulaive weighs: c (i) = i j=1 ω (j). (c) Generae N new paricles using u (i) and c (i) : {x + (i) } N i=1 where Pr(x + (i) = x (j(i) ) ) = ω (j(i) ). (4) Time updae: (a) Generae process noise {w (i) } N i=1 p w (w ). (b) Simulae new paricles x (i) +1 = f (x +, (i) w (i) ). (5) Le := + 1 and repea from 2. Algorihm 1:TheParicleFiler[3]. numbers per paricle are needed in each ieraion of he paricle filer. Uploading daa o he graphics card is raher quick, bu performance is sill los. Furhermore, his makes generaion of random numbers a O(N) operaion insead of a O(1) operaion, as would be he case if he generaion was compleely parallel. Generaing random numbers on he GPU suiable for use in Mone Carlo simulaions is an ongoing research opic, see, for example, [34 36]. Implemening he random number generaion in he GPU will no only reduce daa ransfer and allow for a sandalone GPU implemenaion, an efficien parallel version will also improve he overall performance as he random number generaion iself akes a considerable amoun of ime GPU PF: Likelihood Evaluaion and Sae Propagaion. Boh likelihood evaluaion (as par of he measuremen updae) and sae propagaion (in he ime updae) of Algorihm 1, can be implemened sraighforwardly in a parallel fashion since all paricles are handled independenly. Consequenly, boh operaions can be performed in O(1) ime wih N parallel processors, ha is, one processing elemen per paricle. To solve new filering problems, only hese wo funcions have o be modified. As no parallelizaion issues need o be addressed, his is easily accomplished. In he presened GPU implemenaion he paricles x (i) and he weighs ω (i) are sored in separae exures which are updaed by he sae propagaion and he likelihood evaluaion, respecively. One exure can only hold fourdimensional sae vecors in a naural way, bu using muliple rendering arges he sae vecors can be exended when needed wihou any major changes o he code. The idea is hen o sore he sae in several exures. For insance, wih wo exures o sore he sae, he sae vecor can grow o eigh saes. Wih he muliarge capabiliy of modern graphics cards he changes needed are minimal. When he measuremen noise is lowdimensional (groups of a mos 4 dependen dimensions o fi a lookup able in a

5 EURASIP Journal on Advances in Signal Processing 5 y u (i) Measuremen updae ω (i) = p(y x (i) )ω (i) = i ω (i) ω (i) = ω (i) / Resampling c (i) = i j=1 ω (j) j (i) = P 1 (u (i) ) Forward adder Original daa = = = 3 3+4= 7 3+7= 10 Cumulaive sum 3 = Figure 4: A parallel implemenaion of cumulaive sum generaion of he numbers 1, 2, 3, and 4. Firs he sum, 10, is calculaed using a forward adder ree. Then he parial summaion resuls are used by he backward adder o consruc he cumulaive sum; 1, 3, 6, and 10. Backward adder ω (i) x + (i) = x (j(i) ) Time updae x +1 (i) = f (x(i) +, ω (i) ) Figure 3: GPU PF algorihm. The ouer boxes make up he CPU program saring he inner boxes on he GPU in correc order. The figure also indicaes wha is fed o he GPU; remaining daa is generaed on i. uniform vec2 y; uniform sampler2d x, w, pdf; uniform ma2 sqrsigmainv; cons vec2 S 1 = vec2(1., 0); cons vec2 S 2 = vec2(-1., 0); void main(void) { vec2 xmp=exure2d(x,g1 TexCoord[0]. s ). xy; vec2 e = y-vec2(disance(xmp, S 1 ), disance (xmp, S 2 )); e=sqrsigmainv e+vec2(.5,.5); g1 FragColor.x = exure2d(pdf, e).x exure2d(w,g1 Texcoord[0].s).x; } Lising 1: GLSL coded fragmen shader: measuremen updae. exure) he likelihood compuaions can be replaced by fas exure lookups uilizing he fas exure inerpolaion. The resul is no as exac as if he likelihood was compued he regular way, bu he increase in speed is ofen considerable. Furhermore, as discussed above, he sae propagaion uses exernally generaed process noise, bu i would also be possible o generae he random numbers on he GPU. Example (Shader program). To exemplify GLSL source code, Lising 1 conains he code needed for a measuremen updae in he range-only measuremen example in Secion 4. ThecodeisverysimilaroCcode,andisexecuedonce for each paricle, ha is, fragmen. To run he program a recangle is fed as verices o he graphics card. The size of he recangle is chosen such ha here will be exacly one fragmen per paricle, and ha way he code is execued once for every paricle. The keyword uniform indicaes ha he following variable is se by he API before he program is execued. The variable y is hence a wo-componen vecor, vec2, wih he measuremen, and S 1 and S 2 conain he locaions of he sensors. Variables of he ype sampler2d are poiners o specific exure unis, and hence x and w poin ou paricles and weighs, respecively, and pdf he locaion of he lookup able for he measuremen likelihood. The firs line of code makes a exure lookup and rerieves he sae, sored as he wo firs componens of he vecor (color daa) as indicaed by he xy suffix. The nex line compues he difference beween he measuremen and he prediced measuremen, before he error is scaled and shifed o allow for a quick exure look up. The final line wries he new weigh o he oupu GPU PF: Summaion. Summaion is par of he weigh normalizaion (as he las sep of he measuremen updae) and he cumulaive weigh calculaion (during resampling) of Algorihm 1. A cumulaive sum can be implemened using a mulipass scheme, where an adder ree is run forward and hen backward, as illusraed in Figure 4. This mulipass scheme is a sandard mehod for parallelizing seemingly sequenial algorihms based on he scaer and gaher principles. In [11],hese conceps are described in he GPU seing. In he forward pass parial sums are creaed ha are used in he backward pass o compue he missing parial sums o complee he cumulaive sum. The resuling algorihm is O(logN)in ime given N parallel processors and N paricles GPU PF: Resampling. To preven sample impoverishmen, he resampling sep of Algorihm 1 replaces unlikely paricles wih likelier ones. This is done by drawing a new se of paricles {x + (i) } wih replacemen from he original paricles {x (i) } in such a way ha Pr(x + (i) = x (j) ) = ω (j). Sandard resampling algorihms [31, 37] selecnew paricles

6 6 EURASIP Journal on Advances in Signal Processing 1 x y 1 y 2 u (k) S 1 S 2 0 x (1) x (2) x (3) x (4) x (5) x (6) x (7) x (8) Figure 5: Paricle selecion by comparing uniform random numbers ( ) o he cumulaive sum of paricle weighs ( ). k : x + (i) = x (2) x (4) x (5) x (5) x (5) x (7) x (7) x (7) Fragmens x (j) + x (2) x (4) x (5) x (7) Verices p (0) p (2) p (4) p (5) p (7) p (1) p (3) p (6) p (8) Figure 6: Paricle selecion on he GPU. The line segmens are made up by he poins N (i 1) and N (i), which define a line where every segmen represens a paricle. Some line segmens have lengh 0, ha is, no paricle should be seleced from hem. The raserizer creaes paricles x according o he lengh of he line segmens. The line segmens in his figure mach he siuaion in Figure 5. using uniformly disribued random numbers as inpu o he inverse CDF given by he paricle weighs Raserize x (i) + = x (j(i) ), wih j (i) = P 1( u (j(i) ) ), (5) where P is he CDF given by he paricle weighs. The idea for he GPU implemenaion is o use he raserizer o do sraified resampling. Sraified resampling is especially suiable for parallel implemenaion because i produces ordered random numbers, and guaranees ha if he inerval (0, 1] is divided ino N inervals, here will be exacly one random number in each subinerval of lengh N 1. Selecing which paricles o keep is done by drawing a line. The line consiss of one line segmen for each paricle in he original se, indicaed by is color, and where he lengh of he segmens indicae how many imes he paricles should be replicaed. Wih appropriae segmens, he rasering will creae evenly spaced fragmens from he line, hence giving more fragmens from long line segmens and consequenly more paricles of likelier paricles. The properies of he sraified resampling are perfec for his. They make i possible o compue how many paricles have been seleced once a cerain poin in he original disribuion was seleced. The expression for his is N (i) = Nc (i) u ( Nc(i) ), (6) where N is he oal number of paricles, c (i) = i j=1 ω (j) is he ih cumulaive weigh sum, and N (i) he number of paricles seleced when reaching he ih paricle in he Figure 7: A range-only sensor sysem, wih 2D-posiion sensors in S 1 and S 2 wih indicaed range resoluion. Time (s) GPU CPU Number of paricles Figure 8: Comparison of ime used for GPU and CPU. original se. The expression for sraified resampling is vial for parallelizing he resampling sep, and hence o make a GPU implemenaion possible. By drawing he line segmen for paricle i from N (i 1) o N (i),wihn (0) = 0, he paricles ha should survive he resampling sep correspond o a line segmen as long as he number of copies here should be in he new se. Paricles which should no be seleced ge line segmens of zero lengh. Rasering wih uni lengh beween he fragmens will herefore produce he correc se of resampled paricles, as illusraed in Figure 6 for he weighs in Figure 5. The compuaional complexiy of his is O(1) wih N parallel processors, as he verex posiions can be calculaed independenly. Unforunaely, he used generaion of GPUs has a maximal exure size limiing he number of paricles ha can be resampled as a single uni. To solve his, muliple subses of paricles are simulaneously being resampled and hen redisribued ino differen ses, similarly o wha is described in [38]. This modificaion of he resampling sep does no seem o significanly affec he performance of he paricle filer as a whole GPU PF: Compuaional Complexiy. From he descripions of he differen seps of he paricle filer algorihm i is clear ha he resampling sep is he boleneck ha gives he

7 EURASIP Journal on Advances in Signal Processing Time spen (%) Time spen (%) Number of paricles Number of paricles Esimae Measuremen updae Time updae Resample Random numbers Esimae Measuremen updae Time updae Resample Random numbers (a) GPU (b) CPU Figure 9: Comparison of he relaive ime spen in he differen seps paricle filer, in he GPU and CPU implemenaion, respecively. ime complexiy of he algorihm, O(logN) for he parallel algorihm compared o O(N) for a sequenial algorihm. The analysis of he algorihm complexiy above assumes ha here are as many parallel processors as here are paricles in he paricle filer, ha is, N parallel elemens. Today his is a bi oo opimisic, here are hundreds of parallel pipelines in a modern GPU, hence much less han he ypical number of paricles. However, he number of parallel unis is consanly increasing. Especially he cumulaive sum suffers from a low degree of parallelizaion. Wih full parallelizaion he ime complexiy of he operaion is O(logN) whereas a sequenial algorihm is O(N), however he parallel implemenaion uses O(2N) operaions in oal. Tha is, he parallel implemenaion uses abou wice as many operaions as he sequenial implemenaion. This is he price o pay for he parallelizaion, bu is of less ineres as he exra operaions are shared beween many processors. As a resul, wih few pipelines and many paricles he parallel implemenaion will have he same complexiy as he sequenial one, roughly O(N/M)whereM is he number of processors. 4. Simulaions Consider he following range-only applicaion as depiced in Figure 7. The following sae-space model represens he 2Dposiion x +1 = x + w, y = h(x ) + e = x S e, x S 2 2 (7) Table 2: Hardware used for he evaluaion. GPU CPU Model: NVIDIA GeFORCE Inel Xeon Model: 7900 GTX 5130 Driver: NVIDIA Clock speed: 2.0 GHz Bus: PCI Express, 14.4 GB/s Memory: 2.0 GB Clock CenOS 650 MHz OS: speed: 5.1, Processors: 8/24 64 bi (verex/fragmen) (Linux) where S 1 and S 2 are sensor locaions and x conains he 2Dposiion of he objec. This could be seen as a cenral node in a small sensor nework of wo nodes, which easily can be expanded o more nodes. To verify he correcness of he implemenaion a paricle filer, using he exac same resampling scheme, has been designed for he GPU and he CPU. The resuling filers give pracically idenical resuls, hough minor differences exis due o he less sophisicaed rounding uni available in he GPU and he rick in compuing he measuremen likelihood. Furhermore, he performance of he filers is comparable o wha has been achieved previously for his problem. To evaluae he complexiy gain obained from using he parallel GPU implemenaion, he GPU and he CPU implemenaions of he paricle filer were run and imed. Informaion abou he hardware used for his is gahered in Table 2. Figure 8 gives he oal ime for running he filer for 100 ime seps repeaed 100 imes for a se of differen numbers of paricles ranging from 2 4 = 16 o

8 8 EURASIP Journal on Advances in Signal Processing (Noe ha 16 paricles are no enough for his problem, nor is as many as 10 6 needed. However, he large range shows he complexiy beer.) Some observaions: for few paricles he overhead from iniializing and using he GPU is large and hence he CPU implemenaion is he fases. Wih more work opimizing he parallel implemenaion he gap could be reduced. The CPU complexiy follows a linear rend, whereas a firs he GPU ime hardly increases when using more paricles; parallelizaion pays off. For even more paricles here are no enough parallel processing unis available and he complexiy becomes linear, bu he GPU implemenaion is sill faser han he CPU. Noe ha he paricle selecion is performed on 8 processors and he oher seps on 24, see Table 2,and hence ha he degree of parallelizaion is no very high wih many paricles. A furher analysis of he ime spen in he GPU implemenaion shows which pars are he mos ime consuming, see Figure 9. The main cos in he GPU implemenaion quickly becomes he random number generaion (performed on he CPU), which shows ha if ha sep can be parallelized here is much o gain in performance. For boh CPU and GPU he ime updae sep is almos negligible, which is an effec of he simple dynamic model. The GPU would have gained from a compuaionally expensive ime updae sep, where he parallelizaion would have paied off beer. To produce an esimae from he GPU is relaively more expensive han i is wih he CPU. For he CPU all seps are O(N) whereas for he GPU he esimae is O(log N) where boh he measuremen updae and he ime updae seps are O(1). No couning he random number generaion, he major par of he ime is spen on resampling in he GPU, whereas he measuremen updae is a much more prominen sep in he CPU implemenaion. One reason is he implemened hardware exure lookups for he measuremen likelihood in he GPU. 5. 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