35 th Design Automation Conference Copyright 1998 ACM

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1 Using Reongurable Computing Tehniques to Aelerate Problems in the CAD Domain: A Case Study with Boolean Satisability Peixin Zhong, Pranav Ashar, Sharad Malik and Margaret Martonosi Prineton University and NEC CCRL pzhong, sharad, mrm@ee.prineton.edu, ashar@rl.nj.ne.om Abstrat The Boolean satisability problem lies at the ore of several CAD appliations, inluding automati test pattern generation and logi synthesis. This paper desribes and evaluates an approah for aelerating Boolean satisability using on- gurable hardware. Our approah harnesses the inreasing speed and apaity of eld-programmable gate arrays by tailoring the SAT-solver iruit to the partiular formula being solved. This input-spei tehnique gets high performane due both to (i) a diret mapping of Boolean operations to logi gates, and (ii) large amounts of ne-grain parallelism in the impliation proessing. Overall, these strategies yields impressive speedups (>200X in many ases) ompared to urrent software approahes, and they require only modest amounts of hardware. In a broader sense, this paper alerts the hardware design ommunity to the inreasing importane of input-spei designs, and douments their promise via a quantitative study of input-spei SAT solving. 1 Introdution While hardware aelerators for CAD are not new, the inreasing apaity and speed of eld-programmable gate arrays (FPGAs) oers exibility and omputing power not available before. The hardware an be reused for dierent appliations and an be easily updated to aommodate new developments in algorithms. This paper introdues an novel approah for aelerating the Boolean satisability (SAT) problem using ongurable omputing hardware. In our implementation of the SAT problem, we have harnessed this exibility by implementing the SAT solver iruit on an \input-spei" basis. That is, a iruit is generated espeially for eah SAT formula to be solved. Sine Boolean satisability approahes are logial-operation-intensive, the hardware approah an show large advantages by mapping the SAT expressions diretly to logi gates, and by harnessing large amounts of parallelism in the evaluation of the logi. While the bulk of the ongurable omputing appliations urrently implemented have been fairly simple dataentri systoli designs, our design shows the potential of ustom omputing on diult problems with omplex ontrol strutures. We have implemented a tree searh algorithm, as opposed to the generally-simpler signal proessing pipelines ommon to ongurable omputing thus far. In addition, wehave also implemented a hardware version of nonhronologial baktraking similar to that seen in software SAT solvers [11]. This requires omplex ontrol strutures to manage the baktraking steps. These implementations demonstrate ongurable omputing's potential for impat on a muh broader set of appliations, partiularly in CAD domain, than may initially have been onsidered. 2 The SAT Problem The Boolean satisability (SAT) problem is a well-known onstraint satisfation problem with many appliations in omputer-aided design of integrated iruits, suh as test generation, logi veriation and timing analysis. Given a Boolean formula, the goal is either to nd an assignment of 0-1 values to the variables so that the formula evaluates to 1, or to establish that no suh assignment exists. The Boolean formula is typially expressed in onjuntive normal form (CNF), also alled produt-of-sums form. Eah sum term (lause) in the CNF is a sum of single literals, where a literal is a variable or its negation. In order for the entire formula to evaluate to 1, eah lause must be satised, i.e., at least one of its literals should be 1. An assignment of 0-1 values to a subset of variables (alled a partial assignment) might satisfy some lauses and leave the others undetermined. If an undetermined lause has only one unassigned literal in it, that literal must evaluate to 1 in order to satisfy the lause. In suh a ase, the orresponding variable is said to be implied to that value. A variable is onsidered free if neither assigned nor implied. A onit or ontradition arises if the same variable is implied to be dierent values. This means that the orresponding partial assignment annot be a part of any valid solution. Most urrent SAT solvers are based on the Davis-Putnam algorithm [4]. This is a baktrak searh algorithm. The basi algorithm begins from an empty assignment. It proeeds by assigning a 0 or 1 value to one free variable at a time. After eah assignment, the algorithm determines the diret and transitive impliations of that assignment on other variables. If no ontradition is deteted after the impliation proedure, the algorithm piks the next free variable, and repeats the proedure (forward searh). Otherwise, the algorithm attempts a new partial assignment by omplementing the most-reently assigned variable (baktrak). If this also leads to ontradition, this variable is reset to the free value and the next most-reently assigned variable is omplemented. The algorithm terminates when: (i) no free variables are available and no ontraditions have been enountered (a solution has been found), or (ii) it wants to baktrak beyond the rst variable, whih means all possible assignments have been exhausted and there is no solution to the problem. Determining impliations is ruial to pruning the searh spae sine it allows the algorithm to skip entire regions of the searh spae orresponding to ontraditory partial assignments. Every implied variable orresponds to one less free variable to branh on. Unfortunately, deteting impli x-98/0006/$ th Design Automation Conferene Copyright 1998 ACM DAC98-06/98 San Franiso, CA USA

2 ations in software is very slow. Eah lause ontaining the newly assigned or implied variable is sanned and updated sequentially, with the proess repeated until no new impliations are deteted. Our intuition for hardware speedup potential in the SAT algorithm stems from reognizing that the impliation proedure entral to the algorithm is both highly parallelizable and easily mapped to basi logi gates. Our entire hardware arhiteture is designed to take advantage of this parallelism. Setion 4 details our mapping of the algorithm onto reon- gurable hardware in a formula-spei manner. Reent software implementations of the SAT algorithm have enhaned it in several ways while maintaining the same basi ow [8, 3, 12, 11]. The ontribution of the GRASP work [11] is notable sine it applies nonhronologial baktraking and dynami lause addition to prune the searh spae further. Very signiant improvements in run time are reported. Reognizing nonhronologial baktraking as an important feature, Setion 5 shows how it an be mapped to reongurable hardware with signiant improvements in run time. 3 The Promise of Congurable Computing Speial-purpose hardware aelerators for CAD problems are not new. This approah, however, usually suers from long development time and high ost. The growth of eld programmable logi devies allows appliation-spei hardware without the osts of fabriation. The SRAM-based programmable logi devies (suh as Xilinx FPGAs) allow the same hip to be reprogrammed to dierent iruits an unlimited number of times. One suessful appliation of suh devies is logi emulation. A logi design is mapped to an FPGA array and simulated before it is atually fabriated. An emulator is many orders of magnitude faster than simulation on a general purpose omputer. The development of FPGAs has also led to the advent of eld-programmable ustom omputing mahines. The abundant programmable logi omponents and routing resoures are used to form speial-purpose omputers exploiting ne-grain parallelism. Suh ustom omputing mahines have ahieved very high performane in signal proessing, geneti analysis, and ryptography appliations. Previous work mostly onentrated on data-entri problems with relatively simple logi ontrol. Inreasing density in programmable logi opens up exiting opportunities for hardware aeleration for omplex omputations. As feature sizes shrink even further, 1M-gate FPGAs will be feasible by roughly the year 2001 [10]. With programmability and high integration densities, we an reate a mahine speialized not only to the appliation but also to the input data assoiated with a spei problem. Our hoie of Boolean satisability (SAT) as a ase study here was guided by two main fators: It is a searh-intensive appliation, as opposed to dataintensive appliations with simple ontrol found in many previous studies of ongurable omputing. It is also a basi NP-omplete problem that is ore to many important problems. Gaining experiene with this problem will help us aelerate a wide range of appliations. It ontains a signiant amount of bit-level logi operations. This makes it very amenable for mapping to ongurable hardware. At this time, we know of three interesting proposals for solving SAT using reongurable hardware [13, 1, 9]. Suyama et al. [13] have proposed their own SAT algorithm - instead of the Davis-Putnam approah - for implementation in reongurable hardware. The searh uses full assignment to explore the spae. In their paper, they aknowledge that this is not as eient as a baktrak searh algorithm. The proposal by Abramovii and Saab [1] is also not an implementation of the Davis-Putnam algorithm. Their proposal basially amounts to an implementation of a PODEMbased [6] algorithm in reongurable hardware. Therefore it is diult to handle a generi CNF formula diretly. On the other hand, our approah is more general and an exploit heuristis not available to PODEM. Rashid et al. [9] implement small instanes of the PO- DEM algorithm on a Xilinx XC6216. While mapping and ompilation issues are presented in detail, there are urrently no performane results for their approah. 4 FPGA Mapping: Basi Baktrak Searh 4.1 Hardware Organization Our hardware implementation has two parts: (i) the impliation iruit (ii) a state mahine to manage the baktrak searh. Given a SAT formula, a VHDL desription of the hardware is generated automatially. The speedup over software arises from our implementation of the impliation iruit. It nds all diret impliations of newly-assigned or newly-implied variables in a single lok yle. Consequently, all transitive impliations of a new variable assignment an be determined in a few yles. Sine all lauses are examined in one yle, parallelism is quite onsiderable in pratie. For the aim yes1-1 example in the DIMACS benhmark suite, this approah yields an average of 41.9 eetive lause evaluations per yle. b out out out dout e out out a state a imp astate a imp D Q D Q GClear a out LContra a out LChange Figure 1: Ciruit for impliation and onit detetion. Figure 1 shows the details of the impliation iruit. The state of eah variable in the iruit is enoded into two bits, (v; v). A free literal is (0; 0). The 1 value of the variable is represented by (1;0) and the 0 value by (0;1). Impliations are easy to determine. For a lause with n literals, if n-1 literals are 0, the last literal is implied to 1. In our enoding, given the lauses ( + a)( d + a)( b + + a)(e +a)( +a), a is implied by + d + b and a is implied by e+, as shown in Figure 1. If both v and v are implied or assigned to be true, there is a ontradition. No solution exists with this partial assignment.

3 GContra GChange GClear E il E ir /10 init E il (v imp+v imp)/01 E il(v imp+v imp)/00 GContra/10 ative 1 ative 0 v i-1 v i v i+1 Clok GChange GContra GClear E il E ol E ir Clk LChange LContra LClear E or GChange LChange GContra LContra GClear LClear E il E or E ol E ir Clk GChange LChange GContra LContra GClear LClear E il E or E ol E ir Clk E ir/10 passive 1 passive 0 Figure 2: Global Ciruit Topology The transitive impliation may inlude yli loops. Sine the impliation is monotoni, hanging from 0 to 1 due to our 2-bit enoding, it will never ause osillation. A D ip- op is used with eah literal, so new impliations will propagate one level in one yle. The LChange signal heks new value hanges. Impliations nish when no new hanges are found. In order to avoid heavy ommuniation with a host omputer, searh ontrol is also implemented in hardware. A state mahine is implemented for eah variable and they are onneted aording to the order of searh, as in Figure 2. Eah box in the gure ontains the impliation iruit and the state mahine for eah variable. This distributed topology keeps global signals to a minimum and redues hardware osts. Atany instant, only one state mahine is in ontrol. One that state mahine has nished proessing, it asserts Eor to transfer ontrol to the state mahine on the right (if progressing forward in the omputation) or it asserts Eol to pass ontrol to the left (if baktraking). Eah state mahine is aware of whether its variable has been assigned, implied or is free. The state mahine for a single variable is shown in Figure 3. The ve states in the state mahine are enoded by three bits. Two bits orrespond to the values of the positive and negative literals of its variable. The third bit indiates whether this partiular state mahine is ative. The inputs to eah state mahine are the Enable signals from its left and right neighbors, and the global ontradition (GContra) and hange (GChange) signals. State mahine outputs are the enable signals, Eol and Eor that pass ontrol to the left or right. System operation is fairly simple. After initialization, all the state mahines are in the init state. When a state mahine reeives an enable signal, it hanges its states. If ontrol is transferred from the left, it an only be in the init state. If this variable's value is not implied, it asserts value 1(ative 1) and determines all the transitive impliations of that assignment. If a ontradition is deteted, it will try the value 0 instead (ative 0) and repeat the impliation step. If the impliation settles without a ontradition, it transfers ontrol to the state mahine on its right and it transitions to the passive 1 state. From ative 0, ifa ontradition is deteted, it will baktrak. Its state is reset to init and the ontrol is passed to the left. On the other hand, if impliations settle without a ontradition, then it moves from ative 0 to passive 0 and passes the ontrol to the right. If, as above, ontrol is transferred to a state mahine from the left, but its variable's value has already been implied by a previous assignment, then it merely passes ontrol to the state mahine on its right on the next lok yle and re- Figure 3: State Diagram for Baktraking Mahine mains in the init state. Its output value will be maintained by the impliation. If ontrol is transferred to a state mahine from the right, the system is baktraking. If the variable has been implied by some previous assignment, the state mahine is in the init state now. It simply passes ontrol to the variable on its left. If the variable urrently has the assigned value 1(passive 1), then it is hanged to 0 (ative 0). The impliations are omputed. If the variable already has the assigned value 0, we have already tried both possible values for this variable. In this ase, the state mahine resets to init and baktraks further by transferring ontrol to the left. Finding a Solution A solution has been found when the rightmost state mahine further attempts to pass ontrol to the right. No solution exists if the leftmost state mahine attempts to baktrak by further passing ontrol to the left. 4.2 Performane Results In this setion we ompare the performane of our hardware implementation of the basi Davis-Putnam SAT algorithm to its implementation in GRASP [11]. In order to estimate the hardware performane, we use simulation to ount the exat number of hardware lok yles needed to solve eah problem and divide by lok rate to ompute the run time. We have used a VHDL model to verify design orretness on moderate examples. However, sine VHDL simulation an be slow, we have generated a C-language hardware model that is signiantly faster then general VHDL simulation. We use this for performane estimation of longrunning problems. Like a VHDL simulation, the C-language simulation is also apable of ounting the number of hardware lok yles required exatly. The number of hardware lok yles is translated into run time based on a lok rate of 1.33 MHz. This is a lok rate ahieved on a large example on an IKOS FPGA board [7] as detailed in the setion on hardware implementation issues. The GRASP runs were timed on a Sun 5 workstation with 64 MB of RAM and a 110 MHz proessor. As disussed earlier, our hardware implementation urrently requires variables be ordered statially prior to the hardware implementation. Our ordering strategy plaes earlier the variables with more appearanes in the formula. We ompared the performane for all the examples in the DIMACS SAT benhmark suite [5]. There are 240 problems in the DIMACS suite. Some of them take avery long time to solve and neither GRASP nor our C-model simulation gets

4 a result in reasonable amount of time (several hours). There are 134 instanes in whih at least one program nished. Instanes v =1 12 v =1 11 v 12=0 v 11=0 v =0 10 v 1 =1 v 2 =0 v 3 =0 v =0 1 v =1 14 v 12 =1 v =1 13 v =1 10 v = Figure 5: Searh example for basi baktraking. Speed up ratio Figure 4: Speedup ratio histogram omparing our FPGA approah to a GRASP run, both with basi baktraking. In all examples for whih the implementation of the basi Davis-Putnam algorithm ompletes in GRASP, our hardware implementation also ompletes usually in muh shorter time. Figure 4 shows a histogram in whih eah bar orresponds to a speedup range. Speedup is dened as the ratio of the GRASP run time to the hardware run time. (That is, a 10X speedup means that our approah is ten times faster than GRASP.) The height of the bar orresponds to the number of DIMACS SAT examples for whih the orresponding speedup is obtained. The histogram indiates that more than 90% of the examples have speedup greater than 20X and more than 45% of the examples have speedup greater than 100X. The results learly demonstrate that utilizing parallelism by diret logi mapping in the SAT algorithm ahieves signiant speedup even when the hardware lok is muh slower than that of the general purpose omputer. 5 FPGA Mapping: Nonhronologial Baktrak 5.1 Algorithm When the Davis-Putnam algorithm baktraks to the most reently assigned variable, its baktraking is said to be hronologial. On the other hand, when an algorithm jumps over several previously-assigned variables to a variable more than one level above the urrent variable, the baktraking is said to be nonhronologial. In order to jump diretly to a previous level, the algorithm must rst determine that no ombination of values on the skipped variables will result in a satisfying assignment. GRASP is a reent SAT implementation with nonhronologial baktraking. The GRASP work demonstrated that nonhronologial baktraking an lead to signiant redutions in run time. We desribe an algorithm to ahieve a similar goal in hardware, but with less ontrol omplexity than GRASP. GRASP maintains a data struture alled the impliation graph, from whih one derives the transitive impliations leading to the ontradition. From the ontradition, it traes bak to a set of assignments ontributing to the ontradition. It jumps to the most reently assigned variable in the set. It is diult, however, to traverse the impliation iruit in hardware. As a result, we devised the following alternative. Rather than analyzing the impliations, we take advantage of the fat that determining impliations is very fast in our hardware. When a ontradition ours for both assignments of the variable, it should baktrak. If we reset this variable to be free, the observed ontradition will disappear, but may reur when the same variable is assigned a value in the future. We want tohange the value of the variable that really ontributes to the observed ontradition. If a ontradition was deteted for both assignments to vi, with i being its level, our proedure works its way bak up the levels, one at a time. At eah level j (< i), the proedure alls the impliation routine twie, one for eah vi value, while vj has a ipped value. The variables vk between i and j (j < k < i) are left unassigned when the impliation routine is alled, i.e. both literals vk and vk are set to 0. The algorithm must baktrak to vjif a noontradition ase was found for one of the two assignments. If both ause ontradition, the variable vj an be skipped, and the proedure repeats this step for variable vj,1. This proedure requires only 2n alls to the impliation routine if the algorithm reverts bak bynlevels. Sine the proedure does not all the impliation routine an exponential number of times, and sine the impliation hardware is very fast, this analysis for nonhronologial baktraking an be expeted to be very fast also. In omparison, GRASP has the overhead of maintaining the impliation graph data struture and analyzing it when a ontradition is found, but it does not do the 2n impliations. The following simple example shows how our approah works. Suppose we have the following formula: (v1 0 + v v 13)(v1 0 +v12 0 +v13)(v v 12 +v 14)(v1 0 +v 12 +v14) 0. Assume that no assignment for variables v 2, v 11 leads to a ontradition. The basi searh tree for this formula is shown in Figure 5. In the gure, eah solid arrow represents assigning a new value and determining its impliations. It begins by assigning v 1 = 1 and goes on until v 11 = 1. Finally, v 12 =1 is tried. This leads to a ontradition sine v 13 is required to be both 0 and 1 simultaneously. Similarly, v 12 = 0 also leads to a ontradition. The normal baktrak proedure would reset v 12 to unknown and it would baktrak tov 11. The onit disappears temporarily but will appear again whenever v 12 is set. Figure 6(a) shows our version of nonhronologial baktraking. Figure 6(b) shows how GRASP diretly baktraks to v 1. The dotted arrows indiate skipping and do

5 v 11=0 v 3 =0 v 10=0 v 1 =1 v 2 =0 v 1 =0 v 1 =0 v 1 =1 v 1 =0 Instanes v 12=1 n v 12 =1 v 13=1 v 12=1 v 12 =1 v 13=1 5 (a) v 14=1 Figure 6: Searh examples for nonhronologial baktraking. (a) Algorithm in our hardware algorithm. (b) Software algorithm used in GRASP. v 14=1 (b) Speed up ratio Figure 8: Speedup ratio histogram for nonhronologial baktraking leaf 0 leaf 1 GContra/10 ative 0 previously. Although the state mahine has beome bigger, the extra states require only one more enoding bit. Sine most of the iruit is the same and sine the state mahine is not instrumental in determining the lok yle time, the yle time from the basi algorithm remains valid here. E (v +v )/01 il imp imp E /10 ir E il E il(v imp+v imp )/00 init ative 1 E /00 ir passive 1 bk 0 a bk 0 b GContra/10 passive 0 E /10 ir 5.3 Performane Results We ompare our runtime with nonhronologial baktraking to a GRASP implementation with nonhronologial baktraking. Similar to Figure 4, the results are graphed in Figure 8. Due to the improved performane, there are 149 problems that nished with either GRASP of our approah. While GRASP's more ompliated nonhronologial baktraking allows it to garner a bigger improvement from this tehnique than our hardware does, we still obtain a median speedup over GRASP of 63.5X. From the full DIMACS suite, we oer 100X or greater speedups on 63 of the examples. Figure 7: State diagram for nonhronologial baktraking mahine not inur any omputation; they simply show what values are assumed before an impliation alulation. For both methods, the searh is the same before reahing v 12. Baktraking diers, however. When baktraking at eah level, our impliation proedure is alled twie. That is, we baktrak to v 1after eetively alling the impliation proedure only 22 times, rather than 4082 attempts with the basi baktraking approah. While this simple example is mainly pedagogi, dramati speedup potential also exists in real benhmarks. For example, in the aim yes1-1 benhmark from the SAT suite, hronologial baktraking visits 606,578 partial assignments; the nonhronologial baktraking algorithm only visits 1384 partial assignments. 5.2 Hardware Organization The only modiations required to implement our nonhronologial baktraking algorithm are to the state mahine. No new global signals are added and the impliation iruit is not modied. The state mahine to perform the nonhronologial baktraking is shown in Figure 7. It has more states and transitions to reet the omplex baktraking proedure outlined 6 Implementation Issues 6.1 Envisioned Usage Depending on the problem harateristis, the ongurable omputing implementation an often oer signiant speedups over a software SAT solver. In order for the aeleration to be useful, however, it must oer performane advantages even after hardware ompile time and onguration time are onsidered. For this reason, we envision that the on- gurable hardware tehniques will mainly be used on SAT problems with very long GRASP run-times (hours or days) or in ases where GRASP aborts. In suh ases, the hardware synthesis times required will be aeptable. Furthermore, urrent ommerial CAD tools for FPGAs are quite general and therefore quite slow in this usage; it is not unommon for synthesis and plae-and-route times to exeed one hour. Sine our designs are quite regular and easy-toroute, however, ompiler tools speialized for our template design ould be muh faster, and ould thus broaden the range of problems for whih hardware aeleration is useful. Overall, we envision a system where easy SAT problems are still solved in software. Very large problems, ones that often timeout today, will invoke the hardware ompiler and ongure an FPGA board to assist in solving them. The envisioned hardware platform is a high-performane workstation with an FPGA board attahed via an exter-

6 nal onnetion or the I/O bus. Easy problems are handled by software running on the workstation itself, while longerrunning problems are handled by the FPGA board. Requirements for the FPGA board itself are partly a funtion of the hardware size of the problems being solved; this is disussed in the following subsetion. 6.2 Hardware Resoures Hardware requirements for our approah are a funtion of the size and omplexity of the formula being solved. The hardware usage is estimated in terms of CLBs of Xilinx XC4000 series FPGAs.[14]. The SAT solver's CLB requirements varies widely with the formula to be solved. Aross the DIMACS benhmarks, the median CLB requirements are Overall, relatively few (less than 30%) of these problems will t within the about 2000 CLB limit of urrent FPGA hips. However, 202 of 240 problems require fewer than CLBs and should t on fewer than ten FPGAs. Partitioning the design aross FPGAs is straightforward beause of the regular topology used. In our experiments, we have used the partitioning and pin multiplexing tehniques in the Ikos SLI logi emulation system originally developed as part of the MIT Virtual Wires eort [2, 7]. This partitioning software an multiplex several inter-hip signals to use the same physial pins, thereby irumventing the pin limitations that an often limit the CLB utilization of FPGA designs. Furthermore, the software performs this multiplexing with minimal impat on hardware yle times. We have ompiled many of the DIMACS problems for the IKOS system. Their lok rate ranges from 700KHz to 2 MHz. We use a 1.33 MHz lok rate as a typial value for performane omparison. If SAT is implemented on a diretly-onneted array, the lok rate is expeted to be 10 to 20 MHz. 7 Future Work As evidened by the organization of our paper, we began our work by implementing the basi Davis-Putnam proedure in reongurable hardware. Reent software implementations of the Davis-Putnam proedure have grown to be very sophistiated however [11]. To beat them onsistently, our implementation should math that sophistiation. We zeroed in on nonhronologial baktraking as a key requirement and have been able to implement it with a small inrease in hardware. The GRASP implementation still ontains two additional features that our implementation does not: 1. The ability to add lauses on the y plays a signiant role in GRASP's ability to solve hard problems. Variable relationships derived in the searh help prune searh tree in the future. It is hard to hange the iruit and reroute the FPGA in the middle of the algorithm. We are working on low ost ways of implementing this feature based on multiple onguration ontexts. 2. The ability tohoose the next deision variable on the y also ontributes to the eieny of the software implementations. While this is very simple to do in software, it an be very hardware intensive in reon- gurable hardware, as evidened by the Abramovii and Saab proposal [1]. In pratie, we have found that a good stati ordering of variables works quite well. If dynami ordering an provide signiant improvement, we will implement itaswell. 8 Conlusions Overall, the ontributions of this paper are two-fold. First, we provide a system design for formula-spei Boolean satisability solutions based on a ongurable hardware implementation. Our design's hardware requirements are quite modest ompared to other reent proposals. Moreover, our hardware performane results indiate that the ongurable hardware approah oers dramati improvements over even the best urrent software-based tehniques. We have observed speedups of well over 200X ompared to software SAT solutions on several of the DIMACS SAT benhmarks. The seond ontribution of this paper is muh broader. We present our SAT-solver as a ase study of a lass of inputspei ongurable hardware appliations. These appliations aggressively harness the inreasing integration levels and reongurability of urrent FPGAs by performing template-driven hardware designs for eah problem/data set being solved. Their amenability to parameterized, automated design makes it easy and fast to ompile ongurations for them. Overall, this paper alerts the hardware design ommunity to an inreasingly-important appliation style, and douments its signiant promise via a detailed ase study on formula-spei SAT-solving. Referenes [1] M. Abramovii and D. Saab. Satisability on Reongurable Hardware. In Seventh Intl. Workshop on Field Programmable Logi and Appliations, Sept [2] J. Babb, R. Tessier, and A. Agarwal. Virtual Wires: Overoming pin limitations in FPGA-based logi emulators. In Pro. IEEE Workshop on FPGA-based Custom Computing Mahines, pages 142{151, Apr [3] S. Chakradhar, V. Agrawal, and S. Rothweiler. A transitive losure algorithm for test generation. IEEE Trans. on Computer-Aided Design of Integrated Ciruits and Systems, 12(7):1015{1028, July [4] M. Davis and H. Putnam. A Computing Proedure for Quantiation Theory. Journal of the ACM, 7:201{215, [5] DIMACS. DIMACS Challenge benhmarks and UCSC benhmarks. Available at ftp://dimas.rutgers.edu/pub/hallenge/sat/benhmarks/nf. [6] P. Goel. An Impliit Enumeration Algorithm to Generate Tests for Combinational Logi Ciruits. IEEE Tran. on Computers, C30(3):215{222, Marh [7] IKOS Systems. Virtual Logi SLI Doumentation. Version 1.6. [8] T. Larrabee. Test Pattern Generation Using Boolean Satis- ability. In IEEE Trans. on Computer-Aided Design, volume 11, pages 4{15, January [9] A. Rashid, J. Leonard, and W. H. Mangione-Smith. Dynami Ciruit Generation for Solving Spei Problem Instanes of Boolean Satisability. In Proeedings IEEE Workshop on FPGA-based Custom Computing Mahines, Apr [10] J. Rose and D. Hill. Arhitetural and Physial Design Challenges for One Million Gate FPGAs and Beyond. In Pro ACM/SIGDA Fifth Intl. Symp. on Field- Programmable Gate Arrays, Feb [11] J. Silva and K. Sakallah. GRASP-A New Searh Algorithm for Satisability. In IEEE ACM Intl. Conf. on CAD-96, pages 220{227, Nov [12] P. Stephan, R. Brayton, and A. Sangiovanni-Vinentelli. Combinational Test Generation Using Satisability. Department of Eletrial Engineering and Computer Sienes, University of California at Berkeley, UCB/ERL Memo M92/112. [13] T. Suyama, M. Yokoo, and H. Sawada. Solving Satisability Problems on FPGAs. In 6th Int'l Workshop on Field- Programmable Logi and Appliations, Sept [14] Xilinx Corp. The Programmable Logi Data Book. Xilinx Corp. San Jose, CA, 1996.