Menu. X + /X=1 and XY+X /Y = X(Y + /Y) = X

Size: px
Start display at page:

Download "Menu. X + /X=1 and XY+X /Y = X(Y + /Y) = X"

Transcription

1 Menu K-Maps and Boolean Algera >Don t ares >5 Variale Look into my... 1 Karnaugh Maps - Boolean Algera We have disovered that simplifiation/minimization is an art. If you see it, GREAT! Else, work at it, work at it,, A method to exhaustively minimize is due to Quine/MCluskey and is programmale. As the numer of variales inrease, it gets quite tedious and is not appropriate for our purposes Reminder X + /X=1 and XY+X /Y = X(Y + /Y) = X Two terms whih differ in only one literal an e minimized/ redued y one literal. A K-Map is a graphial aid (a pattern reognition tehnique) for humans to implement the aove two equations. 2 1

2 K-Maps Consider the following arrangement for f. A BC Positions of Truth Tale Rows in K-Map A BC R 0 R 4 01 R 1 R 5 11 R 3 R 7 10 R 2 R f SOP = /A /B /C + /A /B C + /A B C + A /B C + A B /C But the minterms of funtion f are now rearranged so they differ in 1 literal. Look at row 1 (BC=01) of the K-map. The terms of funtion f differ only in one literal, e.g., f ontains /A /B C + A /B C, the seond and fourth terms of the equation, = (/A + A) /B C = /B C. In fat, any two adjaent rows or olumns of 1 s differ in one literal, and thus, an e simplified. 3 K-Maps A BC R 0 R 4 f SOP = /A /B /C + /A /B C + /A B C + A /B C + A B /C Now, onsider the following arrangement for f. A BC m 0 But the minterms of f are now arranged so they differ in 1 literal. m 5 Look at the seond row of the K-Map. The terms of f differ only in one literal, e.g., f ontains A B C + AB C = (/A + A)B C = B C. In fat, if any of two rows or olumns of 1 s differ in one literal, they an e simplified. m 6 01 R 1 R 5 11 R 3 R 7 10 R 2 R 6 ABC f

3 Definitions K-Maps Impliants: terms in a K-Map that are 1 iff the funtion is 1. Prime impliant: a term in a K-Map that is as ig as it an e. If we irle in the K-Map those impliants that are logially and spatially adjaent and if we make sure that all the 1 s of the funtion are overed, we an synthesize the funtion diretly. When a 1 is overed y one and only one (prime) impliant, it is alled an essential (prime) impliant. Goal: > Step 1. Cirle all the (prime) impliants > Step 2. Selet a suset that overs the funtion starting with the prime impliants 5 K-Map: MSOP Example <Example 1> Simplify a given funtion g in SOP form. g = /a / + /a / + /a + a + a / Prime Impliant (eause of m 5 ) (a + /a) / = / Prime Impliant (a + /a) = (eause of m 6 ) g = + / + 6 3

4 K-Map: MSOP Example <Example 1> Simplify a given funtion g in SOP form. g = /a / + /a / + /a + a + a / /a /( + ) = /a / g MSOP1 = + / + /a / = /a / + / + /a ( + /) = /a g MSOP2 = + / + /a = /a + / + 7 Another way to look at it K-Map: Another MSOP Viewpoint g = /a / + /a / + /a + a + a / /a / g MSOP1 = + / + /a / = /a / + / + g MSOP2 = + / + /a = /a + / + /a a / / 8 4

5 K-Map: MPOS Example <Example 2> Will it work for POS if we use 0 s & maxterms? NOTE: Reversed laels from SOP g MPOS /a + + / + = (/a + + )(/ + ) a /a / 9 K-Map: MSOP vs MPOS Let s ompare MSOP with MPOS. g MSOP = /a + / + g MPOS Q: Whih is heaper? Ans: Depends on ost funtion; proaly MPOS Q: Why? Ans: Beause MPOS requires less # of gates and inputs. /a g MSOP requires 4 gates and 9 inputs / g MPOS requires 3 gates and 7 inputs / /a = (/a + + )(/ + ) 10 5

6 K-Map Heuristi Heuristi: (not a guarantee) We note that the POS was minimum (ompared to the SOP) perhaps eause we had only three 0 s vs five 1 s. In general, we synthesize the funtion ased on the least numer of either 1 s or 0 s. But to e sure we must do oth and hek! Oservation: We got 2-level logi with these, i.e., the maximum delay is the delay of two gates. It is sometimes possile to otain a heaper (in gates) ost funtion using more than 2-level logi. If your appliation an tolerate larger delays, this is OK. /a / NOTE: 2-Level logi is the / fastest logi possile and K-Maps give it to you. /a 11 Examples of 4-input K-Map Example: Groups of 2 / /d prime a / /d prime a /d prime a / prime g 1MSOP = a / + a / /d + a /d + / /d 12 6

7 4-input K-Map Example: Groups of 2 and Redundany Examples of (ontinued) Redundant! What is eqn? a prime /a d prime /a prime a d prime g 2MSOP = /a + /a d + a + a d 13 Examples of (ontinued) 4-input K-Map Example: Groups of 4 /a prime d prime g 3MSOP = /a + d 14 7

8 Examples of (ontinued) 4-input K-Map Example: More Groups of 4 / d prime /d prime g 4MSOP = / d + /d = xor d / + /d prime + d prime g 4MPOS = (/ + /d) ( + d) = xor d Same funtion! 15 Don t Cares Don t Cares: Suppose we have the following system a C i f( ) d What if some ominations of the inputs a,,,d are never produed y C i? >Q: What should we write in the Truth Tale, 0 or 1? >A: We write a don t are (X). We are free to hoose X to e 0 or 1 at our onveniene. However, one you pik a partiular value for X, it must e the same throughout the design! 16 8

9 Examples of with don t ares Don t Care Examples Is g 1MSOP = g 2MPOS? Why or why not? 17 5-variale K-Maps Five Variale : Break the funtion into two 4-variale K- maps, e.g., for a funtion f (a,,,d,e) of 5 variales, pik one of the variales, say e, and do a K-map when e=0 and when e=1. Then f = e f e=0 + ef e=1. Can simplify to a d Not in lexial f = e f e=0 +ef e=1 = e ( d+d ) + order e(a +a d+d ) = a d e + d + e ( d) + e(a ) 18 9

10 5-variale K-Maps Or use: > f = f e&e + e f e=0 (not f e=1 )+ ef e=1 (not f e=0 ), i.e., > f = (shared overs) + e (overs in f e=0 only) + e (overs in f e=1 only) f = a d + d + e ( d) + e(a ) = f e&e + e /f e=1 f e=0 + e /f e=0 f e=1 Not in lexial order 19 The End! 20 10

Menu. Algebraic Simplification - Boolean Algebra EEL3701 EEL3701. MSOP, MPOS, Simplification

Menu. Algebraic Simplification - Boolean Algebra EEL3701 EEL3701. MSOP, MPOS, Simplification Menu Minterms & Maxterms SOP & POS MSOP & MPOS Simplification using the theorems/laws/axioms Look into my... 1 Definitions (Review) Algebraic Simplification - Boolean Algebra Minterms (written as m i ):

More information

Definitions Homework. Quine McCluskey Optimal solutions are possible for some large functions Espresso heuristic. Definitions Homework

Definitions Homework. Quine McCluskey Optimal solutions are possible for some large functions Espresso heuristic. Definitions Homework EECS 33 There be Dragons here http://ziyang.ees.northwestern.edu/ees33/ Teaher: Offie: Email: Phone: L477 Teh dikrp@northwestern.edu 847 467 2298 Today s material might at first appear diffiult Perhaps

More information

Experiment 4 Boolean Functions Implementation

Experiment 4 Boolean Functions Implementation Experiment 4 Boolean Functions Implementation Introduction: Generally you will find that the basic logic functions AND, OR, NAND, NOR, and NOT are not sufficient to implement complex digital logic functions.

More information

DKT 122/3 DIGITAL SYSTEM 1

DKT 122/3 DIGITAL SYSTEM 1 Company LOGO DKT 122/3 DIGITAL SYSTEM 1 BOOLEAN ALGEBRA (PART 2) Boolean Algebra Contents Boolean Operations & Expression Laws & Rules of Boolean algebra DeMorgan s Theorems Boolean analysis of logic circuits

More information

Karnaugh Map (K-Map) Karnaugh Map. Karnaugh Map Examples. Ch. 2.4 Ch. 2.5 Simplification using K-map

Karnaugh Map (K-Map) Karnaugh Map. Karnaugh Map Examples. Ch. 2.4 Ch. 2.5 Simplification using K-map Karnaugh Map (K-Map) Ch. 2.4 Ch. 2.5 Simplification using K-map A graphical map method to simplify Boolean function up to 6 variables A diagram made up of squares Each square represents one minterm (or

More information

Simplification of Boolean Functions

Simplification of Boolean Functions COM111 Introduction to Computer Engineering (Fall 2006-2007) NOTES 5 -- page 1 of 5 Introduction Simplification of Boolean Functions You already know one method for simplifying Boolean expressions: Boolean

More information

Combinational Logic Circuits

Combinational Logic Circuits Chapter 3 Combinational Logic Circuits 12 Hours 24 Marks 3.1 Standard representation for logical functions Boolean expressions / logic expressions / logical functions are expressed in terms of logical

More information

LSN 4 Boolean Algebra & Logic Simplification. ECT 224 Digital Computer Fundamentals. Department of Engineering Technology

LSN 4 Boolean Algebra & Logic Simplification. ECT 224 Digital Computer Fundamentals. Department of Engineering Technology LSN 4 Boolean Algebra & Logic Simplification Department of Engineering Technology LSN 4 Key Terms Variable: a symbol used to represent a logic quantity Compliment: the inverse of a variable Literal: a

More information

Experiment 3: Logic Simplification

Experiment 3: Logic Simplification Module: Logic Design Name:... University no:.. Group no:. Lab Partner Name: Mr. Mohamed El-Saied Experiment : Logic Simplification Objective: How to implement and verify the operation of the logical functions

More information

Department of Electrical and Computer Engineering University of Wisconsin Madison. Fall

Department of Electrical and Computer Engineering University of Wisconsin Madison. Fall Department of Eletrial and Computer Engineering University of Wisonsin Madison ECE 553: Testing and Testable Design of Digital Systems Fall 2014-2015 Assignment #2 Date Tuesday, September 25, 2014 Due

More information

CHAPTER-2 STRUCTURE OF BOOLEAN FUNCTION USING GATES, K-Map and Quine-McCluskey

CHAPTER-2 STRUCTURE OF BOOLEAN FUNCTION USING GATES, K-Map and Quine-McCluskey CHAPTER-2 STRUCTURE OF BOOLEAN FUNCTION USING GATES, K-Map and Quine-McCluskey 2. Introduction Logic gates are connected together to produce a specified output for certain specified combinations of input

More information

Binary Decision Diagrams (BDDs) Pingqiang Zhou ShanghaiTech University

Binary Decision Diagrams (BDDs) Pingqiang Zhou ShanghaiTech University Binary Decision Diagrams (BDDs) Pingqiang Zhou ShanghaiTech University Computational Boolean Algera Representations Applying unate recursive paradigm (URP) in solving tautology is a great warm up example.

More information

Digital Logic Lecture 7 Gate Level Minimization

Digital Logic Lecture 7 Gate Level Minimization Digital Logic Lecture 7 Gate Level Minimization By Ghada Al-Mashaqbeh The Hashemite University Computer Engineering Department Outline Introduction. K-map principles. Simplification using K-maps. Don t-care

More information

Chapter 6. Logic Design Optimization Chapter 6

Chapter 6. Logic Design Optimization Chapter 6 Chapter 6 Logic Design Optimization Chapter 6 Optimization The second part of our design process. Optimization criteria: Performance Size Power Two-level Optimization Manipulating a function until it is

More information

Chapter 2 Combinational Logic Circuits

Chapter 2 Combinational Logic Circuits Logic and Computer Design Fundamentals Chapter 2 Combinational Logic Circuits Part 2 Circuit Optimization Overview Part Gate Circuits and Boolean Equations Binary Logic and Gates Boolean Algebra Standard

More information

DIGITAL CIRCUIT LOGIC UNIT 5: KARNAUGH MAPS (K-MAPS)

DIGITAL CIRCUIT LOGIC UNIT 5: KARNAUGH MAPS (K-MAPS) DIGITAL CIRCUIT LOGIC UNIT 5: KARNAUGH MAPS (K-MAPS) 1 Learning Objectives 1. Given a function (completely or incompletely specified) of three to five variables, plot it on a Karnaugh map. The function

More information

This fact makes it difficult to evaluate the cost function to be minimized

This fact makes it difficult to evaluate the cost function to be minimized RSOURC LLOCTION N SSINMNT In the resoure alloation step the amount of resoures required to exeute the different types of proesses is determined. We will refer to the time interval during whih a proess

More information

Approximate logic synthesis for error tolerant applications

Approximate logic synthesis for error tolerant applications Approximate logi synthesis for error tolerant appliations Doohul Shin and Sandeep K. Gupta Eletrial Engineering Department, University of Southern California, Los Angeles, CA 989 {doohuls, sandeep}@us.edu

More information

Chapter 3 Simplification of Boolean functions

Chapter 3 Simplification of Boolean functions 3.1 Introduction Chapter 3 Simplification of Boolean functions In this chapter, we are going to discuss several methods for simplifying the Boolean function. What is the need for simplifying the Boolean

More information

2.6 BOOLEAN FUNCTIONS

2.6 BOOLEAN FUNCTIONS 2.6 BOOLEAN FUNCTIONS Binary variables have two values, either 0 or 1. A Boolean function is an expression formed with binary variables, the two binary operators AND and OR, one unary operator NOT, parentheses

More information

Outcomes. Unit 9. Logic Function Synthesis KARNAUGH MAPS. Implementing Combinational Functions with Karnaugh Maps

Outcomes. Unit 9. Logic Function Synthesis KARNAUGH MAPS. Implementing Combinational Functions with Karnaugh Maps .. Outcomes Unit I can use Karnaugh maps to synthesize combinational functions with several outputs I can determine the appropriate size and contents of a memory to implement any logic function (i.e. truth

More information

CS470: Computer Architecture. AMD Quad Core

CS470: Computer Architecture. AMD Quad Core CS470: Computer Architecture Yashwant K. Malaiya, Professor malaiya@cs.colostate.edu AMD Quad Core 1 Architecture Layers Building blocks Gates, flip-flops Functional bocks: Combinational, Sequential Instruction

More information

ENGINEERS ACADEMY. 7. Given Boolean theorem. (a) A B A C B C A B A C. (b) AB AC BC AB BC. (c) AB AC BC A B A C B C.

ENGINEERS ACADEMY. 7. Given Boolean theorem. (a) A B A C B C A B A C. (b) AB AC BC AB BC. (c) AB AC BC A B A C B C. Digital Electronics Boolean Function QUESTION BANK. The Boolean equation Y = C + C + C can be simplified to (a) (c) A (B + C) (b) AC (d) C. The Boolean equation Y = (A + B) (A + B) can be simplified to

More information

Bawar Abid Abdalla. Assistant Lecturer Software Engineering Department Koya University

Bawar Abid Abdalla. Assistant Lecturer Software Engineering Department Koya University Logic Design First Stage Lecture No.6 Boolean Algebra Bawar Abid Abdalla Assistant Lecturer Software Engineering Department Koya University Outlines Boolean Operations Laws of Boolean Algebra Rules of

More information

CMPE223/CMSE222 Digital Logic

CMPE223/CMSE222 Digital Logic CMPE223/CMSE222 Digital Logic Optimized Implementation of Logic Functions: Strategy for Minimization, Minimum Product-of-Sums Forms, Incompletely Specified Functions Terminology For a given term, each

More information

Philadelphia University Faculty of Information Technology Department of Computer Science. Computer Logic Design. By Dareen Hamoudeh.

Philadelphia University Faculty of Information Technology Department of Computer Science. Computer Logic Design. By Dareen Hamoudeh. Philadelphia University Faculty of Information Technology Department of Computer Science Computer Logic Design By Dareen Hamoudeh Dareen Hamoudeh 1 Canonical Forms (Standard Forms of Expression) Minterms

More information

Chapter 2 Combinational

Chapter 2 Combinational Computer Engineering 1 (ECE290) Chapter 2 Combinational Logic Circuits Part 2 Circuit Optimization HOANG Trang 2008 Pearson Education, Inc. Overview Part 1 Gate Circuits and Boolean Equations Binary Logic

More information

ECE380 Digital Logic

ECE380 Digital Logic ECE38 Digital Logic Optimized Implementation of Logic Functions: Strategy for Minimization, Minimum Product-of-Sums Forms, Incompletely Specified Functions Dr. D. J. Jackson Lecture 8- Terminology For

More information

IT 201 Digital System Design Module II Notes

IT 201 Digital System Design Module II Notes IT 201 Digital System Design Module II Notes BOOLEAN OPERATIONS AND EXPRESSIONS Variable, complement, and literal are terms used in Boolean algebra. A variable is a symbol used to represent a logical quantity.

More information

Standard Forms of Expression. Minterms and Maxterms

Standard Forms of Expression. Minterms and Maxterms Standard Forms of Expression Minterms and Maxterms Standard forms of expressions We can write expressions in many ways, but some ways are more useful than others A sum of products (SOP) expression contains:

More information

1 Disjoint-set data structure.

1 Disjoint-set data structure. CS 124 Setion #4 Union-Fin, Greey Algorithms 2/20/17 1 Disjoint-set ata struture. 1.1 Operations Disjoint-set ata struture enale us to effiiently perform operations suh as plaing elements into sets, querying

More information

ece5745-pla-notes.txt

ece5745-pla-notes.txt ece5745-pla-notes.txt ========================================================================== Follow up on PAL/PROM/PLA Activity ==========================================================================

More information

Chapter 3. Gate-Level Minimization. Outlines

Chapter 3. Gate-Level Minimization. Outlines Chapter 3 Gate-Level Minimization Introduction The Map Method Four-Variable Map Five-Variable Map Outlines Product of Sums Simplification Don t-care Conditions NAND and NOR Implementation Other Two-Level

More information

Chapter 2. Boolean Expressions:

Chapter 2. Boolean Expressions: Chapter 2 Boolean Expressions: A Boolean expression or a function is an expression which consists of binary variables joined by the Boolean connectives AND and OR along with NOT operation. Any Boolean

More information

A B AB CD Objectives:

A B AB CD Objectives: Objectives:. Four variables maps. 2. Simplification using prime implicants. 3. "on t care" conditions. 4. Summary.. Four variables Karnaugh maps Minterms A A m m m3 m2 A B C m4 C A B C m2 m8 C C m5 C m3

More information

QUESTION BANK FOR TEST

QUESTION BANK FOR TEST CSCI 2121 Computer Organization and Assembly Language PRACTICE QUESTION BANK FOR TEST 1 Note: This represents a sample set. Please study all the topics from the lecture notes. Question 1. Multiple Choice

More information

Final Examination (Open Katz, asynchronous & test notes only, Calculators OK, 3 hours)

Final Examination (Open Katz, asynchronous & test notes only, Calculators OK, 3 hours) Your Name: UNIVERSITY OF CALIFORNIA AT BERKELEY BERKELEY DAVIS IRVINE LOS ANGELES RIVERSIDE SAN DIEGO SAN FRANCISCO Department of Electrical Engineering and Computer Sciences SANTA BARBARA SANTA CRUZ CS

More information

Module -7. Karnaugh Maps

Module -7. Karnaugh Maps 1 Module -7 Karnaugh Maps 1. Introduction 2. Canonical and Standard forms 2.1 Minterms 2.2 Maxterms 2.3 Canonical Sum of Product or Sum-of-Minterms (SOM) 2.4 Canonical product of sum or Product-of-Maxterms(POM)

More information

1. Mark the correct statement(s)

1. Mark the correct statement(s) 1. Mark the correct statement(s) 1.1 A theorem in Boolean algebra: a) Can easily be proved by e.g. logic induction b) Is a logical statement that is assumed to be true, c) Can be contradicted by another

More information

Gate-Level Minimization. BME208 Logic Circuits Yalçın İŞLER

Gate-Level Minimization. BME208 Logic Circuits Yalçın İŞLER Gate-Level Minimization BME28 Logic Circuits Yalçın İŞLER islerya@yahoo.com http://me.islerya.com Complexity of Digital Circuits Directly related to the complexity of the algebraic expression we use to

More information

Gate Level Minimization Map Method

Gate Level Minimization Map Method Gate Level Minimization Map Method Complexity of hardware implementation is directly related to the complexity of the algebraic expression Truth table representation of a function is unique Algebraically

More information

SEE1223: Digital Electronics

SEE1223: Digital Electronics SEE223: Digital Electronics 3 Combinational Logic Design Zulkifil Md Yusof Dept. of Microelectronics and Computer Engineering The aculty of Electrical Engineering Universiti Teknologi Malaysia Karnaugh

More information

Points Addressed in this Lecture. Standard form of Boolean Expressions. Lecture 4: Logic Simplication & Karnaugh Map

Points Addressed in this Lecture. Standard form of Boolean Expressions. Lecture 4: Logic Simplication & Karnaugh Map Points Addressed in this Lecture Lecture 4: Logic Simplication & Karnaugh Map Professor Peter Cheung Department of EEE, Imperial College London Standard form of Boolean Expressions Sum-of-Products (SOP),

More information

To write Boolean functions in their standard Min and Max terms format. To simplify Boolean expressions using Karnaugh Map.

To write Boolean functions in their standard Min and Max terms format. To simplify Boolean expressions using Karnaugh Map. 3.1 Objectives To write Boolean functions in their standard Min and Max terms format. To simplify Boolean expressions using. 3.2 Sum of Products & Product of Sums Any Boolean expression can be simplified

More information

Combinational Logic Circuits

Combinational Logic Circuits Chapter 2 Combinational Logic Circuits J.J. Shann (Slightly trimmed by C.P. Chung) Chapter Overview 2-1 Binary Logic and Gates 2-2 Boolean Algebra 2-3 Standard Forms 2-4 Two-Level Circuit Optimization

More information

CprE 281: Digital Logic

CprE 281: Digital Logic CprE 28: Digital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ Minimization CprE 28: Digital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev Administrative

More information

ENGIN 112. Intro to Electrical and Computer Engineering

ENGIN 112. Intro to Electrical and Computer Engineering ENIN 2 Intro to Electrical and Computer Engineering Lecture 6 More Boolean Algebra ENIN2 L6: More Boolean Algebra September 5, 23 A B Overview Epressing Boolean functions Relationships between algebraic

More information

Combinational Logic & Circuits

Combinational Logic & Circuits Week-I Combinational Logic & Circuits Spring' 232 - Logic Design Page Overview Binary logic operations and gates Switching algebra Algebraic Minimization Standard forms Karnaugh Map Minimization Other

More information

Chapter 2: Combinational Systems

Chapter 2: Combinational Systems Uchechukwu Ofoegbu Chapter 2: Combinational Systems Temple University Adapted from Alan Marcovitz s Introduction to Logic and Computer Design Riddle Four switches can be turned on or off. One is the switch

More information

Code No: R Set No. 1

Code No: R Set No. 1 Code No: R059210504 Set No. 1 II B.Tech I Semester Supplementary Examinations, February 2007 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science

More information

-z c = c T - c T B B-1 A 1 - c T B B-1 b. x B B -1 A 0 B -1 b. (a) (b) Figure 1. Simplex Tableau in Matrix Form

-z c = c T - c T B B-1 A 1 - c T B B-1 b. x B B -1 A 0 B -1 b. (a) (b) Figure 1. Simplex Tableau in Matrix Form 3. he Revised Simple Method he LP min, s.t. A = b ( ),, an be represented by Figure (a) below. At any Simple step, with known and -, the Simple tableau an be represented by Figure (b) below. he minimum

More information

Karnaugh Maps. Kiril Solovey. Tel-Aviv University, Israel. April 8, Kiril Solovey (TAU) Karnaugh Maps April 8, / 22

Karnaugh Maps. Kiril Solovey. Tel-Aviv University, Israel. April 8, Kiril Solovey (TAU) Karnaugh Maps April 8, / 22 Karnaugh Maps Kiril Solovey Tel-Aviv University, Israel April 8, 2013 Kiril Solovey (TAU) Karnaugh Maps April 8, 2013 1 / 22 Reminder: Canonical Representation Sum of Products Function described for the

More information

S1 Teknik Telekomunikasi Fakultas Teknik Elektro FEH2H3 2016/2017

S1 Teknik Telekomunikasi Fakultas Teknik Elektro FEH2H3 2016/2017 S1 Teknik Telekomunikasi Fakultas Teknik Elektro FEH2H3 2016/2017 Karnaugh Map Karnaugh maps Last time we saw applications of Boolean logic to circuit design. The basic Boolean operations are AND, OR and

More information

2008 The McGraw-Hill Companies, Inc. All rights reserved.

2008 The McGraw-Hill Companies, Inc. All rights reserved. 28 The McGraw-Hill Companies, Inc. All rights reserved. 28 The McGraw-Hill Companies, Inc. All rights reserved. All or Nothing Gate Boolean Expression: A B = Y Truth Table (ee next slide) or AB = Y 28

More information

Combinational Logic Circuits Part III -Theoretical Foundations

Combinational Logic Circuits Part III -Theoretical Foundations Combinational Logic Circuits Part III -Theoretical Foundations Overview Simplifying Boolean Functions Algebraic Manipulation Karnaugh Map Manipulation (simplifying functions of 2, 3, 4 variables) Systematic

More information

Specifying logic functions

Specifying logic functions CSE4: Components and Design Techniques for Digital Systems Specifying logic functions Instructor: Mohsen Imani Slides from: Prof.Tajana Simunic and Dr.Pietro Mercati We have seen various concepts: Last

More information

University of Technology

University of Technology University of Technology Lecturer: Dr. Sinan Majid Course Title: microprocessors 4 th year Lecture 5 & 6 Minimization with Karnaugh Maps Karnaugh maps lternate way of representing oolean function ll rows

More information

Get Free notes at Module-I One s Complement: Complement all the bits.i.e. makes all 1s as 0s and all 0s as 1s Two s Complement: One s complement+1 SIGNED BINARY NUMBERS Positive integers (including zero)

More information

Unit-IV Boolean Algebra

Unit-IV Boolean Algebra Unit-IV Boolean Algebra Boolean Algebra Chapter: 08 Truth table: Truth table is a table, which represents all the possible values of logical variables/statements along with all the possible results of

More information

Designing Computer Systems Boolean Algebra

Designing Computer Systems Boolean Algebra Designing Computer Systems Boolean Algebra 08:34:45 PM 4 June 2013 BA-1 Scott & Linda Wills Designing Computer Systems Boolean Algebra Programmable computers can exhibit amazing complexity and generality.

More information

EEE130 Digital Electronics I Lecture #4_1

EEE130 Digital Electronics I Lecture #4_1 EEE130 Digital Electronics I Lecture #4_1 - Boolean Algebra and Logic Simplification - By Dr. Shahrel A. Suandi 4-6 Standard Forms of Boolean Expressions There are two standard forms: Sum-of-products form

More information

Gate-Level Minimization

Gate-Level Minimization Gate-Level Minimization ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2011 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Outlines The Map Method

More information

Slide Set 5. for ENEL 353 Fall Steve Norman, PhD, PEng. Electrical & Computer Engineering Schulich School of Engineering University of Calgary

Slide Set 5. for ENEL 353 Fall Steve Norman, PhD, PEng. Electrical & Computer Engineering Schulich School of Engineering University of Calgary Slide Set 5 for ENEL 353 Fall 207 Steve Norman, PhD, PEng Electrical & Computer Engineering Schulich School of Engineering University of Calgary Fall Term, 207 SN s ENEL 353 Fall 207 Slide Set 5 slide

More information

Gate Level Minimization

Gate Level Minimization Gate Level Minimization By Dr. M. Hebaishy Digital Logic Design Ch- Simplifying Boolean Equations Example : Y = AB + AB Example 2: = B (A + A) T8 = B () T5 = B T Y = A(AB + ABC) = A (AB ( + C ) ) T8 =

More information

CSCI 220: Computer Architecture I Instructor: Pranava K. Jha. Simplification of Boolean Functions using a Karnaugh Map

CSCI 220: Computer Architecture I Instructor: Pranava K. Jha. Simplification of Boolean Functions using a Karnaugh Map CSCI 22: Computer Architecture I Instructor: Pranava K. Jha Simplification of Boolean Functions using a Karnaugh Map Q.. Plot the following Boolean function on a Karnaugh map: f(a, b, c, d) = m(, 2, 4,

More information

Review: Standard forms of expressions

Review: Standard forms of expressions Karnaugh maps Last time we saw applications of Boolean logic to circuit design. The basic Boolean operations are AND, OR and NOT. These operations can be combined to form complex expressions, which can

More information

Date Performed: Marks Obtained: /10. Group Members (ID):. Experiment # 04. Boolean Expression Simplification and Implementation

Date Performed: Marks Obtained: /10. Group Members (ID):. Experiment # 04. Boolean Expression Simplification and Implementation Name: Instructor: Engr. Date Performed: Marks Obtained: /10 Group Members (ID):. Checked By: Date: Experiment # 04 Boolean Expression Simplification and Implementation OBJECTIVES: To understand the utilization

More information

Switching Circuits & Logic Design

Switching Circuits & Logic Design Switching Circuits & Logic Design Jie-Hong Roland Jiang 江介宏 Department of Electrical Engineering National Taiwan University Fall 23 5 Karnaugh Maps K-map Walks and Gray Codes http://asicdigitaldesign.wordpress.com/28/9/26/k-maps-walks-and-gray-codes/

More information

Analysis of input and output configurations for use in four-valued CCD programmable logic arrays

Analysis of input and output configurations for use in four-valued CCD programmable logic arrays nalysis of input and output onfigurations for use in four-valued D programmable logi arrays J.T. utler H.G. Kerkhoff ndexing terms: Logi, iruit theory and design, harge-oupled devies bstrat: s in binary,

More information

UNIT II. Circuit minimization

UNIT II. Circuit minimization UNIT II Circuit minimization The complexity of the digital logic gates that implement a Boolean function is directly related to the complexity of the algebraic expression from which the function is implemented.

More information

CS2100 Computer Organisation Tutorial #8: MSI Components Answers to Selected Questions

CS2100 Computer Organisation Tutorial #8: MSI Components Answers to Selected Questions C Computer Organisation Tutorial #8: MI Components Answers to elete Questions. Realize the following funtion with (a) an 8: multiplexer, an (b) a 4: multiplexer using the first input variables as the seletor

More information

Digital Circuits ECS 371

Digital Circuits ECS 371 Digital Circuits ECS 37 Dr. Prapun Suksompong prapun@siit.tu.ac.th Lecture 7 Office Hours: KD 36-7 Monday 9:-:3, :3-3:3 Tuesday :3-:3 Announcement HW2 posted on the course web site Chapter 4: Write down

More information

Improved Circuit-to-CNF Transformation for SAT-based ATPG

Improved Circuit-to-CNF Transformation for SAT-based ATPG Improved Ciruit-to-CNF Transformation for SAT-based ATPG Daniel Tille 1 René Krenz-Bååth 2 Juergen Shloeffel 2 Rolf Drehsler 1 1 Institute of Computer Siene, University of Bremen, 28359 Bremen, Germany

More information

Graduate Institute of Electronics Engineering, NTU. CH5 Karnaugh Maps. Lecturer: 吳安宇教授 Date:2006/10/20 ACCESS IC LAB

Graduate Institute of Electronics Engineering, NTU. CH5 Karnaugh Maps. Lecturer: 吳安宇教授 Date:2006/10/20 ACCESS IC LAB CH5 Karnaugh Maps Lecturer: 吳安宇教授 Date:2006/0/20 CCESS IC L Problems in lgebraic Simplification The procedures are difficult to apply in a systematic way. It is difficult to tell when you have arrived

More information

Gate-Level Minimization

Gate-Level Minimization MEC520 디지털공학 Gate-Level Minimization Jee-Hwan Ryu School of Mechanical Engineering Gate-Level Minimization-The Map Method Truth table is unique Many different algebraic expression Boolean expressions may

More information

Chapter 2: Introduction to Maple V

Chapter 2: Introduction to Maple V Chapter 2: Introdution to Maple V 2-1 Working with Maple Worksheets Try It! (p. 15) Start a Maple session with an empty worksheet. The name of the worksheet should be Untitled (1). Use one of the standard

More information

4 KARNAUGH MAP MINIMIZATION

4 KARNAUGH MAP MINIMIZATION 4 KARNAUGH MAP MINIMIZATION A Karnaugh map provides a systematic method for simplifying Boolean expressions and, if properly used, will produce the simplest SOP or POS expression possible, known as the

More information

CS8803: Advanced Digital Design for Embedded Hardware

CS8803: Advanced Digital Design for Embedded Hardware CS883: Advanced Digital Design for Embedded Hardware Lecture 2: Boolean Algebra, Gate Network, and Combinational Blocks Instructor: Sung Kyu Lim (limsk@ece.gatech.edu) Website: http://users.ece.gatech.edu/limsk/course/cs883

More information

Chapter 2 Combinational Logic Circuits

Chapter 2 Combinational Logic Circuits Logic and Computer Design Fundamentals Chapter 2 Combinational Logic Circuits Part 2 Circuit Optimization Charles Kime & Thomas Kaminski 2008 Pearson Education, Inc. (Hyperlinks are active in View Show

More information

Digital Design. Chapter 4. Principles Of. Simplification of Boolean Functions

Digital Design. Chapter 4. Principles Of. Simplification of Boolean Functions Principles Of Digital Design Chapter 4 Simplification of Boolean Functions Karnaugh Maps Don t Care Conditions Technology Mapping Optimization, Conversions, Decomposing, Retiming Boolean Cubes for n =,

More information

Path Sharing and Predicate Evaluation for High-Performance XML Filtering*

Path Sharing and Predicate Evaluation for High-Performance XML Filtering* Path Sharing and Prediate Evaluation for High-Performane XML Filtering Yanlei Diao, Mihael J. Franklin, Hao Zhang, Peter Fisher EECS, University of California, Berkeley {diaoyl, franklin, nhz, fisherp}@s.erkeley.edu

More information

Code No: R Set No. 1

Code No: R Set No. 1 Code No: R059210504 Set No. 1 II B.Tech I Semester Regular Examinations, November 2006 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science & Systems

More information

Lecture 4: Implementation AND, OR, NOT Gates and Complement

Lecture 4: Implementation AND, OR, NOT Gates and Complement EE210: Switching Systems Lecture 4: Implementation AND, OR, NOT Gates and Complement Prof. YingLi Tian Feb. 13, 2018 Department of Electrical Engineering The City College of New York The City University

More information

POWR IP PZ1/17

POWR IP PZ1/17 Silesian University of Technology as Centre of Modern Education Based on Research and Innovations POWR.03.05.00-IP.08-00-PZ1/17 Project co-financed by the European Union under the European Social Fund

More information

Pipelined Multipliers for Reconfigurable Hardware

Pipelined Multipliers for Reconfigurable Hardware Pipelined Multipliers for Reonfigurable Hardware Mithell J. Myjak and José G. Delgado-Frias Shool of Eletrial Engineering and Computer Siene, Washington State University Pullman, WA 99164-2752 USA {mmyjak,

More information

Definitions. 03 Logic networks Boolean algebra. Boolean set: B 0,

Definitions. 03 Logic networks Boolean algebra. Boolean set: B 0, 3. Boolean algebra 3 Logic networks 3. Boolean algebra Definitions Boolean functions Properties Canonical forms Synthesis and minimization alessandro bogliolo isti information science and technology institute

More information

Computer Organization

Computer Organization Computer Organization (Logic circuits design and minimization) KR Chowdhary Professor & Head Email: kr.chowdhary@gmail.com webpage: krchowdhary.com Department of Computer Science and Engineering MBM Engineering

More information

Austin Herring Recitation 002 ECE 200 Project December 4, 2013

Austin Herring Recitation 002 ECE 200 Project December 4, 2013 1. Fastest Circuit a. How Design Was Obtained The first step of creating the design was to derive the expressions for S and C out from the given truth tables. This was done using Karnaugh maps. The Karnaugh

More information

8 : Learning Fully Observed Undirected Graphical Models

8 : Learning Fully Observed Undirected Graphical Models 10-708: Probabilisti Graphial Models 10-708, Spring 2018 8 : Learning Fully Observed Undireted Graphial Models Leturer: Kayhan Batmanghelih Sribes: Chenghui Zhou, Cheng Ran (Harvey) Zhang When learning

More information

Gate-Level Minimization

Gate-Level Minimization Gate-Level Minimization ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2017 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Outlines The Map Method

More information

UNIT-4 BOOLEAN LOGIC. NOT Operator Operates on single variable. It gives the complement value of variable.

UNIT-4 BOOLEAN LOGIC. NOT Operator Operates on single variable. It gives the complement value of variable. UNIT-4 BOOLEAN LOGIC Boolean algebra is an algebra that deals with Boolean values((true and FALSE). Everyday we have to make logic decisions: Should I carry the book or not?, Should I watch TV or not?

More information

Combinational Circuits Digital Logic (Materials taken primarily from:

Combinational Circuits Digital Logic (Materials taken primarily from: Combinational Circuits Digital Logic (Materials taken primarily from: http://www.facstaff.bucknell.edu/mastascu/elessonshtml/eeindex.html http://www.cs.princeton.edu/~cos126 ) Digital Systems What is a

More information

(Refer Slide Time 6:48)

(Refer Slide Time 6:48) Digital Circuits and Systems Prof. S. Srinivasan Department of Electrical Engineering Indian Institute of Technology Madras Lecture - 8 Karnaugh Map Minimization using Maxterms We have been taking about

More information

Lesson 2: Right Triangle Trigonometry

Lesson 2: Right Triangle Trigonometry Lesson : Right Triangle Trigonometry lthough Trigonometry is used to solve many prolems, historially it was first applied to prolems that involve a right triangle. This an e extended to non-right triangles

More information

Chapter 2 Part 4 Combinational Logic Circuits

Chapter 2 Part 4 Combinational Logic Circuits University of Wisconsin - Madison EE/omp Sci 352 Digital Systems undamentals Kewal K. Saluja and Yu Hen Hu Spring 2002 hapter 2 Part 4 ombinational Logic ircuits Originals by: harles R. Kime and Tom Kamisnski

More information

Boolean algebra. June 17, Howard Huang 1

Boolean algebra. June 17, Howard Huang 1 Boolean algebra Yesterday we talked about how analog voltages can represent the logical values true and false. We introduced the basic Boolean operations AND, OR and NOT, which can be implemented in hardware

More information

Digital Logic Design. Outline

Digital Logic Design. Outline Digital Logic Design Gate-Level Minimization CSE32 Fall 2 Outline The Map Method 2,3,4 variable maps 5 and 6 variable maps (very briefly) Product of sums simplification Don t Care conditions NAND and NOR

More information

Dynamic Programming. Lecture #8 of Algorithms, Data structures and Complexity. Joost-Pieter Katoen Formal Methods and Tools Group

Dynamic Programming. Lecture #8 of Algorithms, Data structures and Complexity. Joost-Pieter Katoen Formal Methods and Tools Group Dynami Programming Leture #8 of Algorithms, Data strutures and Complexity Joost-Pieter Katoen Formal Methods and Tools Group E-mail: katoen@s.utwente.nl Otober 29, 2002 JPK #8: Dynami Programming ADC (214020)

More information

Combinational hazards

Combinational hazards Combinational hazards We break down combinational hazards into two major categories, logic hazards and function hazards. A logic hazard is characterized by the fact that it can be eliminated by proper

More information

1 The Knuth-Morris-Pratt Algorithm

1 The Knuth-Morris-Pratt Algorithm 5-45/65: Design & Analysis of Algorithms September 26, 26 Leture #9: String Mathing last hanged: September 26, 27 There s an entire field dediated to solving problems on strings. The book Algorithms on

More information