ISDN peripheral control

Transcription

1 INTRODUCTION There are currently numerous integrated circuits available for data communication. They are mostly of a high complexity and their functionality covers nearly all requirements for the development of new telecommunication equipment. However, in many cases, the highly specialized communication ICs do not cover the intended product function exactly, and a few, sometimes simple functions remain to be realized seperately. Those extra parts of the electronics design can often be satisfied by the use of programmable logic circuits,a fact, that shall be demonstrated by this application note. In order to complete the prototype of a new system board for data transmission, a small controller unit needed to be designed. The functions of this controller is to monitor an incoming serial stream of data bits, indicating certain commands at fixed positions within this bitstream, and to control an output data line in response to these commands. SPECIFICATION OF THE CONTROLLER FUNCTION The first function in this controller is that of monitoring an incoming stream of data bits. A general overview of the construction and timing relations of the serial bitstream and associated input control signals is shown in Figure 1. The understanding of this structure is most important for the specification of the controller design. The serial stream of data bits (via SDI Serial Data In) is synchronous to the clock signal DCL and one data bit has the length of two clock cycles. The bit stream itself is subdivided into single data words of 32 Bits, whereas the beginning and the length of each data word is indicated by the frame signal FSC. Given this structure, the first task of the controller is to synchronize itself on the data frame and to isolate the data bits number These are the so called command indication bits (C/I Command Indication in Figure 1) serving for the link and network control between the communicating stations. The internal function of the desired controller is to evaluate the C/I-Bits and to send the appropriate response on the output data stream. The complete sequence of commands during a transmission session is shown in Figure 2, illustrating the order of incoming commands and corresponding output bit pattern. Accordingly to this graphical specification the controller has to detect the two commands PU (Power Up) and DR (Deactivate Request), and on the output side, it has to drive the line SDO (Serial Data Out) in dependence on these commands. Basically SDO has a constant level Low after the activation of a communication session. But if the input command PU is recognized, the controller shall send a respond command ARN (Active Request None Loop) within the following data frames and at the same bit position as the incoming C/I-Bits. The command ARN on the line SDO is to send till the command DR is detected at the input side. The command DR marks the end of a communication session and one Frame after its detection the line SDO is to switch to the deactive signal level ( High ) as it is shown in Figure 2. Beside the elementary fuctionality, some additional constraints need to be observed. First, it should be considered, that the complete design needs to have an asynchronous part. During the period of no communication, no frame and no clock signal is attached at the inputs and the initial change of the line Start demands an immediate acknowledgment before the clock becomes externally activated. So, the synchronous mode of operation is to extend with an asynchronous design part. The second constraint was the demand that the incoming data are to read with the HL-edge of the second clock cycle (see Figure 1), while a signal change of the output line is to initiate synchronous with the LH-edge of the system clock. This requirement assures the correct recognition of the incoming data also for long distance transmissions with slow rising signal edges, but therefore the design needs to work with two active clock edges. EXTERNAL ACTIVATION OF A TRANSMISSION SESSION START ONE DATA FRAME FSC DCL SDI SDO EXTERNAL CLOCK BECOMES ACTIVE AFTER THE HL-EDGE OF SDO DATA 0 PERIOD OF ONE DATA BIT = 2 CLOCK CYCLES CONFIRMATION ACTIVATION READ C/I-BIT0 READ C/I-BIT3 COMMAND INDICATION BITS DATA 31 Figure 1. General Structure of the Data Frame and Basic Timing Relations October

2 Figure 2. Command Sequence for a Complete Transmission Session October

3 FUNCTIONAL DESIGN DESCRIPTION Figure 3 shows a possible approach for the realization of the specified controller function. This block structure contains a cyclic 6-Bit-Counter clocked with DCL and synchronized on the frame signal FSC. Refering to the counter value it is possible to determine the position of Command-Bits within input bitstream and so the decoder block CI_Decod can derive the appropriate control signals for Read- and Write-Cycles of Data. The signal CI controls the second essential module, the shift register, via its Enable-Input. The 4-Bit Shift-Register has to read the four Command Bits from the serial bitstream and the following Decoder Com_Decod has just to indicate the two relevant commands, PU and DR. Finally, the real controller is contained within the block Control. There a finite state machine evaluates the PU and DR signals after a new command was read and in correspondence to the actual section of a transmission session the appropriate bit pattern for the output will be generated. Using this global design description, all constraints can be satisfied easily while realizing the complete controller function. First, the shift-register and the Controller-module can be clocked with the inverted and noninverted DCL-pulse and so different clock edges are taken for the Readand Write- Cycle of Data Bits. Furthermore, the asynchronous initialization of the controller is accomplished by the Reset-Inputs of the internal Flip-Flop s and the combinatorial output decoder. Finally the clear structure of the design guarantees the complete testability of its circuit implementation. While a functional specification of each block in this initial design description can easily be created, the final design implementation leads to serious problems. Due to its structure the design requires a sequencer component with one or more combinatorial outputs, and the presence of sequential blocks with two different clocks needs a circuit that fit this condition too. Additionally, the complete design requires a minimum of thirteen internal Flip-Flop s. If these three constraints are taken together an appropriate component can hardly be found. Simple PLDs cannot contain so much multilevel logic. Complex PLDs turned out to be too expensive for this application. So, a different design approach was indicated for this design. The schematic-like block structure was given up for a more abstract, but also compact design description. DESIGN IMPLEMENTATION Since the original design couldn t be directly implemented in a simple PLD, a complete revision of its structure had to be carried out. The resulting description file is to see in Figure 4, now given as an abstract HDL-file. The essential advantage of this design description consists of the facts that abstract descriptions are favorable for all kinds of automatic optimization, and that they can easily be adapted to several hardware architectures. Several changes were made within the design description. First, the counter and the control unit are now merged into one state machine. In doing so, an initial concept was given up. Instead of counting through the whole data frame, the sequencer waits just for the rising and the falling clock edges of the frame signal. So only the second part of a data frame needs to be evaluated and the state machine counts only the steps up to the beginning of the C/I-Bits. Furthermore, some FF s of the shift register are now used twice. While reading the C/I-Bits from the incoming bitstream they have their original function, but during the rest of time they serve as flags. So one FF stores the information about a detected DR-command, while another FF helps to evaluate a frame signal edge timing. Here the feature of two different clock pulses is taken in order to achieve a save mode of operation. All in all the design function is now given in a much more compact description and the abstract description style allows its easy mapping onto different device architectures. So finally a PLC42VA12 was found to be a suitable circuit for the design s realization. In spite of its general fitting, a successful implementation of the design requires design optimization. An optimal state assignment for the included state machine description as well as a final boolean minimization are absolutely necessary for the design compilation and Figure 5 shows the optimized version, which can now be compiled directly. Figure 7 gives a corresponding Pinning for the PLC42VA12 and Figure 6 shows a simulation output resulted from the implemented circuit model. This part of the simulation represents the beginning of a communication session from the initialisation via the Start-signal up to the first acknowledgement (ARN) on output SDO. COUNT6BIT CI_DECOD FSC FSC BIT5 IN5 BIT4 IN4 CI CLK(C) BIT3 IN3 BIT2 IN2 BIT1 RST(R) BIT0 IN1 CIEND IN0 CONTROL CIEND CISTART SHIFTREG COM_DECOD SHENABLE DAT3(Q) IN4 PU PU SDI DATAIN DAT2(Q) IN3 DCL CLK(C) RST(R) DAT1(Q) DAT0(Q) IN2 IN1 DR DR OUT_DECOD SDO1(M) DAT1 CLOCK(C) START RESET(R) SERDATA SDO DAT2 Figure 3. Block Structure of the Controller Design October

4 @PINLIST Start I ; FSC I ; DCL I ; SDI I ; SDO O EQUATIONS Shift Enable Signal defines the Time Slots to read the Command Bits ShEnable = Q4 * Q3 * Q2 * /Q1 * /Q0 + Q4 * /Q3 * Q2 * /Q1 * Q0 + Q4 * /Q3 * Q2 * Q1 * /Q0 + Q4 * /Q3 * /Q2 * Q1 * Q0 ; DR and PU mark the corresponding Commands decoded from the Shift Register DR = /DataBit3 * /DataBit2 * /DataBit1 * /DataBit0 ; PU = /DataBit3 * DataBit2 * DataBit1 * DataBit0 ; Shift Register SHIFT operation only when Enable, else HOLD DataBit0.CLK = / DCL ; DataBit0.RST = / Start ; DataBit0.J = ShEnable * SDI ; DataBit0.K = ShEnable * / SDI DataBit1.CLK = / DCL ; DataBit1.RST = / Start ; DataBit1.J = ShEnable * DataBit0 ; DataBit1.K = ShEnable * / DataBit0 DataBit2 serves also for the Detection of a new Frame Phase DataBit2.CLK = / DCL ; DataBit2.RST = / Start ; DataBit2.J = ShEnable * DataBit1 + /Q4 * /Q3 * /Q2 * /Q1 * /Q0 * FSC ; DataBit2.K = ShEnable * / DataBit1 + /Q4 * /Q3 * /Q2 * /Q1 * Q0 * /FSC DataBit3 serves also as Flag for a detected DR Command DataBit3.CLK = / DCL ; DataBit3.RST = / Start ; DataBit3.J = ShEnable * DataBit2 + Q4 * /Q3 * /Q2 * /Q1 * Q0 * DR ; DataBit3.K = ShEnable * / DataBit2 + Q4 * /Q3 * /Q2 * /Q1 * Q0 * /DR ; The Flag PU stores the switches at the first occurence of the Command PU PU_Flag.CLK = DCL ; PU_Flag.RST = / Start ; PU_Flag.J = Q4 * /Q3 * /Q2 * Q1 * Q0 * PU ; PU_Flag.K = 0 ; Q4.CLK = DCL ; Q4.RST = / Start ; Q3.CLK = DCL ; Q3.RST = / Start ; Q2.CLK = DCL ; Q2.RST = / Start ; Q1.CLK = DCL ; Q1.RST = / Start ; Q0.CLK = DCL ; Q0.RST = / Start ; Figure 4. Complete HDL-Description for the Controller (1 of 3) October

5 Finally the Output Signal SDO = Start + Q4 * Q3 * Q2 * /Q1 * PU_Flag + Q4 * /Q3 * /Q2 * /Q1 * /Q0 VECTORS [ DataBit3, DataBit2 ] FSC_Flag = 1 B; NFSC_Flag = 0 B; DR_Flag = 1 B; NDR_Flag = 0 VECTORS [ Q4, Q3, Q2, Q1, Q0 ] JKFFR state assignment with One Bit Changes for a Minimum of Logic Wait_on_FSC = B; Wait_on_NFSC = B; Step1 = B; to much Step2 = B; Step3 = B; Step4 = B; Step5 = B; Step6 = B; Step7 = B; Step8 = B; Step9 = B; Step10 = B; Step11 = B; Step12 = B; Step13 = B; Step14 = B; Step15 = B; Step16 = B; Step17 = B; Step18 = B; Step19 = B; Step20 = B; DatBit1_0 = B; DatBit1_1 = B; DatBit2_0 = B; DatBit2_1 = B; DatBit3_0 = B; DatBit3_1 = B; DatBit4_0 = B; DatBit4_1 = B; End_Cycle = B; End = WHILE [ Wait_on_FSC ] IF [ FSC_Flag ] THEN [ Wait_on_NFSC ] else remain in this state WHILE [ Wait_on_NFSC ] IF [ NFSC_Flag ] THEN [ Step2 ] WHILE [ Step1 ] IF [] THEN [ Step2 ] WHILE [ Step2 ] IF [] THEN [ Step3 ] WHILE [ Step3 ] IF [] THEN [ Step4 ] WHILE [ Step4 ] IF [] THEN [ Step5 ] Figure 4. Complete HDL-Description for the Controller (2 of 3) October

6 WHILE [ Step5 ] IF [] THEN [ Step6 ] WHILE [ Step6 ] IF [] THEN [ Step7 ] WHILE [ Step7 ] IF [] THEN [ Step8 ] WHILE [ Step8 ] IF [] THEN [ Step9 ] WHILE [ Step9 ] IF [] THEN [ Step10 ] WHILE [ Step10 ] IF [] THEN [ Step11 ] WHILE [ Step11 ] IF [] THEN [ Step12 ] WHILE [ Step12 ] IF [] THEN [ Step13 ] WHILE [ Step13 ] IF [] THEN [ Step14 ] WHILE [ Step14 ] IF [] THEN [ Step15 ] WHILE [ Step15 ] IF [] THEN [ Step16 ] WHILE [ Step16 ] IF [] THEN [ Step17 ] WHILE [ Step17 ] IF [] THEN [ Step18 ] WHILE [ Step18 ] IF [] THEN [ Step19 ] WHILE [ Step19 ] IF [] THEN [ Step20 ] WHILE [ Step20 ] IF [ DR_Flag ] THEN [ End ] IF [ NDR_Flag ] THEN [ DatBit1_0 ] WHILE [ DatBit1_0 ] IF [] THEN [ DatBit1_1 ] WHILE [ DatBit1_1 ] IF [] THEN [ DatBit2_0 ] WHILE [ DatBit2_0 ] IF [] THEN [ DatBit2_1 ] WHILE [ DatBit2_1 ] IF [] THEN [ DatBit3_0 ] WHILE [ DatBit3_0 ] IF [] THEN [ DatBit3_1 ] WHILE [ DatBit3_1 ] IF [] THEN [ DatBit4_0 ] WHILE [ DatBit4_0 ] IF [] THEN [ DatBit4_1 ] WHILE [ DatBit4_1 ] IF [] THEN [ End_Cycle ] WHILE [ End_Cycle ] IF [] THEN [ Wait_on_FSC ] WHILE [ End ] IF [] THEN [ End ] Figure 4. Complete HDL-Description for the Controller (3 of 3) October

7 @PINLIST Start I ; FSC I ; DCL I ; SDI I ; SDO O EQUATIONS Shift Enable Signal defines the Time Slots to read the Command Bits ShEnable = Q4 * Q3 * Q2 * /Q1 * /Q0 + Q4 * /Q3 * Q2 * /Q1 * Q0 + Q4 * /Q3 * Q2 * Q1 * /Q0 + Q4 * /Q3 * /Q2 * Q1 * Q0 ; DR and PU mark the corresponding Commands decoded from the Shift Register DR = /DataBit3 * /DataBit2 * /DataBit1 * /DataBit0 ; PU = /DataBit3 * DataBit2 * DataBit1 * DataBit0 ; Shift Register SHIFT operation only when Enable, else HOLD DataBit0.CLK = / DCL ; DataBit0.RST = / Start ; DataBit0.J = ShEnable * SDI ; DataBit0.K = ShEnable * / SDI DataBit1.CLK = / DCL ; DataBit1.RST = / Start ; DataBit1.J = Q4 * /Q3 * Q2 * /Q1 * Q0 * DataBit0 + Q4 * /Q3 * Q2 * Q1 * /Q0 * DataBit0 + Q4 * /Q3 * /Q2 * Q1 * Q0 * DataBit0 ; DataBit1.K = Q4 * /Q3 * Q2 * /Q1 * Q0 * /DataBit0 + Q4 * /Q3 * Q2 * Q1 * /Q0 * /DataBit0 + Q4 * /Q3 * /Q2 * Q1 * Q0 * /DataBit0 DataBit2 serves also for the Detection of a new Frame Phase DataBit2.CLK = / DCL ; DataBit2.RST = / Start ; DataBit2.J = Q4 * /Q3 * Q2 * Q1 * /Q0 * DataBit1 + Q4 * /Q3 * /Q2 * Q1 * Q0 * DataBit1 + /Q4 * /Q3 * /Q2 * /Q1 * /Q0 * FSC ; DataBit2.K = Q4 * /Q3 * Q2 * Q1 * /Q0 * /DataBit1 + Q4 * /Q3 * /Q2 * Q1 * Q0 * /DataBit1 + /Q4 * /Q3 * /Q2 * /Q1 * Q0 * /FSC DataBit3 serves also as Flag for a detected DR Command DataBit3.CLK = / DCL ; DataBit3.RST = / Start ; DataBit3.J = Q4 * /Q3 * /Q2 * Q1 * Q0 * DataBit2 + Q4 * /Q3 * /Q2 * /Q1 * Q0 * DR ; DataBit3.K = Q4 * /Q3 * /Q2 * Q1 * Q0 * / DataBit2 + Q4 * /Q3 * /Q2 * /Q1 * Q0 * /DR ; The Flag PU stores the switches at the first occurence of the Command PU PU_Flag.CLK = DCL ; PU_Flag.RST = / Start ; PU_Flag.J = Q4 * /Q3 * /Q2 * Q1 * Q0 * PU ; PU_Flag.K = 0 ; Q4.CLK = DCL ; Q4.RST = / Start ; Q4.J = /Q4 * Q3 * /Q2 * /Q1 * /Q0 ; Q4.K = Q4 * /Q3 * /Q2 * /Q1 * Q0 ; Figure 5. HDL-Description for the Final Design Implementation (1 of 2) October

8 Q3.CLK = DCL ; Q3.RST = / Start ; Q3.J = /Q4 * /Q3 * Q2 * /Q1 * /Q0 ; Q3.K = Q4 * Q3 * Q2 * Q1 * Q0 * Databit3 + Q4 * Q3 * Q2 * /Q1 * /Q0 ; Q2.CLK = DCL ; Q2.RST = / Start ; Q2.J = /Q4 * /Q3 * /Q2 * Q1 * /Q0 + Q4 * Q3 * /Q2 * Q1 * /Q0 ; Q2.K = /Q4 * Q3 * Q2 * Q1 * /Q0 + Q4 * Q3 * Q2 * Q1 * Q0 * DataBit3 + Q4 * /Q3 * Q2 * Q1 * /Q0 ; Q1.CLK = DCL ; Q1.RST = / Start ; Q1.J = /Q4 * /Q3 * /Q2 * /Q1 * Q0 * /Databit2 + /Q4 * Q3 * Q2 * /Q1 * Q0 + Q4 * Q3 * /Q2 * /Q1 * Q0 + Q4 * /Q3 * Q2 * /Q1 * Q0 ; Q1.K = /Q4 * /Q3 * Q2 * Q1 * Q0 + /Q4 * Q3 * /Q2 * Q1 * Q0 + Q4 * Q3 * Q2 * Q1 * Q0 + /Q4 * /Q3 * /Q2 * Q1 * Q0 + Q4 * /Q3 * /Q2 * Q1 * Q0 ; Q0.CLK = DCL ; Q0.RST = / Start ; Q0.J = /Q4 * /Q3 * /Q2 * /Q1 * /Q0 * DataBit2 + /Q4 * /Q3 * Q2 * Q1 * /Q0 + /Q4 * Q3 * Q2 * /Q1 * /Q0 + /Q4 * Q3 * /Q2 * Q1 * /Q0 + Q4 * Q3 * /Q2 * /Q1 * /Q0 + Q4 * Q3 * Q2 * Q1 * /Q0 + Q4 * /Q3 * Q2 * /Q1 * /Q0 + Q4 * /Q3 * /Q2 * Q1 * /Q0 ; Q0.K = /Q4 * /Q3 * /Q2 * /Q1 * Q0 * /DataBit2 + /Q4 * /Q3 * Q2 * /Q1 * Q0 + /Q4 * Q3 * Q2 * Q1 * Q0 + /Q4 * Q3 * /Q2 * /Q1 * Q0 + Q4 * Q3 * /Q2 * Q1 * Q0 + Q4 * Q3 * Q2 * Q1 * Q0 * DataBit3 + Q4 * Q3 * Q2 * /Q1 * Q0 + Q4 * /Q3 * Q2 * Q1 * Q0 Finally the Output Signal SDO = Start + Q4 * Q3 * Q2 * /Q1 * PU_Flag + Q4 * /Q3 * /Q2 * /Q1 * /Q0 ; Figure 5. HDL-Description for the Final Design Implementation (2 of 2) October

9 Figure 6. Simulator Output of the Modeled Circuit Implementation Device Pin1 Pin2 Pin3 Pin4 Pin14 = C42VA12 = DCL = START = FSC = SDI = SDO Figure 7. Pinlist for the Controller Implementation October

10 *************************************************** * Output of Updsim Version 1.85 * * Date: 02/04/93 Time: 13:56:28 * *************************************************** * * * Input File Name : APPNOTE3.net * * Output File Name : APPNOTE3.SCL * * * *************************************************** * P START, FSC, DCL, SDI, PU_Flag, DataBit3, DataBit2, DataBit1, DataBit0, # SDO PCO * S 1 ( 500 ) START S 0 ( 1000, 33000, 65000, 97000, , , , ) FSC S 1 ( 500, 1000, etc) DCL S 0 ( 55000, 61000, , , , ) SDI SU time = * F Figure 8. SCL SUMMARY The example of the developed controller has shown that even relative complex designs can be realized with quite small PLDs. Especially if sequential control functions or irregular logic is to be implemented. Hardware programmable logic ICs are often the most suitable solution and sometimes the use of PLDs can simplify the development of new boards and systems significantly. In addition, the example also illustrates the great effect, which can be achieved by certain design styles and by an appropriate optimization of designs. An initial design description has an essential influence on the final network and its implementation and so it affects the requirements for a component as well as the whole projects costs. By optimization a designer can reduce the amount of gates for a certain design too, leading to a much more efficient use of the given components. October