Routing Tree Construction with Buffer Insertion under Buffer Location Constraints and Wiring Obstacles

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1 Routing Tree Construction with Buffer Insertion under Buffer Location Constraints and Wiring Obstacles Ying Rao, Tianxiang Yang University of Wisconsin Madison {yrao, ABSTRACT Buffer insertion is crucial in deep submicron VLSI design. We implement a new algorithm proposed by Tang et al [1] in which a buffered routing tree is constructed on a grid chip area under buffer location constraints and wiring obstacles. We differ from the original algorithm in that we adopt Elmore delay model instead of the Rubinstein s model [2]. Tree structure analysis is first made to dissect a routing tree into components of several categories. Such categorization, including wire path, buffered path, buffer combination, BC-subtree has made it possible for us to enumerate different routing tree structures, thus enabling formulating the Maze Routing with Buffer Insertion problem as a shortest path graph problem. With existing graph algorithms we are then able to find optimal solutions. 1. INTRODUCTION Routing has become one of the most challenging tasks facing VLSI circuit designers as fabrication technology moves into deep sub-micron territory. It has been shown that, as a result of scaling, interconnect delays becomes the most significant part of total system delay [3]. Routing information is highly desirable at an early stage during the layout design process for helping designers achieve various performance optimizations. There has been considerable previous research in optimizing interconnect delays. Two main approaches are buffer insertion and wire sizing. We are going to focus on buffer insertion. Work has shown that when a single long wire is properly buffered, its delay can be reduced to a linear function of its length [4]. Several algorithms have been proposed. In [5], Van Ginnekan proposed a polynomial time algorithm for buffer placement in distributed RC trees. This buffer insertion algorithm is based on dynamic programming (DP) for a given Steiner tree. It has since been generalized to other applications such as low power [6], buffered Steiner tree construction [7], etc. However, the DP formulation is limited to inserting buffers at tree vertices, treating individual tree edges as a connection of wire segments. To obtain a buffering which is close to optimal, the number of wire segments needs to be made large for long wires. In [8], Alpert and Devgan propose an algorithm for segmenting individual wires to reduce the size of the input to the Van Ginnekan s algorithm. These algorithms can efficiently construct a buffered routing tree, but they cannot handle buffer and routing obstacles. Zhou et al. [9] introduced the concept of buffer obstacle and proposed an algorithm using DP to minimize interconnect delay by simultaneous routing and buffer insertion for 2-pin net with restriction on buffer locations. More recently, Lai and Wong [10] proposed a graph-based formulation of the Maze Routing problem with buffer insertion and wire sizing. Jaganathan et al. [11] studied the buffer insertion problem to maximize the delay reduction to cost ratio. However, they can only deal with 2-pin nets. Cong and Yuan presented in [12] an algorithm for simultaneous routing tree construction and buffer insertion for multiple -pin nets under fixed buffer locations. It used DP approach to construct the routing tree in a bottom-up fashion. Our algorithm challenges this algorithm. Both theoretical and experimental results show that our graph-based algorithm outperforms the DPbased algorithm by a large margin

2 In the rest of this paper report, we first briefly review Elmore delay model for wire, buffer and tree cases in section 2. In section 3, we formally formulate our problem as a routing tree with buffer insertion (RTB) problem. In section 4, we study Lai and Wong s maze routing algorithm with buffer insertion [10] for 2-pin case which is one of the bases for our tree routing algorithm. 2- pin case maze routing is used in one of our important lookup table construction. In section 5, we discuss our maze routing tree algorithm in detail with some actual implementation details that facilitate the algorithm realization. In the last two sections, we show our implementation results and make some further observations. where c(t v ) is simply the capacitive load seen at v, equaling to the sum of loads of the left and right subtrees c(t l(v) ) and c(t r(v) ), and the capacitance of the wores to those subtrees, C el(v) and C er(v). Given this notation, the Elmore delay of wire e v is defined as: cev elmore( e v ) = re ( + c( Tv )) v 2 We adopt Elmore delay model for its accuracy, although Tang et al. adopted Rubinstein s delay model for simplic ity. 2. DELAY MODEL Elmore delay model has been a popular delay model since it was proposed in [4] because of its simple analytical form, fidelity and other properties [13]. If we model a wire segment as a π -type element (Fig. 1), the Elmore delay of the individual wire segment is: where d 1 t wire = rw cw + c 2 ( d c is the downstream capacitance of this wire segment. Similarly, for an inserted buffer with capacitance c b, resistance r b, and intrinsic delay t in, the Elmore delay is computed as: t = r c + t buffer b d in. ) 3. PROBLEM FORMULATION Given a source node and multiple sink nodes on a routing grid, our goal is to construct a routing tree from source to all sinks with feasible buffer insertion in the presence of buffer location blockage and wiring obstacles. Buffers cannot be inserted into buffer-constrained areas and routing wires cannot cross wiring obstacle. We name this problem RTB (Routing-tree with buffer insertion) and give its formal definition as follows: Problem RTB : Given a routing graph G=(V,E), a buffer library B, a source node s V and k sink nodes t 1, t 2,, t k V, find a buffered routing tree T rooted at s and leafed at t i, i=1,, k, for each node v T, b(v) B {0} where b(v)=0 indicates no buffer is inserted at v and b(v) 0 requires v is a buffer node, for each segment l T wire w(l) W, such that the maximum delay from s to t i I=1,,k, is minimized. 4. TWO-PIN MAZE ROUTING WITH BUFFER INSERTION Figure 1: Elmore Delay Model To compute the Elmore delay of a wire in tree T, we first recursively define c(t v ) - the total lumped capacitance of T, as follows: We adopt Lai and Wong s algorithm [10] for 2- pin maze routing with buffer insertion. This algorithm serves a basic element in the lookup table construction phase in our algorithm

3 The 2-pin buffered path maze routing algorithm introduces the idea of directed BPgraph where each node in the graph stands for a buffer choice and each edge connecting two nodes is weighted with its Elmore delay along the edge. For simplic ity, we only consider one buffer type. Figure 3 shows the BP-graph for the sample routing grid in Figure 2. Figure 4: Shortest Path Problem for BP-graph 5. TREE MAZE ROUTING WITH BUFFER INSERTION Figure 2: A Simple Routing Grid (Dark block: wiring obstacles. Grey block: buffer location blockage. s: source. t: sink. Other dots: buffer location candidates.) Figure 3: Part of BP-Graph (Vertex u bo with buffer b 0 and its connections to neighbors in the BP-Graph BG for the grid graph in Figure 2.) Once BP-graph is constructed, the minimumdelay routing problem is a shortest path graph problem from one source and one target in a directed graph. That is, while all buffer locations are considered as buffer insertion location candidates, the preferred buffer locations are found by finding the shortest path from the source to the sink. Figure 4 shows a simple example of the shortest path formulation and its solution. For more generalized applications, we need to construct a routing tree starting from a source (root) to multiple sinks (leaves). In order to analyze a buffered routing tree structure, we need to make a few notations. 5.1 Notations B: buffer library of different buffer choices. (For simplicity, our implementation uses only one buffer type) F: the set of nodes which allows buffer to be inserted (buffer node). N={s} { t i i=1,,k } F: the set consisting of the source, the sinks and the possible buffer nodes. G ={t i i=1,,k} non-empty sink set. Wire Path: a path connecting two nodes in N with buffers inserted between. A wire path is a special buffered path. Buffer Combination: a tree component connecting three or more nodes in N without internal buffers. For convenience, we call the upstream node in a buffer combination as driver, and the other nodes as receiver. Subtree: a tree connecting a buffer node or the source to a subset of sinks. BC-subtree: a subtree beginning with a buffer combination. A BC-subtree is a special subtree. Wire Path Table: a table storing precomputed optimal buffer-to-buffer wire sizing solutions for wire paths. Buffer-Combination Table: a table storing pre-computed optimal solutions for buffered path

4 the buffer combination, the driver resistance of v and the load capacitances of ri (i=1,2,,t). Figure 6 shows a buffer combination with distance configuration e, l 1 and l 2. Degree of buffer combination (=t+1) is small in practice (or it will cause large delay). We can restrict the maximum degree of a buffer combination so that the distance configuration can be obtained by computing a Steiner tree of a small number of nodes. 5.2 Main Idea Figure 5: Illustration of notations. A buffered routing tree is a set of buffer combinations and connecting buffer paths. A buffered path is a set of connected wire paths. Both wire path and buffer combination can be pre-computed and stored in Wirepath Table, Bufferred Path Table and Buffer Combination Table. The minimum delay of a wire path from one node u to another node v is a function of d(u,v) shortest distance between u and v, the driver resistance in u and the load capacitance in v. Thus the wirepath delay can be pre-calculated and stored in the Wirepath lookup table. The lookup entry is d(u,v) when we have only one buffer type. With the above three pre-computed lookup tables, it would then facilitate Elmore delay computations in later phases of our algorithm. The general idea is to enumerate all tree constructing possibilities. A more detailed implementation procedure is shown in the next sub-section. 5.3 Algorithm Formulation The following algorithm formulation shows the steps to implement the general idea stated above. Note that the loops in this algorithm only provide a very general overview. More details on implementation is presented in the next subsection. Refer to our open source for more details on recursive tree construction with exhaustive combination searching and indexing schemes. Distance from node u to v is computed by considering all possible buffer insertion combinations (using aforementioned BP-Graph). With lookup entry being ((u,v), path between u and v), the solution to lookup is the buffer locations along the path and minimum delay between u and v. The delay of a buffer combination (v, r1, r2,, rt) is a function of distance configuration of Figure 7: Graph-RTBW Algorithm by Tang et al. Figure 6: 3-node buffer combination example 5.4 Implementation Procedure: - 4 -

5 1. Retrieve all possible buffer insertion positions from the grid graph by excluding grid nodes in buffer blockage wire obstacle areas 2. Let N={s} F T, where F={f i, buffer positions} and T={t i, target positions}. Calculate the distance between each pair of nodes with maze router. Calculate Elmore delays for each pair of nodes and store them in the Wirepath Table. 3. Construct a directed graph in which all elements of N are vertices, and the edges are weighted by their delays. Note that there the graph is bidirectional between any pair of nodes except that there s only one edge coming from the source and only one edge going into each target. 4. Calculate the shortest path between any pair of vertices by applying Dijkstra s algorithm and store the path information into Buffered Path table. 5. Calculate the length of the Steiner tree of any three nodes in N, calculate the delay of this tree and store them in the Buffer Combination Table. 6. Give an index to each combination of any number of targets. 7. Starting from the 2-combinations of targets, get the minimum delay of trees starting from buffer combination that roots at every driver including source and buffer positions. Also store the tree with minimum delay. The shortest path between any driver and this target combination can then be obtained by applying Dijkstra's algorithm. Sore the results. 8. Go through all the target combinations until finally it reaches the whole set of all targets. The shortest path from source to the combination is the routing tree we want. Figure 8 shows an example of the process to enumerate target combinations. 9. Go through the tree from top(source) down until all the nodes are just one target in which intermediate nodes are positions to insert buffers. 10. Using the tree structure obtained above and maze -route every two adjacent nodes. Figure 8: Enumerate target combinations from 1- combinations to 3-combinations. 6. RESULTS Figure 9.1~9.9 show test results for four cases. Figures are plotted in Figure. Note that on the grid graph, solid squares denote wiring obstacles and dotted squares denote buffer blockage areas. On the routing trees, square with a diamond denotes source; squares with asterisks denote targets and blank squares denotes inserted buffers. Test Case Grid Size 10x10 10x10 10x10 30x30 Number of Targets Number of Buffers System Runtime (Sec.) User Time (Sec.) Figure 9.1: General statistics for 4 tests. (Run-time refers to system-time)

6 Figure 9.2: Routing tree for test Figure 9.6: Routing tree visualization for test 3. Figure 9.3: Routing tree visualization for test Figure 9.4: Routing tree for test 2 Figure 9.5: Routing tree visualization for test 2 Figure 9.7: Routing tree visualization for test Figure 9.8: Routing tree visualization for test

7 Figure 9.9: Routing tree visualization for test 4 7. DISCUSSION We have successfully implemented graph-based routing-tree construction with wiring and buffer location constraints. Experiments have shown that optimal solutions can be found fast for a reasonable problem size. The exhaustive enumeration nature of this algorithm can find optimal buffered routing tree. The future implementation improvement may be made in the final stage of the algorithm. It would be more advantageous in terms of runtime to use Steiner-tree routing algorithms (with obstacles) to route the final buffered tree. Currently we use Lee s algorithm to do maze routing due to very limited time. By comparing our simplified implementation with that proposed in the original algorithm [1], adding wiresizing to the routing tree actually won t take much more effort. Thus a more generalized buffered routing tree with wiresizing can be build upon our current implementation. References [1] X Tang, R Tian, H Xiang and D.F. Wong, A New Algorithm for Routing Tree Construction with Buffer Insertion and Wire Sizing under Obstacle Constriants ICCAD, pages , 2001 [2] J. Rubinstein, P. Penfield, and N.A. Horowitz, Signal delay in RC tree networks, IEEE TCAD 2:3, pp , 1983 [3] The National Technology Roadmap for Semiconductors, Semiconductor Industry Association, 1997 [4] J. Cong and Z. Pan, Interconnect Performance Estimation Models For Synthesis and Design Planning Proc. Intl. Workshop on Logic Synthesis, pp , 1998 [5] L.P.P.P. van Ginneken, Buffer Placement in Distributed RC-tree Networks for Minimal Elmore Delay Proc. Int l Symp. On Circuits and Systems, 1990, pp [6] J. Lillis, C-K Cheng, and T T Y Lin, Optimal Wire Sizing and Buffer Insertion for Low Power and a Generalized Delay Model Proc. Intl. Conf. On Computer- Aided Design, pp , 1995 [7] T Okamoto and J Cong, Buffered Steiner Tree Construction with Wire Sizing for Interconnect Layout Optimization Pro. Intl. Conf. On Computer-Aided Design, pp , 1996 [8] C Alpert and A Devgan, Wire Segmenting for Improved Buffer Insertion Proc of the Design Automation Conf., pp , 1997 [9] H. Zhou, D F Wong, I M Liu and A Aziz, Simultaneously Routing and Buffer Insertion with Restrictions on Buffer Locations Proc of the Design Automation Conf., pp , 1999 [10] M Lai and D F Wong, Maze routing with buffer insertion and wiresizing, DAC-00, pp , 2000 [11] A Jagannathan, S W Hur and J Lillis, A fast algorithm for context -aware buffer insertion, DAC-00, pp , 2000 [12] J Cong and X Yuan, Routing tree construction under fixed buffer locations, DAC-00, pp , 2000 [13] W.C. Elmore, The Transient Response of Damped Linear Network with Particular Regard to Wideband Amplifiers J. Applied Physics, 1948, pp [14] R. Gupta, et al., The Elmore Delay as a Bound for RC Trees with Generalized Input Signals, Proc, ACMIEEE Design Automation Conference, 1995, pp

8 APPENDIX README file for Source Code: File: README Author: Ying Rao, Tianxiang Yang 556 Final Project Source Description. * BUILD SOURCE 1. Untar the source distribution % tar xzf buffer-insertion1.3.tar.gz 2. Make binary by cding into.556_project % make The source should be built correctly. * RUN TESTBENCH 1. At this point you can either run the program by typing % bufferinserstionmain input output matlab_output where input is the input test file accessable under testfile directly, output is the file name for output, and matlab_output is for matlab source code for visualization. or you can simply type % make test1 (or test2, test3, test4) We provide four testbenches for testing purposes. * TESTBENCH FORMAT A sample txt test file looks like: Detailed interpretation of the above file: width, height define blocked areas for wiring. -- there are total 3 blocked areas. -- the first area defined by the second area defined by the third area defined by define blocked areas for buffer insertion -- there are total 2 such areas -- the first defined by the second one is the four numbers represent a rectangle's two diagonal coordinates the source point 4 -- the number of the targets the coordinate of the targets (8,5),(6,3)(9,3) and (9,5) -- Technology Parameters wire unit resistance is and wire unit capacitance is buffer resistance is 180, buffer capacitance is 23.4 and buffer delay is not used in this project(another type of buffer) * TEST RESULT If you run "make test", the test txt result file are put into.testrslt directory. One example txt result is: This is a tree representation of bufferinsertion positions. The digit in the graph is the index of the grid graph nodes. See source code for idx and node coordinates mappings. It would be better to use matlab to view the test result by open and run those out.m files also in this.testrslt directory. Also see project report for mablab figures printouts. * SOURCE LIST AdjcGraph.cpp -- Graph Data Structure Class(linked-list presentation) - 8 -

9 AdjcGraph.h BufferCombTable.cpp -- Table for Buffer Combination BufferCombTable.h PTildeTable.cpp -- Table for Buffered shortest path PTildeTable.h WirePathTable.cpp -- Table for Wire path WirePathTable.h RTBW.cpp -- Algorithm for Single-source-multitargets Buffer Insertion RTBW.h bufferinsertionmain.cpp -- main file gridgraph.cpp -- Input and output Processing Class Gridgraph.h makefile maze.cpp -- Maze Router maze.h readme -- This file. release-notes -- Some notes on development report -- Implementation draft stack_y.cpp -- Stack data structrure stack_y.h CVS -- local CVS management info (ignore them) WirePath.h -- some definitions -- The following utilities are use for calculating the graph node index, manupilating graph things, etc. Bipart.cpp Bipart.h Comb.cpp Comb.h TestBipart.cpp TestUtil.cpp Util.cpp Util.h * KNOWN PROBLEMS We did extensive tests on our programs, and found nothing wrong with finding buffer positions. For example, we tested up to 7 targets in a testbech, the program found all buffers correctly. But due to the high complexity of the algorithm, we couldn't guarantee the correctness of the program. We expect more testbenches and appriciate any feedbacks. The future improvement may be made in the final stage of the algorithm. It would be better to use Steiner-tree algorithm (with obstacles) to get the final routing tree. Currently we use maze router to implement this due to very limited time. In some cases, result may produce some unexpected routing schemes