Architectures for Computer Vision

Transcription

1 1 / 18 from Algorithm to Chip with Verilog Hong Jeong c 2014 John Wiley & Sons Singapore Pte Ltd. Published 2014 by John Wiley & Sons Singapore Pte Ltd. March 13, 2015

2 2 / 18 Part 1 Verilog HDL Chapter 1 Introduction

3 Computer Architectures for Vision 3 / 18 Contents Computer Architectures for Vision Algorithms for Computer Vision Computing Devices for Vision Design Flow for Vision Architectures

4 Computer Architectures for Vision 4 / 18 Flynn Johnson Taxonomy Data Stream(s) Single Multiple SISD SIMD Instruction Stream(s) Single Multiple MISD GMSV GMMP MIMD DMSV DMMP Distributed Global Memory Shared variables Message passing Communication/Synchronization

5 Computer Architectures for Vision 5 / 18 SISD { Q k+1 = T(Q k,d k,i k ), O k = H(Q k,d k,i k ), k = 0,1,2,... (1) Q: state, D: data, I: instruction

6 Computer Architectures for Vision 6 / 18 SIMD { Q l k+1 = T(Ql k,dl k,i k), O l k = H(Ql k,dl k,i k), l [0,N 1], (2) Q: state, D: data, I: instruction

7 Computer Architectures for Vision 7 / 18 MISD { Q l k+1 = Tl (Q l k,ol 1 k,i l k ), O l k = Hl (Q l k,ol 1 k,i l k ), l [0,N 1], (3) Q: state, D: data, I: instruction

8 Computer Architectures for Vision 8 / 18 MIMD { Q l k+1 = Tl (Q l k,dl k,il k ), O l k = Hl (Q l k,dl k,il k ), l [0,N 1]. (4) Q: state, D: data, I: instruction

9 Computer Architectures for Vision 9 / 18 MIMD 2 { Q l k+1 = Tl (Q l k,dl k,il k,ml k,ml k ), O l k = Hl (Q l k,dl k,il k,ml k,ml k ), l [0,N 1]. (5) Q: state, D: data, I: instruction, M: memory, m: message

10 Computer Architectures for Vision 10 / 18 Parallel Iterative Neighborhood Computation { Q (k+1) (A p ) = T(Q (k) (N(A p )),I(A p )), k = 0,1,...,K 1, O(A p ) = Q (K 1) (A p ), p P, (6) A: window, k: iteration, N: neighborhood

11 Algorithms for Computer Vision 11 / 18 Contents Computer Architectures for Vision Algorithms for Computer Vision Computing Devices for Vision Design Flow for Vision Architectures

12 Algorithms for Computer Vision 12 / 18 Technology Performance Parallelism Time Flexibility Exhaustive Search Ultimate goal No NP-hard General Gauss Seidel Low Serial Fast General Jacobi Low Parallel Fast General Relaxation Medium Parallel Medium General DP Good Parallel Fast 1D problem SA Goog No Slow General BP Near best Parallel Slow General GC Best Serial Slow General Table: Comparison of major vision algorithms. cf. DP: dynamic programming, SA: simulated annealing, BP: belief propagation, and GC: graph cuts.

13 Computing Devices for Vision 13 / 18 Contents Computer Architectures for Vision Algorithms for Computer Vision Computing Devices for Vision Design Flow for Vision Architectures

14 Computing Devices for Vision 14 / 18 Technology Performance/ Cost Time running until Speed Flexibility ASIC Very High Very long Very high No FPGA Medium Long High Low GPU High Medium High Medium DSP High Medium medium High EP Low Short Low High Generic CPU Low- Medium Very short Very low Very high Table: Comparison of major devices. cf. EP: Embedded Processor.

15 Design Flow for Vision Architectures 15 / 18 Contents Computer Architectures for Vision Algorithms for Computer Vision Computing Devices for Vision Design Flow for Vision Architectures

16 Design Flow for Vision Architectures 16 / 18 Vision Vision problem Algorithm design Vision architecture Architecture design Architecture algorithm Chip design HDL coding Simulation, function verification Gate/Transistor-level design Simulation, timing verification Implementation (Board, FPGA, ASICs Prototype testing HDL Coding Synthesis Implementation Figure: Design flow from vision to chip.

17 Design Flow for Vision Architectures 17 / 18 FPGA Design 1. Define a new project and enter the design using VHDL or Verilog HDL languages. The design can also be entered using schematic diagrams that can be translated to any HDL. 2. Compile and simulate the design. Find and fix timing violations. Obtain power consumption estimates and perform the synthesis. 3. Download the design to the FPGA using either a parallel port or a USB cable. Designs can also be downloaded via the Internet to a target device.

18 Design Flow for Vision Architectures 18 / 18 Design and Coding for Vision System Architecture design: Given an algorithm, analyze the computational structures in terms of data structures memory, queue, stack, and processing and express them in a hardware algorithm. HDL coding: Code the algorithm in HDL and test. cf. Design tools: Altera Quartus and Xilinx ISE/Vivado