100M Gate Designs in FPGAs

Transcription

1 100M Gate Designs in FPGAs Fact or Fiction? NMI FPGA Network 11 th October 2016 Jonathan Meadowcroft, Cadence Design Systems

2 Why in the world, would I do that? ASIC replacement? Probably not! Cost prohibitive Low power or lack thereof Too much unnecessary stuff Prototyping? That makes sense! Initial systems and/or proof of concept (e.g. base stations) Pre-silicon chip (ASIC) verification Early embedded software & firmware development HW/SW integration and bring-up Let s have a closer look Cadence Design Systems, Inc. for NMI FPGA Network

3 System Design Challenges Bridging the hardware-software convergence gap Time-to-market Development cost reduction Multi-core design and verification complexity Integration of new designs and derivatives Software stack development Hardware-software convergence Cadence Design Systems, Inc. for NMI FPGA Network

4 It s all about the software Software dominates development cost and schedules Software is a necessity to successfully sell silicon Delay of software delivery delays time to revenue Source: IBS Starting software development as early as possible is crucial Source: IBS Cadence Design Systems, Inc. for NMI FPGA Network

5 Until you need some hardware! Connecting to the real world A complete environment that applies real-world stimulus Provide a physical interface allowing to quickly integrate with external systems, networks, and/or test equipment Allowing design teams to validate the design with real-world applications such as booting the operating system, transferring files, and displaying graphics /video System environment Real-world interfaces (real-time speed) USB / SATA / SAS 4G/ LTE Analyzer / Tester Pre-silicon RTL model Protium Ethernet Tester Live Network PCI Express Video/Audio Cadence Design Systems, Inc. for NMI FPGA Network

6 Using the right tool, at the right time Key to success Hardware Debugging Software Development and System Validation 100% Workload Design Creation 0% RTL Ready Tapeout Test Chip Cadence Design Systems, Inc. for NMI FPGA Network

7 Keys for success, and fast prototype bring-up No FPGA -specific design/rtl modifications needed Handling of any clocking structure and any number of clocks Automatic memory compilation & modeling Fully automatic, multi-fpga partitioning Optional, manual guidance for performance optimization Pre FPGA P&R model validation Multiple design integrations per day Avoids time consuming FPGA P&R runs Fully integrated FPGA P&R Automatic constraint generation Guaranteed P&R success Cadence Design Systems, Inc. for NMI FPGA Network

8 Cadence multi-fabric compile flow Months Days Traditional FPGA Prototype Flow ASIC RTL (Verilog / VHDL / SV) Debug probes and trigger conditions 1-2 days per iteration Fast prototype bring-up Golden pre-partition model Post-partition verification model All Palladium debug features Verification model to validate FPGA functionality 1-2h per iteration Integrated Compile Engine Memory compiler Board file HDL-ICE for fast compile Partitioning Board router FPGA P&R FPGA bit files Debug inserter Manual partition directives 60M Gates/Hour Functional assurance before P&R Multiple Iterations Optional Independent re-run of selected tests for debug Waveforms of probes Cadence Design Systems, Inc. for NMI FPGA Network

9 Advanced clocking any type; any number Traditional imitations: Gated clock, multiplexed clocks # of clocks Difficult to achieve FPGA timing closure Long iteration times / long FPGA P&R times Unpredictable results & prototype behavior Protium benefits: No hold-time violations in user clock domains Removes any FPGA-specific clock limitations Supports unlimited # of design clocks Improves FPGA timing closure Accelerates FPGA P&R times Cadence Design Systems, Inc. for NMI FPGA Network

10 Comprehensive, automated memory support The conversion and implementation of memories is one of the most challenging and time-consuming steps in the bring-up of an FPGA-based prototype system, often taking many weeks to complete Type Size Upload/ download Comments FPGA-internal ~50Mbits/FPGA Yes Fully automatic compile XSRAM (automated small external memory) XDRAM (automated bulk memory) DCMC (Direct connected memory card) 128 Mbytes per memory card 16 GBytes per XDRAM card x GBytes (depending on memories used) Yes Yes No Fully automatic compile Extends FPGA-internal memory to external SRAM Useful for SPI-flash and other small memories (e.g. boot ROM) semi automatic compile Leverages XDRAM hardware Support for DDR3/4, LPDDR3/4 Design change may be required, depending on memory type App notes available The memory compile capabilities in the Protium platform are comprehensive and easy to use: Smaller memories are fully automatically compiled into FPGA-internal memory resources For larger, off-fpga memories, Protium platform offers several solutions; which one to use depends on specific requirements and objectives FCMC (Full-custom memory card) custom No Full custom development Cadence Design Systems, Inc. for NMI FPGA Network

11 Automatic, multi-fpga partitioning - adjustable performance Unique to Protium Fully automatic: Clock-tree transformation ASIC memory mapping Partitioning FPGA P&R Black-boxing: Single FPGA scope FPGA-specific optimization Direct clock mapping Directly connected bulk memories FPGA P&R options and constraints Manual guidance: Partitioning input Directly connected bulk memories FPGA P&R options and constraints Logic replication Clock-tree simplification ASIC RTL (Verilog / VHDL / SV) Memory compiler Board file Integrated Compile Engine HDL-ICE for fast compile Partitioning Board router FPGA P&R FPGA bit files Debug probes and trigger conditions Debug inserter Manual partition directives Blackbox RTL Vivado FPGA Synthesis FPGA Netlist Cadence Design Systems, Inc. for NMI FPGA Network

12 Enhancing FW/SW debug The basics JTAG debugger interface UART interface Fast system configuration What really makes a difference Backdoor memory access to quickly change boot code, software, etc. Clock control to start/stop the clock on demand Fully scriptable runtime environment Remote access prototype system is a network resource, accessible anytime from anywhere High-performance link to software model Cadence Design Systems, Inc. for NMI FPGA Network

13 Debug in Protium Unique to Protium Waveforms across partitions Provides a design-centric view rather than an FPGA-centric view Force/release signal Forces predefined signals (at compile time) into 0 or 1 during runtime Memory upload and download Monitor signal Real-time monitoring of predefined (at compile time) signals Runtime Start/stop clock capability (run N cycles) Probes Runtime data capture of predefined signals for offline waveform viewing Cadence Design Systems, Inc. for NMI FPGA Network

14 Accelerating HW/SW Development & Debug C/C++ models & test benches FPGA Prototyping CPU MEM GPU IP CPU MEM GPU IP TLM Fabric Fabric IP IP IP IP IP IP IP IP Abstract HW Models SW Execution: Up to 100MHz Debug: Full HW/SW SW: Full-Featured HW/SW: Concurrent CPU TLM Fabric Co-Prototyping MEM GPU IP RTL Fabric Cycle-accurate HW Models SW Execution: Up to 50MHz Debug SW: JTAG HW/SW: Independent SCE-MI IP IP IP IP Model Accuracy CPU Sub-System: Instruction-accurate Rest of system: cycle-accurate Key : TLM Bridge RTL SW Execution: 4-40MHz (SW application dependent) Debug SW: Full-Featured HW/SW: Concurrent Cadence Design Systems, Inc. for NMI FPGA Network

15 Protium transaction interface Enabling co-prototyping Host Protium Transactors: Chip Models Software Transactors SCE-MI 2.1 Transaction Interface Chip Designs Hardware Transactors TLM 2.0 ó Bit-level Get/Put Signal-level Snd/Rcv ( sideband ) AXI 4 Master/Slave AXI 4-Lite Master/Slave AXI 3 Master/Slave AHB Master/Slave APB Slave Applications/Uses: Connect from SystemC/C++ to RTL running in Protium Leverage 100% hardware accurate RTL with your system modeling environment Automatically build complete, custom-configured HW-to-SW transactor links over SCE-MI Custom build your own transactors using high-performance, low-latency SCE-MI 2.1 API Cadence Design Systems, Inc. for NMI FPGA Network

16 Example H.264 decoding Host Protium Compressed video H.264/VP8 FILE NAL unwrap Parse + CAVLC Inverse Quant Transformation Display Transactor Transactor Interface (AXI over SCE-MI) Uncompressed video Intra Prediction Inter Prediction Ref Frames Deblock Filter Scale / YUV2RGB Frames/sec Bandwidth (MBps) Width (pixels) Height (pixels) Silver Surfer Epic Cadence Design Systems, Inc. for NMI FPGA Network

17 UD Module Looking beyond ASIC prototyping Prototyping FPGA designs in FPGAs Benefits: Advanced debug capabilities Verification/validation platform available in days Avoid all those time consuming timing closure trial & error runs (we all know how long FPGA P&R times can be) Early software development platform available in days Applying prototyping techniques to FPGA design Benefits: Faster time to market Shorter development times lower development costs Higher product quality Example: Memory modeling with XDRAM NM B Protium FPGA X DUT DDRn Controller Upload/Download DINAR XDRAM Board DDRn I/f Logic K7 DDR3 Ctrl S O D I M M Cadence Design Systems, Inc. for NMI FPGA Network

18 Summary 25M gate FPGAs are here today 100M gate FPGAs will be here in just a few years! These high-capacity FPGAs are not for everybody Requiring ASIC design techniques & tools Main use model is for prototyping & emulation Cadence Design Systems, Inc. for NMI FPGA Network

19 Cadence Design Systems, Inc. for NMI FPGA Network

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