2. Learn how to use Bus Functional Models (BFM) and write test cases for verifying your design.

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1 Verifying your IP Objective The purpose of this tutorial is to guide a user through the simulation and verification framework available in quartus. By the end of this tutorial you will be able to : 1. Setup and run Modelsim for your quartus project. 2. Learn how to use Bus Functional Models (BFM) and write test cases for verifying your design. Introduction Functional verification is a key design effort for any chip design endeavor. This is all the more important if you are creating a component that hooks on to the system interconnect bus (Avalon in this case) since your IP also needs to be compliant with the bus protocol. The system integration tool in Quartus - Qsys provides a drag and drop feature to create a system where IPs compliant with the bus protocol can just be dropped on the bus and connected to other components on the bus. Hence, to create a memory mapped component which can act both as a bus master and/or a bus slave all one needs to ensure is that it adheres to the bus protocol. This can ofcourse then also be extended to include streaming and interrupt interfaces (Refer [1] to learn more about other kinds of Avalon bus components ). To ease this verification effort, Altera provides a set of BFMs (Bus Functional Models) for a generic bus masters, slaves and other types of bus IPs that can be plugged in your design to verify your IP. Thus without even connecting your IP to other components and verifying the entire system a designer can focus on the functional integrity of his own IP by just hooking up the respective BFMs. This can be done independent of other designers while ensuring quality of the IP. The available BFM IPs are categorized as the Avalon Verification IP Suite and are available in the "Verification->Simulation" Category in Qsys. Using the BFMs provided may require a learning curve if you are not familiar with using them before, however the effort is worthwhile and will ensure that that the design is fully verified before prototyping the application on the FPGA. In short using the BFMs will : 1. Provide a realistic model of an Avalon Master, Slave or a streaming Qsys module that you may need to interface to. Thus without even completely understanding the specifics of an IP you can assure a successful design by rigorous verification using the BFMs. 2. Make you understand how extensive verification is done in a real chip design project. It will also give you a more in depth usage of System Verilog which is a skill much appreciated and required in the industry. This short tutorial serves as an introductory guide to using the BFMs and how you can setup your quartus project to use the BFMs correctly. A more extensive guide is available from Altera [1]. Qsys Setup for using the Verification IPs. In this section we will look at the setup and the available IPs required to use the BFMs to verify your design. Let's say your IP is called custom_module as shown in Figure 1 and you intend to verify this IP. The custom_module has both an Avalon master and a Avalon Slave interface as can be seen in Figure 1 below. We need two verification IPs namely an Avalon MM Slave BFM and an Avalon MM Master BFM to simulate the behaviour of this module as a slave and a master. 1. Connect the avalon_slave interface of custom_module to m0 - the Avalon Master Interface of the Master BFM 2. Connect the avalon_master interface of custom_module to s0 - the Avalon Slave interface of the Slave BFM. The BFM Verfication IPs are available in the Verification->Simulation category as shown in Figure 2 below.

2 Figure 1 : Connecting the Verification IPs to a custom_module Figure 2 : Instantiating the Verification IPs in Qsys. Once you have made the appropriate connections as described above go to the Generation tab in Qsys. 1. In the Simulation section enable Verilog as the simulation option as shown below

3 Figure 3 : Enable Verilog as the simulation. 2. In the Testbench Section enable the Standard option for the testbench Qsys system and Verilog as the simulation model as shown in figure below. Figure 4 : Enable the standard option for the testbench Qsys system. Ensure that the paths for the Simulation, Testbench and Synthesis are correctly populated. Your Generation Tab should now look like the figure below. Assuming you have no errors in the Qsys interconnections, Hit "Generate" to extract the design files for the IPs used and the Qsys interconnect files. Setting up Modelsim Follow these steps below to setup modelsim inside Quartus : Figure 5: Check for errors. 1. Go to Tools->Options in the Menu Bar. In the Options Dialogue box go to EDA Tool Options. Provide the path for the modelsim binaries for Modelsim. Ensure that the Modelsim-Altera field is blank. Your Options Dialogue box should look like this. To know the Modelsim installation path type "which vsim" on a terminal.

4 NOTE : If you wish to use any other Simulation tool provide the path to the binary for that tool. This tutorial looks at just Modelsim. 2. To tell Quartus which tool to use for Simulation; Go to Assignments->Settings on the menu bar. Go to EDA Tool Settings in the Settings Dialogue box. Select Modelsim as the Tool name and set up this page as shown in figure below. Feel free to explore more simulation options including the NativeLink Tool. 3. To run Modelsim. Go to Tools->Run Simulation Tool-> RTL Simulation. You will now enter the familiar world of Modelsim! 4. Modelsim will now start and load up its initial configuration script which will compile the libraries needed for this project. You may see some errors at this point. These errors have been carefully looked into and have been found to be benign for further use. So if the errors look like the following figure then move to the next step. If you see additional errors related to your design fix them.

5 5. Now, open the file "run_simulation.tcl" provided to you in the project top directory. This is the file that we will use to setup the project top level, compile and elaborate the design. Ensure that the following variables accurately represent your design in the script. system_name <Name of the Qsys subsystem> TOP_LEVEL_NAME <Name of the testbench to be run> After the line that reads "#compile testbench and test program", list the design files you wish to compile. This includes all relevant verilog modules outside the Qsys subsystem and relevant test programs. The sample file provided to you has an example of how to do this for the demo project. 6. After making these changes run the.tcl script in modelsim by issuing the following command. Ensure that your current working directory contains the file run_simulation.tcl do run_simulation.tcl Ensure that the tcl script is located in your current working directory in modelsim. You have now successfully setup the verification environment for simulating and verifying your design. The next section deals with the basics of how to write a test program in system verilog including writing SV assertions, transactions and other aspects of verification.