CHAPTER 1 INTRODUCTION. equipment. Almost every digital appliance, like computer, camera, music player or

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1 1 CHAPTER 1 INTRODUCTION 1.1. Overview In the modern time, integrated circuit (chip) is widely applied in the electronic equipment. Almost every digital appliance, like computer, camera, music player or mobile phone, has one or several chips on its circuit board. Very Large Scale Integration (VLSI), in general, comprises over an excess of one million transistors, an incredible figure that could not have been imagined a decade ago. Though the complexity of the chip has compounded by a factor of 1000 since its first introduction, yet the term VLSI still remains to be accepted and denotes digital integrated systems with high complexity. Further, past few decades have witnessed an extraordinary increase in VLSI research. The Computer-Aided Design (CAD) has further aided the growth in the complexity and performance of integrated circuits in the VLSI technology. With such a phenomenal increase in complexity, it is more crucial than ever before to manage the design process, in order to maintain the reliability, quality, and extensibility of a given design. The process includes definition, execution and control of design methodologies in a flexible and configurable way [1], [2]. Speed of development in high-performance computing, telecommunications and consumer electronics in a rapidly changing market, developmental costs, and cost involved in case of mistakes, play a critical role in a commercial environment [3]. Hence, it requires designs that can be processed quickly, cheaply and mistakes brought to the forefront at the earliest, perhaps, before fabrication stage.

2 2 VLSI is preferred due to its many advantages: compactness, less area, physically smaller; higher speed, lower parasitic (reduced interconnection length); lower power consumption; and higher reliability, improved on-chip interconnects. In addition, VLSI integration significantly reduces manufacturing cost. Nevertheless, a few disadvantages, such as long design and fabrication time and higher risk to project with complexity of millions of components leads to the anticipation of fast computation and layouts close to optimality generation. The research and development of circuit layout (Physical Design) automation tools could pave a way for future growth of VLSI systems. The accepted norm about the layout of integrated circuits on chips and boards is that it is a complex process. Consequently, any problem arising as a result of optimization problems requires to be solved during the circuit layout, which is intractable [4], [5]. This refers to the fact that they are mostly Nondeterministic Polynomial (NP) - hard [6]. The major implication of this recourse is that the optimal solutions cannot be achieved in polynomial time VLSI Design Cycle The VLSI design pertains to design of a single integrated circuit to execute a complex digital function. Typically, the design process is an iterative process that fine-tunes an idea for a device which can be manufactured through various levels of design abstraction [7]. The process is elaborate and involves a series of steps that includes specification to fabrication, in which the integrated circuit is produced. Beginning with abstract requirements, the process involves converting these requirements into a register transfer description, e.g., control flow, registers and arithmetic and logical operations, which is simulated and tested. It is then moved to circuit representation involving gates, transistors

3 3 and interconnections. At this juncture, simulation is used to verify each component. Ultimately, the geometric layout of the chip is produced as geometric shapes typifying circuit elements and their interconnections. The blueprint of the layout, thus, intends to achieve area compactness and accuracy in routing and timing [8], [9]. The distinctive steps involved in VLSI design cycle are illustrated in Figure 1.1. These steps are system specification, functional design, logic design, circuit design, physical design, fabrication and testing. System Specification Behavioral Description High Level Synthesis Logic Synthesis Physical Design Fabrication / Testing Figure 1.1: VLSI design flow System specifications Design specifications are required to lay down the rules for the design. While working on the design, the main factors to be considered in this process include physical dimensions

4 4 (size of the chip), performance, functionality, choice of fabrication technology and design techniques [10]. The expected end results of the whole process are the specifications for the speed, size, functionality and power of the VLSI circuit Behavioral Description Behavioral description is then created to analyze the design in terms of functionality, performance, compliance to given standards, and other specifications. The outcome of this step is usually timing diagram or other relationships between sub-units. This phase is to improve the overall design process and reduce the complexity of the subsequent phases [11] High Level Synthesis Logic design step transforms the behavioral specification into a register transfer level (RTL) description that includes the word widths, control flow, register allocation, logic and arithmetic operations. Further, the functional units are expressed as primitive logic operations (NAND, NOT, etc.). This description can be represented in the form of a Hardware Description Language (HDL), namely Verilog and VHDL. The main objective of this step is to minimize the number of Boolean expressions Logic Synthesis Logic synthesis is a process by which an abstract form of desired circuit behavior. A technology-dependent description of the circuit is created, which transforms the logic expressions into a circuit representation with components, such as cells, macros, gates, transistors, and interconnections collected in a netlist. During implementation of some topologies, logic equations are broken down and mapped to available physical circuit

5 5 blocks in the circuit topology [12]. The correctness and timing of each component are verified by the logic synthesis Physical design Physical design is a step in the standard design cycle which follows after the circuit design. At this step, circuit representations of the components (devices and interconnects) of the design are converted into geometric representations of shapes which, when manufactured in the corresponding layers of materials, will ensure the required functioning of the components. This geometric representation is called integrated circuit layout. The final performance of the circuit is assessed through a compact arrangement of the area and accurate routing of wires [11]. Being an NP-hard problem, the physical design is further broken down into a number of sub-problems, which is denoted as partitioning, placement and routing. The focus of this research is to study the partitioning and placement [12] Fabrication and testing At last, the wafer is manufactured and diced in a fabrication facility. In order to ensure that the chips meet all the design and functional requirements, each chip is packaged and tested. Nevertheless, the success of the entire process strongly depends on the correlation between abstract models at the higher level and physical implementation at the lower level.

6 Physical Design Cycle The logic synthesis and circuit design results in the circuit components, which are extracted from a physical library and converted into rectangular shapes with fixed dimensions. The circuit components are called as cells or modules and the interconnections as nets which are collected as a netlist. The timing constraints on signal propagation paths along nets are defined. A complete layout of the circuit, where all the cells are positioned on the chip without overlapping and all the interconnection paths completed, is the output of the physical design stage. This layout is achieved in multiple stages: partitioning, floorplanning, placement, routing and compaction [13]. Figure 1.2 illustrates the stages of circuit layout. Circuit Design Partitioning Floorplanning Placement Routing Fabrication Figure 1.2: Design process steps of circuit layout Partitioning The engineering change orders can be handled by an effective and efficient partitioning tool by tremendously reducing the complexity of the design process [14], [15]. Besides,

7 7 final product with respect to production cost and system performance is evaluated based on the quality of the partitioning [16]. Partitioning is a technique to divide a circuit or system into a collection of smaller components. It is a design task that breaks a large system into smaller pieces to be implemented on separate interacting components. While at the same time, it also acts as an algorithmic method to solve difficult and complex combinatorial optimization problems as in logic [17]. The size of VLSI designs has increased to systems of hundreds of millions of transistors. The complexity of the circuit has become so high that it is very difficult to design and simulate the whole system without decomposing it into sets of smaller sub-systems. As a result, the circuits are partitioned by grouping the components into blocks also known as sub-circuits or modules. However, the actual partitioning process is based on factors like number of blocks, the size of the blocks, and the number of interconnections between the blocks [18]. The output of partitioning is a set of blocks along with the interconnections required by blocks, which are referred to as a netlist Floorplanning Floorplanning is the process of identifying structures that should be placed close together, and allocating space for them in such a manner as to meet the sometimes conflicting goals of available space (cost of the chip), required performance, and the desire to have everything close to everything else. Floorplanning includes finding the alignment and relative orientation of the modules so that the total device area is minimized. The placement of the modules is done on the basis that strongly connected components come

8 8 closer to each other. After floorplanning, the routing region must be divided into channels and switchboxes Placement A crucial task in chip design is placement which requires the positions of the modules to be decided on a given chip area. The placement has a greater influence on the total length of wires required to interconnect them, and as a result on the performance of the chip, the signal transition times and the consumption of power. Meeting time constraints were not a difficult task in the past, but in modern times due to technological advancement and growing complexity, the chip design has become a complex and time consuming process [19]. In addition, interdependent optimization goals and tight constraints will have to be addressed. Hence, the placement requirements keep changing, as placement tools became a fundamental component in integrated design flows at a number of stages and scenarios. Due to its iterative nature, placement has made the overall turnaround time greatly sensitive to the runtime of the placement. The varied reasons justify the need for flexible yet powerful and fast placement algorithms which is critical for faster turnaround and least time to market [20]. To sum up, the main objective of the placement is to find a minimum area arrangement of the blocks that allows completion of interconnections between the blocks. Two phases are included in standard cell placement. The first phase includes the creation of initial placement. The second phase includes assessment of the initial placement followed by improvement on the iteration till the layout contains minimum area and follows the design specifications [18]. In order to permit interconnections, space is left blank between the blocks. During placement, an estimated amount of routing space is added between the

9 9 cells. In one of the previous works of the author, it has been shown that estimating the space is crucial, as too much space can lead to sub-optimal layouts or too little space might rule out the optimal (shortest) routes for all nets, similarly the completion of the interconnections can also become impossible [21]. In such an instance, a rearrangement of the cells becomes necessary. Therefore, it is wise to integrate the computation of the routes into the placement task. However, the quality of the placement cannot be evaluated until the routing phase is completed. Another case of placement may be carried out if routable design is not achieved due to time constraint. Further, the effort is made to decrease the number of iterations by estimating the required routing space because when the positions of the blocks are fixed, it is not easy to improve the routing as well as the overall performance of the circuit [19]. Thus, it is evident that the efficient placement algorithm is essential for a good routing and circuit performance Routing Routing is considered to be one of the most complicated steps in the back-end design process. It refers to finding suitable paths within the available layout space where the wires are connected to the desired set of pins. It seeks to minimize total wire length but with respect to track capacity constraints. The main goal of this phase is to ensure that the interconnections are completed between the blocks as per the specified netlists in semi custom design [22]. When free spaces are unoccupied, they are partitioned into channels and switchboxes, which are used to complete all circuit interconnections through the shortest possible wire length. Routing takes a two-stage method: global routing and detailed routing [23]. Global routing connects the blocks of the circuit without taking into

10 10 account the exact geometric details of each wire and pin. Global routing specifies the loose route" of a wire through different regions in the routing space. Detailed routing assigns actual tracks and vias for nets. The two distinct problems that arise due to these routing is to balance the densities of the routing channels and to assign specific wire segments to each connection [24]. The objectives of the global routing algorithm are to distribute the connections among the channels to ensure that the channel densities are balanced and to reduce the number of turns for each connection. The main drawback of two-stage process of routing, i.e., global and detailed routing, is that it does not provide appropriate opportunities to tackle problems which arise from signal delay, cross talk and process constraints. Batterywala, et al. [25] put forward an intermediate step of track assignment between global and detailed routing to address these problems. During this stage, the global routing information can be used to efficiently address these problems and to support the detailed router in achieving the wiring completions Research Rationale Over the past 40 years, the number of transistors in an integrated circuit has doubled roughly every two years. This trend, known as Moores s Law, his prediction has proven to be accurate, in part because the law is now used in the semiconductor industry to guide long-term planning and to set targets for research and development. The VLSI industry has seen a steady growth of device capacity along with Moore s Law, to the point that today multiple processors are implemented on a single chip. This has enabled the industry to expand its market to new territories previously impossible, such as high-performance computing. Despite the exciting development, the growth of device capacity and the

11 11 expansion of a new user population place new challenges on CAD software for VLSI design. It is, therefore, important to reconsider the key CAD algorithms developed and used successfully in the past, with the first class requirement of scalability. This problem is particularly challenging because scalability has to be achieved across the entire flow, without much sacrifice of quality of result. Due to the large number of components, the task of designing integrated circuits is complex, which gives rise to the hypergraph partitioning problem. This problem, especially, occurs when dividing a circuit specification into clusters of netlist (sub-circuits) to minimize the cluster interconnect. Each sub-circuit can then be assembled independently, speeding up the design and integration processes. A circuit specification includes cells, which are pre-designed integrated circuit modules that implement a specific function and have input and output terminals. A net is a collection of input and output terminals connected together and is used to connect a group of cells together. Each connection between a cell and a net occurs at a pin. Cell connectivity information for the entire circuit is provided by the netlist, which specifies all the nets for a given circuit. Cell connectivity information from the circuit is represented by hypergraph. The hypergraph comprises vertex and hyperedge. While graph edges are pairs of nodes, hyper edges that connect any number of nodes and can therefore contain an arbitrary number of nodes. The vertex represents a cell in the circuit, while hyperedge the net from the netlist of circuit. The physical size of the cells and signal delays in the nets are evaluated from the vertices and hyperedges, respectively. The circuit specification is said to satisfy the

12 12 hypergraph representation if each net in the circuit has at least one pin on any one cell. Hypergraph application has been used for very long in the VLSI design process [26]. The constructive and iterative improvement placement methods are used for placement. In constructive placement method, once the coordinated of a cell have been fixed they are not modified any more. In iterative placement method, all cells have already some coordinates and cells are moved around, their positions are interchanged. Despite producing high quality placement, certain iterative improvement methods require excessive computation time. In contrast, the constructive placement method does not yield high quality placement but takes much shorter time. The performance of the circuit depends on both the quality of the placement as well as the shorter time. Therefore, there is a need to produce an efficient placement solution which can address these two challenges as design procedures takes weeks, months or even years to realize larger circuits. The fact that future placement and routing tasks will be much more complicated (due to the increasing size of the circuits and the growing design objectives) implies that faster placement and routing tools should be developed to handle such immense complexity. Future placement and routing tools must be adequately flexible to handle any modifications in VLSI design styles and design objectives. An effective, efficient, flexible and robust is required overall to address these complexities. The following gaps have been identified and will be addressed by this research study: The growth of device capacity and the expansion of a new user population have resulted in new challenges on CAD software for VLSI design.

13 13 A need to achieve scalability across the entire flow through CAD software for VLSI, without much sacrifice on the quality of the result. A need to produce an efficient placement solution which can address high quality placement within a shorter time. Faster placement and routing tools are required to handle complicated tasks. They should be flexible and robust to handle any modifications in VLSI design styles and design objectives. Unimodular hypergraph partitioning within the VLSI design has not been studied by others because even cardinality hyperedges are perfectly balanced, whereas odd ones have a deviation of exactly one but in hypergraph whose edges are not balanced. Hence, it will be a major contribution of this study Aim and Objectives of the Research The aim of this study is to develop and examine new methods and strategies, which are robust and flexible, as well as effective and efficient, to perform the partitioning and placement tasks. The main objectives of this study are To introduce a special type of hypergraph, namely unimodular hypergraph To address the various clustering methods are used to obtain effective VLSI circuit partitioning. To investigate an alternative method, namely Markov Renewal Reward process for VLSI circuit partitioning, which is a stochastic process under continuous time and discrete values

14 14 To address circuit placement challenges through Utility theory 1.6. Thesis Outline The remaining chapters of this thesis are organized as follows: Chapter 2 This chapter introduces the definitions of a hypergraph and the hypergraph partitioning problem. Unimodular hypergraph is defined as a stochastic function and proposed an alternative approach to netlists with the help of transition probability matrices. Further, this chapter explains the qualification of hypergraph K and G to be unimodular hypergraphs. The use of unimodular hypergraph to obtain the maximum flow at a particular node and to minimize the time between two nodes is also proposed. Chapter 3 This chapter highlights the clustering methods: Two-Step clustering, Hierarchical clustering and K-medoids clustering. In the two-step clustering method, pre-clustering and clustering with an optional step of outlier handling between the two was used. In the hierarchical method, agglomerative and divisive clusterings were performed. In the K- medoids method, a step approach was attempted. The clustering algorithms were compared based on the factors, such as the size of the data set and run time. For each of the factors, four tests were conducted with one test for each algorithm. The results showed that K-medoids method overcame VLSI partitioning problem by using medoids to represent the cluster rather than centroid. The K-medoid model achieves greater performance in comparison with other clustering method. The results pertaining to these methods are given in detail.

15 15 Chapter 4 In this chapter, the benefits of Markov chain model are described in detail. Markov renewal reward process is an extremely useful tool for efficient cell partitioning; therefore, an investigation of this approach was conducted. While analyzing the Markov Renewal Reward method for VLSI circuit partitioning, an attempt was made to investigate the probability distribution of the accumulated reward in a Markov renewal process and to obtain the accumulated reward that is directly influenced by random process that can be modeled by continuous-time Markov chain. In doing so, two novel approaches were employed. These approaches along with the strategies have been described in this chapter. Chapter 5 Chapter 5 discusses the methods used to address the cell placement problem with specific goals and objectives. In this chapter, utility theory was focused as it can be used in both decisions making under risk and uncertainty and also for its effectiveness to select the best moves. Three types of utility curves, such as Conservation Man, Average player and the Gambler have been discussed. Further, the utility theory has been analyzed for its efficiency to solve cell placement problem. Chapter 6 Chapter 6 concludes the findings of the study by providing a summary and an evaluation of the work presented. Finally, scope for future work is provided.