PLACEMENT OF TSVS IN THREE DIMENSIONAL INTEGRATED CIRCUITS (3D IC) College of Engineering, Madurai, India.

Transcription

1 Volume 117 No , ISSN: (printed version); ISSN: (on-line version) url: ijpam.eu PLACEMENT OF TSVS IN THREE DIMENSIONAL INTEGRATED CIRCUITS (3D IC) 1 M.R.Sheeba, 2 D.Gracia Nirmala Rani, 1,2 Electronics and Communication Engineering, Thiagarajar College of Engineering, Madurai, India. Abstract: The main purpose for the Three Dimensional Integrated Chip (3D IC) technology is to increase the performance of the Integrated Circuit. When these IC s are stacked in Three Dimensional structure there will be some multi objective issues like inter layer wire length and congestion. So in order to reduce the inter layer wire length and the congestion in 3D IC, the regular placement of TSVs (Through Silicon Via) is to be done. An evolutionary optimization algorithm is used for the regular placement and assignment of TSVs in 3D IC. At first, the floorplanning of an IC is done by using Cadence. After floorplanning method, the white space is calculated. After the calculation of the white space the location of the TSVs (Through Silicon Via) are obtained. So the TSVs are placed on the white space by the regular placement method. The benchmark ISCAS 85 (International Symposium on Circuits And Systems have taken. Keywords: Three Dimensional Integrated Chip (3D IC), Through Silicon Via (TSV), Inter layer wire length, congestion, Placement. 1. Introduction The main concept of 3 Dimensional Integrated Chip is to obtain the small chip area with high performance. A 3D IC concept is that stacking of multiple dies one above another. The stacking of these dies are done by the different bonding styles. Totally there are three types of bonding styles they are as i) Face to Face bonding (F2F) ii) Back to Back bonding (B2B) iii) Face to Back bonding (F2B). The Face to Face (F2F) bonding does not have any standard process. Wafer thinning is not required for this bonding method. The advantage of the Face to Face bonding is that it requires few TSVs. The disadvantage of this bonding is that, only two dies can be stacked. The connections are provided by the vertical interconnect which occurs in between two face (interconnect) side of the tier. The Back to Back bonding is done by the bonding both back of the two tiers. The main advantage of the Back to Back bonding is that this process of bonding style is easier. The disadvantage is that it requires more TSV s and it allow only one die to be stacked. The connection is done on the back (active) side of the both tiers. The Face to Back (F2B) bonding uses the standard process for assembly, test and packaging. The merits of the Face to Back bonding are that it allows an arbitrary number of dies to be stacked. The demerit is more TSV s are required the connection is made by the vertical interconnects (face) side of one device tier and active (back) side of the other device tier. Bonding is done by the Copper Pillar Micro Bumps. The Larger die is called as the mother die and the smaller die is called as the daughter die. The daughter die is placed over the mother die. Daughter die and its bonded copper column should be thinner than the collapsed flip chip (interconnecting semiconductor) bumps surrounding it. Copper Pillar Micro Bumps have been widely adopted to form these connections because their small size and pitch can provide the required interconnect density. It is used to connect the adjacent dies. After the process of floor planning the whole circuit which contains large logic elements are partitioned. 2. Previous work Placement of Through Silicon Via in the floor planned 3D IC is an issue. The partitioning [1] is done to reduce the temperature and the thermal effects of the IC. While stacking of ICs by tier over tier there raises a problem of more power dissipation. Because of more power dissipation providing coolant for each tier is impossible. So in order to avoid this power dissipation partitioning have been done. The guided simulated annealing method is used [2]. It is used for the 3D floor planning and then it is partitioned. The quadratic algorithm [3] is used to assign the location of the TSVs. The Multi Objective Evolutionary Approach (MOEA) [4] is done based on the genetic algorithm to reduce the wire length of the interconnects. The placement of TSVs [5] is assigned by the Weighted Average (WA) wire length model. The multi objective evolutionary technique [6] is used in order to have the efficient rout ablility. The light weight multi objective dead space optimization methodology [7] is used to optimize the interconnects. The calculation of Keep Out Zone (KOZ) [8] is done. The size of the KOZ varies so 179

2 according to the size of KOZ the TSVs are placed. The floor planning is done [9] to calculate the wire length. The thermal TSVs are inserted in order to improve the vertical heat flow in the floor planned chip. The analysis of thermo mechanical stress and the impact of Keep Out Zone (KOZ) are done. So that the performance is increased and the wire length is reduced. The placement and the design planning [11] for the 3 Dimensional Integrated Circuits have been analyzed. 3. Proposed Algorithm The evolutionary optimization algorithm is proposed in this paper for the regular placement and the assignment of the TSVs in the Three Dimensional Integrated Circuits. The floor planned design of the 3D IC is given as the input. So by calculating the white space in the floor planned design of the 3 Dimensional Integrated Circuits the TSVs are assigned and then those TSVs are placed in the white space. The group of cells in the integrated circuits is known as the chromosomes. The placement and the assignment of TSVs are calculated by the fitness value of the chromosomes. The fitness values of each chromosome are the quality of the solutions of each chromosome. The fitness of the chromosomes is calculated by the floor planned design of the integrated circuits. The Non dominated Sorting Genetic Algorithm (NSGA) [12] is an algorithm used to calculate the white space for the assigning and the placement of Through Silicon Via. There three Multi Objective Genetic Algorithm (MOGA) operators used for the calculation of the fitness of the chromosomes. Those Multi Objective Genetic Algorithm operators are as follows; selection, crossover, mutation and binary tournament. The binary tournament is a kind of selection which is done by the selection of the individuals from the population by using genetic algorithm. 1. Binary tournament selection: The binary tournament selection can be done by two methods; (i) First method is that by calculating the rank of the each chromosomes (i.e. the rank of the cells). The rank of the each chromosome is calculated by the pareto optimal method. It is a method of making the individuals best but without anything worst. By this ranking method the chromosomes which have higher fitness are calculated easily. (ii) Second method is that by calculating the crowding distance of the chromosomes (i.e. the crowd of the cells). The crowding length is calculated by the length of the side of the hyper rectangle of the neighbouring vertices. The crowding distance of the chromosomes is calculated in order to avoid the local minima. chromosomes. These chromosomes are generated by the greedy technique. This greedy technique is a multi step process used to obtain the better result. Therefore some chromosomes are obtained by this greedy technique and the rest of the populations i.e. chromosomes are generated randomly. 3. Mutation: In this process, the probabilities are increased in each generation. So that by increasing the probability in each generation there is also a minute improvement. By this minute improvement the solution becomes more optimized. 4. Crossover: The crossover method is done form one generation to another generation. The probability of the generation in crossover method will not be constant. The higher probability are kept in first generation because to obtain new solutions of the chromosomes. The probabilities are reduced in order to obtain the better convergence. Figure 1. Block diagram of the benchmark circuit c Selection: The selection of the chromosome (TSV) is calculated from the initial population of the 180

3 The above diagram figure one represents the diagram of the benchmark circuit of c3540. This benchmark is an eight bit ALU which will perform binary and BCD arithmetic operations moreover as logic and shift operations. Logic operations square measure intermixed with arithmetic ones, very much like within the TTL BCD addition is finished via a two's complement adder by adding via to each digits of the primary quantity, and so subtracting via from the digits of the result if they are doing not generate a carry. Complete of fourteen management inputs square measure used for multiplexing and masking knowledge inputs. Most multiplexers during this circuit have an odd range of inputs, e.g. 3 and 5, and their choice is completely different between lower and higher digits (4 bits). The choice mechanism of M4 (output MB) is even a lot of difficult. The most important module is M5 (ALU Core), that consists of 2 four bit CLAs. Module M8 (Shifter) will shift the input bus A by one to eight bits in either direction. Parity and 0 flags square measure generated by module M12 (Flags) victimization the input buses A, B and also the output bus Z; see the relevant figures or the Verilog model for his or her actual definition. Numerous logic functions of A and B square measure calculated by module M13 that doesn't have an understandable high level structure. 4. Simulation Results Table 1. Gate Areas For Different Iscas 89 Benchmark Circuits S.No Benchmark circuits Modules Primitives Registers CPU time (s) Gate (mm 2 ) 1 c area 2 c c c c c Each of the benchmark circuits are divided into two modules. In fig. 2 the primitives represents the total number of gates in both the modules. The registers represent the total number of inputs in the two modules. CPU time is the execution time of both the modules. The gate area represents the TSV (Through Silicon Via) where to be placed. The simulation result of c3540 benchmark circuit is shown in the fig.2. In fig. 3 the RTL Schematic of the c3540 benchmark circuit is shown. In fig. 4 the floorplanned design of the c3540 benchmark circuit is shown. In figure 5 the partitioning of the c3540 benchmark circuit is shown. By partitioning method the white space has been calculated. So at the white space the regular assignment and the placement of the TSVs can be done. When compared to the previous papers the gate area is minimized. So that the TSVs cab be placed. In previous papers the gate area was mm 2 for c3540, mm 2 for c1355, mm 2 for c7552, mm 2 for c5315, mm 2 for c1908 and mm 2 for c2670. Now the gate area is mm 2 for c3540, mm 2 for c1355, mm 2 for c7552, mm 2 for c5315, mm 2 for c1908, mm 2 for c

4 Figure 4. Floor planned design of c3540 benchmark circuit Figure 2. Simulation result of c3540 benchmark circuit Figure 5. Partitioning of c3540 benchmark circuit 5. Conclusion For the assignment and the regular placement of Through Silicon Via (TSV) the evolutionary optimization algorithm is used. The ISCAS 85 (International Symposium on Circuits And Systems) benchmark have been taken for this analysis. The floor planned design of the c3540 benchmark circuit is obtained by using cadence. The gate area is reduced so that by calculating the white space assignment and the location of the TSVs can be done. References Figure 3. RTL Schematic of c3540 benchmark circuit [1] B. Goplen and S. Sapatnekar, Placement of 3-D ICs with thermal and the inter layer via considerations, Proc. ACM/IEEE Design Autom. Conf., pp , [2] A. Quiring, M. Olbrich, E. Barke, Fast Global Interconnnect Driven 3D Floor planning, Proc. IFIP/IEEE Intl. Conf. Very Large Scale Integration (VLSI-SoC), pp [3] D. H. Kim, K. Athikulwongse, S. K. Lim, A study of through-silicon-via impact on the 3-D stacked IC layout, Proc. IEEE/ACM Int. Conference on Computer Aided Design, pp Nov [4] D. Cuesta, J. L. Risco-Martin, J. L. Ayala, J. I. Hidalgo, 3D thermal-aware Floor planner using a MOEA approximation and Integration, the VLSI journal, vol. 46, pp. 1021,

5 [5] H. Meng-Kai, V. Balabanov, C. Yao-Wen, TSV- Aware Analytical Placement for 3- D IC Designs Based on a Novel Weighted- Average Wire length Model, IEEE Trans. On Computer Aided Design of Integrated Circuits and Systems, vol. 32, no. 4, April [6] M. C. Kim, Multi objective Placement Optimization for High performance Nano scale Integrated Circuits, Doctor of Philosophy thesis, The University of Michigan, [15] S.V.Manikanthan and K.srividhya "An Android based secure access control using ARM and cloud computing", Published in: Electronics and Communication Systems (ICECS), nd International Conference on Feb. 2015,Publisher:IEEE,DOI: /ECS [16] Rajesh, M., and J. M. Gnanasekar. & quot; Path observation-based physical routing protocol for wireless ad hoc networks. & quot; International Journal of Wireless and Mobile Computing 11.3(2016): [7] J. Knechtel, I. L. Markov, J. Lienig, M. Thiele, Multi objective Optimization of Deadspace, a Critical Resource for 3D-IC Integration, Proc. Int. Conf. Computer Aided Design, pp [8] K. L. Sung, Regular Versus Irregular TSV Placement for 3D IC, Design for High Performance, Low Power and Reliable 3D Integrated Circuits, pp. 3-40, [9] P. Budhathoki, J. Knechtel, A. Henschel, I. M. Elfadel, Integrating 3D Floor planning and Optimization of Thermal Through-Silicon Vias, 3D Stacked Chips, Springer International Publishing Switzerland, pp , [10] M. Jung, J. Mitra, D. Z. Pan, S. K. Lim, TSV Stress-Aware Full Chip Mechanical Reliability Analysis and Optimization for 3D IC, Communications of the ACM, vol. 57, no. 1, pp , [11] G. Luo, Placement and Design Planning for 3D Integrated Circuits, PhDThesis, University of California, [12] Debasri Saha, Susmita Sur-Kolay, Multi objective Optimization of Placement and Assignment of TSVs in 3D ICs, 30th International Conference on VLSI Design and th International Conference on Embedded Systems, [13] S.Shakeela, Agribot: An Agriculture Robot, International Innovative Research journal of Engineering and Technology, vol 02, no 04, pp , [14] T. Padmapriya and V. Saminadan, Improving Throughput for Downlink Multi user MIMO-LTE Advanced Networks using SINR approximation and Hierarchical CSI feedback, International Journal of Mobile Design Network and Innovation- Inderscience Publisher, ISSN : vol. 6, no.1, pp , May

6 184