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1 A Translation Method of Ladder Diagram on PLC with Application to a Manufacturing Process Hyung Seok Kimy, Dong Sung Kimy, Naehyuck Changz, Wook Hyun Kwony y School of Electrical Eng, Seoul National University, Seoul, Korea z Computer Eng, Seoul National University, Seoul, Korea Abstract This paper proposes a translation method for PLCs (Programmable logic controllers) used in most automation systems It describes detailed steps of the method that converts from a ladder diagram directly toanativecode A general-purpose DSP (Digital signal processor) based PLC with the method is implemented A benchmark test in an automotive manufacturing process shows that the proposed translation method fairly speeds up execution in comparison with existing interpretation methods Introduction Programmable logic controller (PLC) was originally developed to replace electro-magnetic relay circuit It is widely used for implementing systems based on logic, sequencing, timing, counting and arithmetic [, ] PLCs are the backbone of most automation projects of the process control and instrumentation sector Automation of production lines and manufacturing processes will lead to the development of the manless factory where there is no longer any significant requirement for production workers or operators Such levels of automation will not be achievable without development of control systems, particularly PLCs [] As automation systems progress, works that the PLC carries out become more complex To treat them eciently, it has retained more than a hundred kinds of instructions Of the instructions, the proportion of special instructions such as PID and oating-pointoperations has been increased with the extension of its adaptable range These instructions need much time to execute The execution time of the PLC Korea This work is supported in part by the POSCON, Ltd, is important as a measure of its performance Thus, increase of instructions puts a burden to performance of the PLC To improve speed of the PLC, architectures of a new processor have been suggested They developed specic processors for PLC to raise its performance, using parallel processing methods [5{7] or specic IC (ASIC) design methods [8{0] For example, researches on reduced instruction set computer (RISC) put typical instructions of the PLC into a PLC-specic processor [5, 6] This method seems ecient to increase the execution speed But it is dicult to add new instructions to the processor and to develop it within a short time Koo et al [5] insist that the PLC based on a general-purpose processor has less performance than one based on a specic-purpose processor But the general-purpose processor has some practical advantages It has the price/performance curve that grows at a very fast rate It also can be manufactured at lower cost in a shorter time through the improvement related to the software The translator of PLC languages occupies a main part of the software The translator should convert the LD to another code close to the machine language But it is not easy to translate the graphical LD into the native code of a processor because of a semantic gap between them Existing translation methods have not considered it seriously They convert an LD to intermediate codes that consists of code matching with each node of the PLC On their operation, they fetch intermediate codes from the and then call a routine of corresponding block They usually require a long time even on high-performance RISC processors because they need many branches Accordingly, a method is needed to overcome slow speed and low eciency of this translation method To improve the performance of the PLC on the general-purpose processor, it is essential to translate

2 the graphical LD to the native code properly short This paper proposes the proper translation method of LD and describes implementation of it and to an automotive manufacturing process The paper is organized as following Section introduces existing LD translation approach in the PLC Section proposes our translation method of LD It also describes implementation of a PLC system for test Section evaluates translation methods with to an automobile manufacturing process Finally, the conclusion with future works is drawn in Section 5 Common Approach ming panel system mable logic controller micro processor power supplier I/O table Figure shows a common structure of a PLC The microprocessor moves state of a plant to an I/O table through input devices, executes stored in the, and controls the plant by transmitting calculated output values through the output devices Figure deinput circuit output circuit Figure : A general structure of PLC input device output device scribes operation to execute the After the PLC starts to control a plant, its memories repeat operation of gure As a kind of controller, PLC itself includes little user interface generally Instead, a ming unit similar to a calculator or a computer keyboard is connected to the CPU unit of the PLC through the communication port The mer draws LD directly with the ming unit to make s Then, PLC translates this into intermediate codes associated with each element of LD, and loads them into Its translator fetches intermediate codes and calls routine of corresponding execution codes As shown in the gure, `call' and `return' instructions appear frequently in existing method They usually require a long time even on high-performance RISC processors Execution time of the seems to be long because LD prorgram a e token analyzer mnemonic operation routine d system b c è X0 : 0 X : X : 0 Y0 : 0 Y : Y : I/O table a fetch by the command b call the execution routine that is associated with each command c translate operands and read data in I/O table d execute proper operation e go to a, then repeat a-e Figure : Block diagram of the LD interpreter the processor fetches intermediate codes of stored in and alternates them with an execution routine prepared already Accordingly, a method is needed to overcome slow speed and low eciency of this processing scheme Translation Method of LD Architecture Figure represents main ow of the proposed translation method of PLC by theblock diagram The rst ladder diagram PLC processor LD/mnemonic converter download macro compiler assembler Figure : Block diagram of the proposed method input is LD and the last output is executable binary code specic to the PLC processor First, in the LD/mnemonics converter, an LD

3 is converted to the that consists of LD mnemonics This process is shown in gure The (a) of gure is an example of simple LD block The (b) describes a tree for representing A C (a) B ;M_LDID 0ffffh,0ffffh,R LDHI 0ffffh,R OR 0ffffh,R ;; LD X ;M_LDIA 08000h,0h,R0 LSH -,R0 BR LD00 LD00: ;; LD X ;M_LDIA 08000h,0h,R0 LSH -,R0 BR LD00 LD00: ;; LD X ;M_LDIA 08000h,0h,R0 LSH -,R0 BR LD00 LD00: ;; AND X ;M_LDIA 08000h,0h,R0 ;M_LDID 07fffh,0ffffh,R LDHI 07fffh,R OR 0ffffh,R OR R,R0 AND R0,R0 BR AND00 AND00: ;; ORB LDI R0,R0 LSH,R0 ;M_LDID 08000h,0h,R LDHI 08000h,R OR 0h,R AND R,R0 ;; ANDB LDI R0,R0 LSH,R0 ;M_LDID 07fffh,0ffffh,R LDHI 07fffh,R OR 0ffffh,R OR R,R0 AND R0,R0 A ANDBLK B ORBLK (b) C AND LOAD LOAD LOAD AND ORBLK ANDBLK Figure : LD/mnemonic conversion Boolean equation () It makes translation of graphical LD block into text format easy A, B and C in (b) pull the latest data from the stack, then carry out AND or OR logical operation with them (c) C B A or 0 output(on=off) = ^ [ _ [ ^ ]] () `_' and `^' represent `and' and `or' logical operations respectively The (c) is a mnemonic as an output of the LD/mnemonic converter `LOAD' pushes the value of operand(the point of PLC) to stack `ANDBLOCK' and `ORBLOCK' operate _ and ^ logical operation respectively with the latest blocks calculated by `AND' or `OR' A stack is needed for these logical operations, a general purpose register that globally not be overwritten for other purpose can be used Through these steps, LD is changed to uniform text format similar to general assembly code Thus, its lexical analysis becomes easy The macro compiler translates each mnemonic to assembly code block specic to the main processor The point operands such as `X0' and `Y0' is replaced by matching addresses, constant operands matching constants At this process, the macrocompiler noti- es mer of ming errors of the source code and optimizes code for length and execution time of machine code Figure 5 shows resultant assembly code in TMS0C0 DSP The assembler generates executable binary code with the assembly code In the two-pass assembler, the rst pass stores addresses of Figure 5: assembly code labels such as `LD00' and `AND00' in symbol table, then the second pass refers to the table and converts assmbly code to binary code The PLC has a number of branches because it decides, by logic operation, whether it executes a rung or not It requires a large The PLC-specic assembler that reduces both the size of the and the translation time is shown in gure 6 PLC mnemonics have independent relation with each other except ones with ow control or global variable Using this, at step, addresses of labels commonly used with another mnemonic are stored in a symbol table After processing labels and global variables, the assembly code block that matches with each mnemonic passes the assembler in the order of,,,5 steps Whenever ablock nishes conversion, all data from the symbol table are erased except global data Then, reduction and less translation time are achieved As a ;; LD X ;M_LDIA 08000h,0h,R0 LSH -,R0 BR LD00 LD00: ;; LD X ;M_LDIA 08000h,0h,R0 5 LSH -,R0 BR LD00 LD00: ;; LD X ;M_LDIA 08000h,0h,R0 6 7 LSH OR BR LD00: -,R0 R0,R0 LD00 symbol table LD00: LD00: LD00: AND00: Figure 6: pass of the assembler nal result of the LD translator, the executable binary code produced by the assembler is transmitted to the PLC and resides in its

4 Implementation of PLC We have built a large-scale PLC based on digital signal processor (DSP) TMS0C0 It supports about 00 mnemonics including logical operations, arithmetic operations, trigonometric functions, PID etc It also has 0,000 points including I/O points and temporal registers Serial communication port has been set to connect the PLC to the loader, IBM-PC Internal cache is disabled in order to measure constant execution time The wait state of the I/O table and the is set to 50ns, 5ns respectively Both translation methods are implemented for their performance evaluation Performance Evaluation Execution Time of Mnemonics Translation time and execution time can be considered as main factors for performance evaluation First, the translation time of the existing method is much shorter than that of the proposed method To get executable binary code using the proposed method, the LD must pass through procedure of several steps such as LD-mnemonics converter, macro compiler and assembler Besides, le input/output is taken at every step But, usually, once an of PLC has been xed, without modication of the it is used for a long time, about several years Stopping PLC operation for update of the can cause a great loss to the users Since the user does not nd a diculty in time due to infrequent translation, translation time is not related to the performance of PLC Therefore, it is concluded that the element for evaluating the LD translator is not translation time but execution time of the mnemonics For both methods, the graph of mean value of measured execution time of various kinds of LD mnemonics is shown in gure 7 The mnemonics are classied according to their purpose and form, based on the grouping of a PLC manufacturers [,] Common arithmetic mnemonic generally has three operands which consist of two sources and one destination Mnemonics with three operands occupies most of common PLC mnemonics They provide the largest reduction of the execution times because they pass operand routine three times at least and fetch the intermediate code in more frequently On the contrary, owcontrol mnemonics are in the least reduction since owcontrol mnemonics have an operand as label and have brief machine code Accordingly, the proposed structure is ecient when LD mnemonics have more operands and longer code Application Y00 Y0 Y0 Y0 M0 M Y0 HOME POS Y00 Y00 X000 Y0 Y0 Y00 X00 Y0 Y0 START LS LS Y0 X000 X000 M0 Y00 Y0 Y00 Y0 (T 0 ) (T ) (T ) (T ) (T ) (T 5 ) (T 6 ) basic tranfer timer,counter compare common arithmetic special arithmetic flow control proposed existing Figure 7: execution time of LD mnemonics We measured the execution time of the LD Y0 LS LS Figure 8: LD for automotive process Figure 8 is an example of the LD for automatic control of an shuttle process used in an automotive manufacturing process The operation sequence of the process is Home Position!Shuttle Up!Shuttle Advance!Shuttle Down!Shuttle Return!Home Position LD ming can be done for various puposes and is not unigue The arithmetic operations

5 such as add, mul and sin can be assigned as outputs in LD They also can be represented as a form of fuction block (FB) These non-logical operations are divided into common arithmetics (add,sub,mul etc) and special arithmetics (sin,cos,pid etc) To analyze re- execution time 6 5 the size of Nexe =00 special arithmetic (P 5 ) (P ) timer,counter common 0% 5% flow control arithmetic % (P 6 ) (P ) 60% (P ) comparison 9% transfer (P ) 0% basic 689% (msec) Nexe =00 N exe =00 0% 0% 60% 80% ratio of basic mnemonic in 00% existing structure Figure 9: frequency of mnemonics in the process duction of execution time of an, a ratio of mnemonics included in the should be known Figure 9 is a result of practical examining s on the automotive manufacturing process We analyzed the execution time of an, changing total number of mnemonics and percentage of basic mnemonics respectively The following equation is calculation of execution time of an is T0T6 mean execution time of each class of the mnemonics, as the result of this experiment N exe is total number of LD mnemonics in the T exe = T0 P basic N exe () 6X P i + T i i= ( ; 0:689) ( ; P basic) N exe The percentage of basic mnemonic, P basic, is assumed to be changed according to the But PP6 are constants and ratio between them is assumed to be constant Figure 0 represents a relation between ratio of basic LD mnemonics and execution time of It also shows change of the execution time when increasing N exe,thenumber of mnemonics, in a by three hundreds It also can be noted that dierence between the total execution times is decreased if the uses basic mnemonics frequently Memory requirement of each method is calculated and the result is represented in (),() N PLC is the number of mnemonics that the PLC serves On the existing method, requirement is M 0 =:N exe +8:97N PLC +8 (Bytes) () Figure 0: method proposed structure Execution time of a in each At the proposed method, requirement is M =9:790N exe (Bytes) () Unless N exe is exceedingly large in the process, M does not require absurdly much compared with M 0 5 Conclusion We have described a method to translate LD into the native code of the processor The improvement of the execution time has been considered in order to acquire the high-speed PLC In the proposed method, an executable code is generated without converting the LD to the intermediate code It includes three steps of the LD/mnemonic converter, the macro compiler and the assembler We have built a high-speed DSP-based PLC system with the translation method The execution time of each mnemonic has been measured on the PLC When the proposed translation method is applied to an automotive manufacturing process, the execution time of the s used by the process has been analyzed The proposed translation method results in better performance The requirement of it can be much more as a tradeo of speed But the proposed translation method does not require nonrealistic size unless the of the process is very long 5

6 As the role of the PLC is larger in various elds, further studies on ecient translation method will be required They can be investigated with execution time and requirement The translation method of other ming languages of the PLC may be valuableaswell [] POSFA PLC Programming manual, POSCON, 995 [] MCPU Programming manual, LG industrial electronics, 996 References [] I Warnock, Programmable Controllers - Operation and, Prentice Hall, 988 [] International Electrotechnical Commission, Programmable Controllers - Part : Programming language, IEC Publication-, 99 [] J Park, N Chang, G S Rho, and W H Kwon, \Implementation of a Parallel Algorithm for Event Driven Programmable Controllers," Control Eng Practice, vol, no, pp , 99 [] H Murakoshi, M Sugiyama, G Ding, T Oumi, T Sekiguchi, and Y Dohi, \A High-Speed Programmable Controller based on Petri Net," Proceeding of '9 IECON, pp , 99 [5] Jong-il Kim, J Park, and W H Kwon, \Architecture of a ladder solving processor for mable controllers," Microprocessors and Microsystems, vol 6, no 7, pp 69-79, 99 [6] G Rho, J Park, and W H Kwon, \Load Balancing of a Data-ow Based Programmable Controllers," Proc of IECON 9, Hawaii, USA, 99 [7] A J Laduzinsky, \An Open Architecture, VMEbus PLC," Control Engineering, vol 8, no, 99 [8] K Koo, G Rho, J Park, WH Kwon, and N Chang, \Architectural Design of a RISC Processor for Programmable Logic Controller," Journal of Systems Architecture, vol, 998 [9] G Rho, K KOO, N Chang, J Park, and WH Kwon, \Implementation of a RISC Processor for Programmable Controllers," Microprocessors and Microsystems, 99 [0] Y Shimokawa, T Matsushita, H Furuno, and Y Shimanuki, \A High-Performance VLSI chip for Instrumentation and Electric Control," Proc of IECON 9, pp88-889, 99 [] RW Lewis, Programming Industrial Control Systems using IEC - 6

However, no results are published that indicate the applicability for cycle-accurate simulation purposes. The language RADL [12] is derived from earli

However, no results are published that indicate the applicability for cycle-accurate simulation purposes. The language RADL [12] is derived from earli Retargeting of Compiled Simulators for Digital Signal Processors Using a Machine Description Language Stefan Pees, Andreas Homann, Heinrich Meyr Integrated Signal Processing Systems, RWTH Aachen pees[homann,meyr]@ert.rwth-aachen.de