VON NEUMANN ARCHITECTURE. VON NEUMANN ARCHITECTURE IB DP Computer science Standard Level ICS3U

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1 C A N A D I A N I N T E R N A T I O N A L S C H O O L O F H O N G K O N G 5.3 Putting all the Units Together the Von Neumann Architecture 5.4 s Von Neumann Architecture the four components that make up the Von Neumann architecture memory input / output arithmetic / logic unit (ALU) control unit (CU) Von Neumann Architecture the execution of a program in a Von Neumann Architecture computer proceeds in three distinct phases (i.e. the Von Neumann Cycle) fetch decode execute the three steps are repeated for every instruction until either the computer executes a HALT instruction or there is a fatal error 1

2 Von Neumann Cycle an algorithm / pseudocode for the process While we do not have a HALT instruction or a fatal error Fetch phase Decode phase Execute phase End of the loop modern-day computer scientists believe the Von Neumann Architecture may be reaching the end of its useful lf life hardware design, manufacturing methods, and circuit technology, computer designers have been able to take the basic sequential architecture and improve its performance by 4 or 5 orders of magnitude first generation computers machine language instructions per second second generation computers 1 million machine language instructions per second modern-day computers 2-5 billion machine language instructions per second 2

3 processing speed is NOT increasing exponentially, but at logarithmically the slowdown in increasing the processing speed is the inability to place gates any closer together on a chip the physical limitations of registers the inability of the sequential one-instruction-at-atime Von Neumann model to handle large-scale problems is called the Von Neumann bottleneck principle in If you cannot build something to work twice as fast, do two things at once. The results will be identical. computers not with one processor, but with tens, hundreds, or even thousands each processor is occupied with meaningful work speed up the solution to large problems by 1, 2, or 3 orders of magnitude the idea behind the dual-core and quad-core processors that have two or four separate processors on a single chip 3

4 SIMD a single program whose instructions are fetched/decoded/executed in a sequential manner by one control unit the ALU (circuits and registers) is replicated man times each ALU has its own local memory where it may keep private data SIMD the control unit fetches an instruction and broadcasts that instruction to every ALU, which executes it in parallel on its own local data useful in operations on mathematical structures called vectors and arrays MIMD also known as the cluster computing entire processors rather than just the ALU every processor is capable of executing its own separate program in its own private memory at its own rate each processor tackles a small part of the overall problem, communicates its result to each other 4

5 MIMD it is a scalable architecture to match the number of processors to the size of the problem Homework Pg. 273 # 1 What are the advantages and disadvantages of using a very large memory cell size, say, W = 64 instead of the standard size W = 8? If each integer occupies one 64-bit memory cell and is stored using sign/magnitude notation, what are the largest (in terms of absolute value) positive and negative integers that can be stored? What if two cells are used to store integers? Homework Pg. 273 # 3 A memory unit that is said to be 640 KB would actually contain how many memory cells? What about a memory of 512 MB? What about a memory of 2 GB? 5

6 Homework Pg. 273 # 4 Explain what use a read-only memory (ROM) serves in the design of a computer system. What type of information is kept in a ROM, and how does that information originally get into the memory? 6