IN4073 Embedded Real-Time Systems. X32 Microcontroller Soft core

Transcription

1 IN4073 Embedded Real-Time Systems X32 Microcontroller Soft core

2 FGPAs vs Standard Microcontrollers 8051, ARM,.., core architectures AD, Atmel, Dalas, Intel, MC (PIC), NS, ST, TI, Zilog ASICs with core, e.g., Cypress Can be expensive, peripheral set is hard-wired FPGAs are a flexible, low-cost bread-board to experiment with HW using SW (VHDL) instead of ICs and wires More expensive FPGA also have hard cores: often best of both worlds TE0300 Board: $100 (1600k gates, no hard core) In4073 Emb RT Sys ( ) 2

3 TE0300 FPGA + Memory Create your own core and set of peripherals that communicate via FPGA I/O lines (UARTS, LEDS) UART (PC Link, chars) UART (QR Link, frames) LEDS (8) Timer Clock Filters In4073 Emb RT Sys ( ) 3

4 Turn FPGA into a Microcontroller high-speed designs in HW (e.g., VHDL) XS3E-1600 clock 100 MHz, 1600k gates low-speed designs in SW (e.g., C) Need processor core that communicates with VHDL devices no hard core (only in more expensive FPGAs) so need soft core to execute programs academia: zero-cost public domain VHDL soft core experience with free 8-bit soft core (6502) + tool chain (CC65): not so good so we built our own (well, Sijmen Woutersen did) In4073 Emb RT Sys ( ) 4

5 X32 Approach (1) no binary compatibility issues so choice of instruction set architecture (ISA) basically free but we don t want to build (i.e., retarget) an ANSI C compiler to some ISA that we first need to architect given the specific FPGA properties we just want simplicity, no big-time performance optimization project Backend 1 ISA 1 C Front End...? Backend n ISA n In4073 Emb RT Sys ( ) 5

6 X32 Approach (2) So we took lcc (ANSI C) But we simply took the intermediate representation (byte code) as target ISA So compiler is already done Soft core = just writing an ISA interpreter in VHDL Experimental 32 bit arch: X32 Top-down approach: X32 + compiler took 1 MSc project! Simple, but only 2 MIPS! (mem bound stack ISA!) C lcc Front End lcc byte code asm, link X32 object code X32 In4073 Emb RT Sys ( ) 6

7 X32: Memory Map SRAM FFFFFFF Peripheral rd wr rdy addr data CPU Peripheral K 80000XXX 80000XXX Interrupt Controller C FFFFFFFF Peripherals: memory-mapped I/O (32 bit word => 4 addresses) Int.Controller: special peripheral (occupies larger address space) In4073 Emb RT Sys ( ) 7

8 X32 Peripheral: Simple Output addr decoder addr off-board output lines reg we data wr CPU NOTE: all circuits are VHDL In4073 Emb RT Sys ( ) 8

9 X32 Peripheral: Simple Input button, off-board input lines oe addr decoder rd addr CPU data NOTE: all circuits are VHDL In4073 Emb RT Sys ( ) 9

10 X32 Peripheral: Complex Devices LEDs, rx, tx clocks, timers, UARTs oe reg we addr decoder rd addr data wr CPU NOTE: all circuits are VHDL In4073 Emb RT Sys ( ) 10

11 X32 Peripheral Interrupts buttons, LEDs, switches, timers, RS232, off-board I/O ports Peripheral 0 - K IRQ 0 IRQ n Interrupt Controller CPU multiple IRQ lines per peripheral possible (e.g., tx+rx IRQ per UART) CPU peripherals used at the lab: buttons, LEDs, UART (RS232 interfaces to PC and to QR) In4073 Emb RT Sys ( ) 11

12 X32: Interrupt Controller IRQ 0 Interrupt Controller interrupt acknowledge IRQ n IE k, prio k, vector k IE_global vector priority exec level CPU FSM for each IRQ: IRQ. IE IE_global. (priority > exec level) stdby IE scheduled acknowledge servicing / interrupt In4073 Emb RT Sys ( ) 12

13 X32: Interrupt Sources CPU: divide-by-0, overflow (disable unless needed!) Buttons, switches, I/O ports positive AND negative edge-triggered Timers: counter value > threshold reg UART: rx buffer char received / tx buffer empty Maxon motor decode error (in2305) QR link data frame (7 readings) received (in4073) In4073 Emb RT Sys ( ) 13

14 X32: Interrupt Features Each peripheral can have multiple IRQ lines Local interrupt enable/disable IRQ latch within IC cleared on local interrupt disable Each IRQ can have different priority and ISR vector ISRs are serviced in order of priority Interrupts NOT automatically disabled: ISR preemption! Only higher-priority IRQs preempt current priority IRQ Global interrupt enable/disable Pending interrupt by IC NOT cleared on global disable In4073 Emb RT Sys ( ) 14

15 X32: Software ISA: lcc + X32-specifics: {LOAD STORE} X met X {SP, FP, AP, EL,..} header file x32.h library functions console I/O (getchar/putchar) strings printf setjmp/longjmp (for compatibility reasons).. No HW floating-point support (SW lib) In4073 Emb RT Sys ( ) 15

16 X32: Memory-mapped I/O in C #define ADDR_PERIPHERALS 0x int *peripherals = (int *) ADDR_PERIPHERALS; #define PERIPHERAL_LEDS 0x07 // LEDs are 8th register int { } main(void) // write to 0x offset of 7 ints // is 0x x1c = 0x c: peripherals[peripheral_leds] = 0x77; return(0); In4073 Emb RT Sys ( ) 16

17 X32: Sample Project X32 Demo Board: X3S1200 FPGA RS232 (PC link) 8 LEDs 8 switches 4-digit SSD 4 buttons In4073 Emb RT Sys ( ) 17

18 X32: Sample Project #include <x32.h> #define X32_leds = peripherals[peripheral_leds] #define X32_buttons =... #define X32_display =.. #define X32_clock = int { } main(void) printf( Hello World!\r\n ); while (1) { X32_display = X32_clock; X32_leds = X32_buttons; if (X32_buttons == 0x09) break; } In4073 Emb RT Sys ( ) 18

19 X32 Site (Free Downloads) In4073 Emb RT Sys ( ) 19

20 X32: Demo Demo.. (x32_projects.tgz: leds.c) In4073 Emb RT Sys ( ) 20

21 Interrupts: Principle dev 1 IRQ contr CPU IRQ # dev N... MOVE R1, (var-addr) MULT R1, 9 DIVIDE R1, 5 ADD R1, HW CALL ISR: PUSH R1... POP R1 RET In4073 Emb RT Sys ( ) 21

22 X32 Interrupts IRQ # IRQ contr CPU IRQ controller preprocesses multiple IRQ s Each device: (IRQ #, priority) Vectored IRQ Interrupts NOT disabled Automatic ISR preemption if prio IRQ > prio current ISR Normal call saves context -> no interrupt keyword In4073 Emb RT Sys ( ) 22

23 Example: ISR version of hello.c #define IRQ_BUTTONS = INTERRUPT_BUTTONS void isr_buttons(void) { X32_leds = X32_buttons; if (X32_buttons == 0x09) done = 1; } void main(void) { SET_INTERRUPT_VECTOR(IRQ_BUTTONS),&isr_buttons); SET_INTERRUPT_PRIORITY(IRQ_BUTTONS),10); ENABLE_INTERRUPT(IRQ_BUTTONS); ENABLE_INTERRUPT(INTERRUPT_GLOBAL); printf( Hello World!\r\n ); while (! done) X32_disp = X32_clock; DISABLE_INTERRUPTS(INTERRUPT_GLOBAL); } In4073 Emb RT Sys ( ) 23

24 X32: Demo Demo.. (x32_projects.tgz, console.c) In4073 Emb RT Sys ( ) 24

25 Interrupts: Data Sharing Problem void { } isr_read_temps(void) itemp[0] = peripherals[..]; itemp[1] = peripherals[..]; void { NOT ATOMIC! } main(void)... while (TRUE) { tmp0 = itemp[0]; tmp1 = itemp[1]; if (tmp0!= tmp1) panic(); } In4073 Emb RT Sys ( ) 25

26 Interrupts: Data Sharing Problem single C expressions usually aren t atomic either..: void { } isr_read_temps(void) itemp[0] = peripherals[..]; itemp[1] = peripherals[..]; void { NOT ATOMIC! } main(void)... while (TRUE) { if (itemp[0]!= itemp[1]) panic(); } In4073 Emb RT Sys ( ) 26

27 Solutions (1) Disable interrupts that trigger those ISRs that share the data... while (TRUE) {!! DISABLE INT tmp0 = itemp[0]; tmp1 = itemp[1];!! ENABLE INT if (tmp0!= tmp1) panic(); } The critical section is now atomic Use semaphores to protect critical section (discussed in a later lecture) In4073 Emb RT Sys ( ) 27

28 Solutions (2) Don t disable interrupts but write ingenious code, e.g., involving alternating data buffers or even queues such that ISR and (main) code never access the same data Why? code becomes error-prone and (too) hard to read Rule: keep it simple, just disable interrupts, as long as you adhere to: keep the critical sections SHORT keep the ISRs SHORT (to minimize latency, see later) In4073 Emb RT Sys ( ) 28

29 X32: Demo Demo.. (x32_projects.tgz, critical.c) In4073 Emb RT Sys ( ) 29

30 Interrupt Latency Quick response to IRQ may be needed Depends on previous rules: worst-case latency = t_disabled + t_higher prio ISRs + t_myisr DI EI ip ISR nw ISR main nw IRQ ip IRQ In4073 Emb RT Sys ( ) 30

31 X32: Demo Demo.. (x32_projects.tgz: timing.c) In4073 Emb RT Sys ( ) 31

32 Embedded SW Architectures Round-Robin Round-Robin with interrupts RTOS high prio everything deva ISR devb ISR devz ISR task code deva ISR devb ISR devz ISR task code A task code B task code Z low prio In4073 Emb RT Sys ( ) 32

33 RTOS: Primary Motivation Task switching with priority preemption Additional services (semaphores, timers, queues,..) Better code! Having interrupt facilities, one doesn t always need to throw a full-fledged RTOS at a problem However, in vast majority of the cases the code becomes (1) cleaner, (2) much more readable by another programmer, (3) less buggy, (4) more efficient The price: small run-time overhead and small footprint In4073 Emb RT Sys ( ) 33

34 Task Switching Task switching = switching from current context (PC, stack, registers) to another context Context = thread identity, hence aka multithreading Need two constructs: initialize a context switch to a context Often used: setjmp/longjmp We use X32 init_stack/context_switch In4073 Emb RT Sys ( ) 34

35 Simple Example (X32) void void int { } void { } **thread_main; **thread_a; *stack_a[1024]; main(void) thread_a = init_stack(stack_a, task_a); printf( now in thread_main\n ); context_switch(thread_a,&thread_main); printf( back in main_thread\n ); task_a(void) print( now in thread_a\n ); context_switch(thread_main,&thread_a); In4073 Emb RT Sys ( ) 35

36 Time Slicing Example (1) void void int void { } **thread_main; **thread_a; *stack_a[1024]; thread_id; isr_timer(void) if (thread_id == 0) { thread_id = 1; context_switch(thread_a,&thread_main); } else { thread_id = 0; context_switch(thread_main,&thread_a); } In4073 Emb RT Sys ( ) 36

37 Time Slicing Example (2) int { main(void) thread_a = init_stack(stack_a, task_a); thread_id = 0; // now in main!! set timer to interrupt every 5 ms } void { } while (TRUE) print(now in thread_main\n); task_a(void) while (TRUE) print( now in thread_a\n ); In4073 Emb RT Sys ( ) 37

38 X32: Demo Demo.. (x32_projects.tgz: slicing.c) In4073 Emb RT Sys ( ) 38