Single-Cycle Examples, Multi-Cycle Introduction

Transcription

1 Single-Cycle Examples, ulti-cycle Introduction 1

2 Today s enu Single cycle examples Single cycle machines vs. multi-cycle machines Why multi-cycle? Comparative performance Physical and Logical Design of Datapath and Control icroprogramming 2

3 Example of Derived Control: AL Control Signals If we have 5 arithmetic operations And Or Add Subtract Set-on-less-than Need 3 bits to distinguish among them AL Control Input Function 000 And 001 Or 010 Add 110 Subtract 111 Set-on-less-than AL Control 3 AL 3

4 AL Control for Each Type of Instruction opcode rs rt rd shamt funct Opcode ALop Operation Function AL Action AL Control LW 00 load word add 010 SW 00 store word add 010 Branch equal 01 branch equal subtract 110 R-type 10 add add 010 R-type 10 subtract subtract 110 R-type 10 AND and 000 R-type 10 OR or 001 R-type 10 set-on-less-than set-on

5 AL Control for Each Type of Instruction opcode rs rt rd shamt funct Opcode ALop Operation Function AL Action AL Control LW 00 load word add 010 SW 00 store word add 010 Branch equal 01 branch equal subtract 110 R-type 10 add add 010 R-type 10 subtract subtract 110 R-type 10 AND and 000 R-type 10 OR or 001 R-type 10 set-on-less-than set-on ALop is an encoding created to distinguish LW/SW, Branch Equal, R-type It is derived from the instruction opcode through some decoding logic 5

6 apping Control Bits to Hardware Opcode ALop Operation Function AL Action AL Control LW 00 load word add 010 SW 00 store word add 010 Branch equal 01 branch equal subtract 110 Let s try a simple example: generate the AL control signals for the three instructions above In a high-level language, one could write if (ALop == 00){ } ALcontrol = 010; else if (ALop == 01){ } ALcontrol = 110; AL Control Input Function 000 And 001 Or 010 Add 110 Subtract 111 Set-on-less-than 6

7 apping Control Bits to Hardware (cont.) Opcode ALop Operation Function AL Action AL Control LW 00 load word add 010 SW 00 store word add 010 Branch equal 01 branch equal subtract 110 Hardware Description Language Input Truth Output Tables ALop[1,0]ALControl[2] if (ALop[1] == 0 & ALop[0] == 0){ } ALcontrol[2] = 0; ALcontrol[1] = 1; ALcontrol[0] = 0; else if (ALop[1] == 0 & ALop[0] == 1){ } ALcontrol[2] = 1; ALcontrol[1] = 1; ALcontrol[0] = 0; Input Output ALop[1,0] ALControl[1] Input Output ALop[1,0] ALControl[0]

8 apping Control Bits to Hardware (cont.) Opcode ALop Operation Function AL Action AL Control LW 00 load word add SW 00 store word add Branch equal 01 branch equal subtract Truth Tables Input Output Input Output Input Output ALop[1,0]ALControl[2] ALop[1,0] ALControl[1] ALop[1,0] ALControl[0] ALop[1] ALop[0] 1 0 ALcontrol[2] ALcontrol[1] ALcontrol[0] 8

9 Truth Table for the Full Set of AL Control Bits To optimize the control logic, identify Patterns that cannot occur (e.g. ALop = 11) Signals that are irrelevant for the function we want to compute The more don t care signals, the better the chance for optimal logic Don t care signals can be replaced by 0s or 1s as needed in the logic optimization process Note that: 11 is a pattern that cannot occur for ALop Thus, 01 can be replaced by 1, and 10 by 1x Function bits are ignored for I-type instructions (LW/SW, branch) For all other combinations not included in the previous truth table, the outputs are don t cares 9

10 Truth Table for the Full Set of AL Control Bits ALOp ALOp1 ALOp0 F5 Function code F4 F3 F2 F1 F0 AL Control How do we use ALOp bits and Function code bits to generate the AL control bits? ALOp Block of Logic Function Bits AL Control 10

11 When is AL Control Bit 2 == 1 Let s pick one bit of the output and examine it, closely ALOp ALOp1 ALOp0 F5 Function code F4 F3 F2 F1 F0 AL Control AL Control Bit 2 11

12 When is AL Control Bit 2 == 1 (cont.) ALOp ALOp1 ALOp0 F5 Function code F4 F3 F2 F1 F0 AL Control Operation Bit 2 is 1 when ALOp0 bit is 1 OR ALOp1 bit is 1 AND Function Code Bits F2 F1 F0 = 010 But if ALOp1 bit is 1 AND F2 F1 F0 = 11 OR 011, AL Control Bit 2 is and thus could be mapped to a 1 Hence: Operation Bit 2 is 1 when ALOp0 bit is 1 OR ALOp1 bit is 1 AND Function Code Bit F1 = 1 12

13 apping to Logic Gates Operation Bit 2 is 1 when ALOp0 bit is 1 OR ALOp1 bit is 1 and Function Code F1 = 1 ALOp ALOp 0 F3 ALOp 1 F1 AL Control Bit 2 F(5-0) F2 F1 F0 13

14 sing Don t Care Information ALOp ALOp1 ALOp0 F5 Function code F4 F3 F2 F1 F0 AL Control If you use don t cares on the inputs: make sure you propagate backwards! Do not use in a conflicting way for some other output! Sometimes, this is not worth the trouble 14

15 Repeat: When is AL Control Bit 1 == 1 ALOp ALOp1 ALOp0 F5 Function code F4 F3 F2 F1 F0 AL Control AL Control Bit 1 15

16 Truth Table for Full Set of AL Control Bits ALOp ALOp1 ALOp0 F5 Function code F4 F3 F2 F1 F0 AL Control Operation Bit 1 is 1 when ALOp1 bit is 0 OR Function Code Bits F3 F2 F0 = 000 or F2 F1 F0 = 010 AL Control Bit 1 sing the don t care information, Bit 1 is 1 when ALOp1 bit is 0 OR Function Code Bit F2 = 0 16

17 apping to Logic Gates Operation Bit 1 is 1 when ALOp1 bit is 0 OR Function Code Bit 2 (F2) is 0 ALOp F3 F(5-0) F2 F1 ALOp1 F2 AL Control Bit 1 F0 17

18 Repeat: When is AL Control Bit 0 == 1 Are we having fun yet? ALOp ALOp1 ALOp0 F5 Function code F4 F3 F2 F1 F0 AL Control AL Control Bit 0 18

19 Truth Table for Full Set of AL Control Bits ALOp ALOp1 ALOp0 F5 Function code F4 F3 F2 F1 F0 AL Control Operation Bit 0 is 1 when ALOp1 bit is 1 AND Function Code Bit 3 (F3) is 1 OR Function Code Bit 0 (F0) is 1 We have used the don t care information for Bit 0 AL Control Bit 0 19

20 apping to Logic Gates Operation Bit 0 is 1 when ALOp1 bit is 1 AND Function Code Bit 3 (F3) is 1 OR Function Code Bit 0 (F0) is 1 ALOp F3 F(5-0) F2 F1 F0 F3 F0 ALOp1 AL Control Bit 0 20

21 AL Control Logic ALOp Function Bits Block of Logic ALOp AL Control ALOp 0 F3 ALOp 1 F1 AL Control Bit 2 F(5-0) F2 F1 F0 F3 ALOp 1 ALOp 1 F2 AL Control Bit 1 AL Control Bit 0 21

22 Basic Datapath with Control for Our AL Current PC PC Instruction 4 Instr[15-11] Adder Instr[25-21] C O N T R O L Note we did not show logic for this one ALOp RegWrite Read Reg 1 Instr[20-16] Read Read Reg 2Data 1 Write Reg Write Data Read Data 2 ALSrc << 2 AL ADDER Zero PCSrc emwrite emtoreg Read data RegDst Instr[15-0] Sign extend Instr[15-0] AL Control emread We did this one. Function Field from Instruction 22

23 Basic Datapath with Control Current PC PC Instruction 4 Instr[15-11] Adder Instr[25-21] C O N T R O L ALOp RegWrite Read Reg 1 Instr[20-16] Read Read Reg 2Data 1 Write Reg Write Data Read Data 2 ALSrc << 2 AL ADDER Zero PCSrc emwrite emtoreg Read data RegDst Instr[15-0] Sign extend Instr[15-0] AL Control emread 23

24 Another Control Example: How to do PC Select? PC Instruction Current PC 4 Instr[15-11] Adder Instr[25-21] C O N T R O L ALOp << 2???? ADDER RegWrite Read Reg 1 Instr[20-16] Read Read Reg 2Data 1 Write Reg Write Data Read Data 2 ALSrc AL Zero PCSrc emwrite emtoreg Read data RegDst Instr[15-0] Sign extend Instr[15-0] AL Control emread 24

25 PC Select Current PC PC Instruction 4 Instr[15-11] Adder Instr[25-21] C O N T R O L ALOp Branch RegWrite Read Reg 1 Instr[20-16] Read Read Reg 2Data 1 Write Reg Write Data Read Data 2 ALSrc << 2 AL ADDER Zero PCSrc emwrite emtoreg Read data RegDst Instr[15-0] Sign extend 16 Instr[15-0] 32 AL Control emread 25

26 echanics: Implementing Jumps opcode address PC[31:28] address 0 0 Jump instruction contains 26 bit immediate field (address) When jump instruction executes, the new PC is constructed as follows: Top 4 bits of PC stay the same Jump instruction s address is appended to the top 4 bits of the PC Bottom two bits are set to zero 26

27 Jump Example Current Program counter is: 0x What s the new PC after the Jump instruction executes? Top four bits of PC are 0x2 ( ) Jump

28 How Datapaths Appear in Silicon: Pentium Integer ALs. Superscalar means here more than one AL. Floating point datapath. Pipelined means just what you would think here: it has pipeline registers to make it faster 28

29 How Datapaths Appear in Silicon: ALPHA Floating point unit Floating-point n nit Floating apper and Queue Instruction Data path Bus Interface nit emory Controller Integer nit (Left) Integer apper Integer Queue Data and Control Busses emory Controller Integer nit (right) 2 Integer units. Again, more than 1 due to superscalar execution model Instruction Cache BI Data Cache 29

30 How Datapaths Appear in Silicon: Power PC 30

31 Common Layout Style for These Things Roughly speaking: tall and skinny Pentium integer ALPHA float Pentium float ALPHA integer 31

32 Why Tall & Skinny : Bit-Slice Style ALs Logic dominated by wide busses (32, 64) of the operand bits Start with all the wires for all the operand bits 32

33 Why Tall & Skinny : Bit-Slice Style ALs Logic dominated by wide busses (32, 64) of the operand bits Start with all the wires for all the operand bits Then you hang logic along the busses in the other dimension etc Logic ops Barrel shifter Fast adder 33

34 Why Tall & Skinny : Bit-Slice Style ALs When computations get complex, deep in logic, you pipeline Start with all the wires for all the operand bits Then you hang logic along the busses in the other dimension If the computation is too deep as logic, you pipeline. Big example is floating point units. Pipeline stage Operation Operation Pipeline stage Operation Operation 34

35 Single Cycle Design Summary Datapath design First, make sure you have all the right stuff in the datapath ake sure you know all your ISA instructions, formats, opcodes, etc Lay out a basic, simple datapath, try your instructions You want to avoid being surprised later that you missed an essential unit Controlpath design ake sure you know all the control signals you need, and precisely what they do ake sure you know when you have a direct control signal (ie, it s in the instruction format itself) vs a derived control signal, that you need to create from a block of logic. ake sure you can actually build the derived signals Try your instructions, make sure your control works OK Do you need more units? Different units? The extra logic you will need is the stage management stuff for stalls, hazards, etc. 35

36 Typical Instruction Execution 1) Fetch instruction from memory 2) Decode instruction 3) If necessary, perform an AL operation 4) If memory access, perform load/store 5) Write results back to register file and increment the PC 36

37 Complete Single-cycle Datapath Current PC PC 4 Adder Instruction emory (RA) << 2 ADDER Instruction Register File Read Reg 1 Read Read Reg 2Data 1 Write Reg Write Data Read Data 2 Sign extend AL Zero Data emory (RA) Write Data Read data 37

38 Single Cycle Design Process 1. Go through each instruction type 2. Figure out the resources and data paths required How many adders for PC, operation, etc. How many ports to memory 3. Overlay requirements of all instructions Where two values need to get to one place, insert a multiplexor Keep track of required control 4. Design the control logic 5. You re done! Result: Easy to understand machine. Visual model of the ISA Only storage objects are architectural objects: emory, Register File, PC 38

39 What s Wrong with a Single-Cycle Implementation It was assumed that data flows through all parts of the datapath in ONE clock cycle From Register file to memory From emory to register file From PC to PC From Register File to Register File How long is a cycle AL 10 ns Register File 5 ns emory 10 ns Assume everything else takes zero time 39

40 Instruction Timings Instr Type Instrem RegRead AL Dataem Reg Write Total R-format ns Load ns Store ns Branch ns Jump ns PC Register File Read Reg 1 Read Read Reg 2Data 1 Write Reg Write Data Read Data 2 Sign extend AL Zero Data emory (RA) Write Data Read data 40

41 What s Wrong with a Single-Cycle Implementation Difficult to implement variable cycle clock sually run the clock at the SLOWEST speed This is called the critical path The critical path is the path through the system which limits performance What if we add a multiplier or divider? What if we add a floating point unit? FP (floating point) math can take a very long time 100 s of ns for multiply and divide Lots of techniques to reduce time - will cover later on How about breaking the machine into parts? 41

42 Cost of the Single Cycle Architecture Instr Class 1 Instr Class 2 Instr Class 3 Our Cycle Time (longest Instruction) ost of the time is wasted! 42

43 ulti-cycle Solution Idea: Let the FASTEST instruction determine clock period Instr Class 1 Instr Class 2 Instr Class 3 Takes 4 cycles Takes 2 cycles Less Wasted Time 43

44 ulti-cycle Reality We are going to go further than allowing the fastest instruction to determine rate We are going to break EVERY instruction up into phases R-class Load Branch Store 44

45 IPS Architecture Instruction Classes AL Load Store Branch Jump IF mem rd mem rd mem rd mem rd mem rd ID OF op code op code op code op code op code operands operands operands operands operands 1 or 2 reg rd 2 reg rd 2 reg rd 2 regs rd PC, (immd) immd immd PC, immd immd E op addr gen addr gen cond gen addr gen mem rd mem wr addr gen RS reg wr reg wr NI PC+4 PC+4 PC+4 if cond; update PC update PC 45

46 Note That Instruction decode and register read must be done for all classes of instructions PC+4 can be done right after fetch Address generation for Jump can be performed during the decode step The same adder can be shared among: Instruction fetch logic (PC = PC + 4) Address generation logic (Address = A + IR[15:0]) Branch target calculation (Next PC = (PC + 4) + IR[15:0]) AL operations (ALOutput = A + B) Same memory port can be used to access instructions and data 46

47 IPS Architecture Instruction Classes AL Load Store Branch Jump IF ID OF mem rd mem rd mem rd mem rd mem rd PC + 4 PC + 4 PC + 4 PC + 4 PC + 4 op code op code op code op code op code operands operands operands operands operands addr gen addr gen addr gen addr gen addr gen 1 or 2 reg rd 2 reg rd 2 reg rd 2 regs rd (immd) immd immd PC, immd E op addr gen addr gen cond gen update PC if cond update PC RS NI reg wr mem rd mem wr reg wr 47

48 Also Note We need more storage There are intermediate values between each phase Examples: Place to store instruction (Instruction Register) Place to store AL output Place to store branch target Place to store operands from RegFile This is storage NOT accessible from ISA 48

49 ultiple Cycle Implementation Datapath PC[31:28] 30 Shift left 2 Jump Address Target 32 emory PC Instruction Register Read Reg1 Read Read Reg2 Data 1 Write Reg Write Data Read Data 2 A B 4 Zero AL ALOut Write Data DR Sign Extend Shift left 2 49

50 Full Diagram of ulti-cycle achine Figure

51 Recall IPS Instruction Formats R-type Instructions op rs rt rd shamt funct Load or Store or 43 rs rt immediate (address) Branch rs rt immediate (address) Jump immediate (address) 51

52 Summary Single cycle implementations have to consider the worst case delay through the datapath to come-up with the cycle time. ulticycle implementations have the advantage of using a different number of cycles for executing each instruction. In general, the multicycle machine is better than the single cycle machine, but the actual execution time strongly depends on the workload. The most widely used machine implementation is neither single cycle, nor multicycle it s the pipelined implementation. We will walk through multicycle during the next lecture. 52