Interrupt Basics Karl-Ragmar Riemschneider

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1 Interrupt Basics Exceptions and Interrupts Interrupts Handlers vs. Subroutines Accept or hold Pending: Priority control Exception vector table Example Karl-Ragmar Riemschneider

15 Exceptions in H8S/2357

16 Example for IRQ Input

17 Interrupt Controller

18 Interrupt Controller Two interrupt control Mode 0 or Mode 2: 2 interrupt control modes can be set INTM1 and INTM0 bits in the system control register (SYSCR). Priorities settable with IPR Interrupt priority register (IPR) is provided for setting interrupt priorities. 8 priority levels can be set for all interrupts except NMI. NMI is assigned the highest priority level of 8, and can be accepted at all times. Independent vector addresses All interrupt sources are assigned independent vector addresses No need for interrupt handling routine to determine the source of interrupts. Comfortable but NOT typical!! Often the handler has to find out the source of the interrupt, see daisy chain principles in the literature of other processors.) Nine external interrupts IRQ_7 to IRQ_0 + NMI Edge of interrupt signal is selectable: IRQ_7 to IRQ_0: NMI: falling edge, rising edge, or both edge detection, or level sensing. Rising edge or falling edge.

19 Interrupt Request (IRQ) Enable Register - IER Additional switch to enable/disable the IRQ lines Remark: before use one IRQ you have enable this

20 Interrupt Request (IRQ) Sense Control Registers - ISCRH, ISCRL defines the effective event or state on IRQ Pins (falling, rising edge both edges or low level)

21 Decision Chain in Mode 0

22 System Control Register SYSCR

23 System Control Register SYSCR Bit NMIEG sets the active edge (falling/rising) of the Signal which effects non maskable interrupts NMI

24 NMI

25 Interrupt Controller - discussed until now

26 System Control Register SYSCR Interrupt Control Mode 0 or 2 is set by INTM1 (and INTM0)

27 System Control Register SYSCR - Interrupt Control Mode 0 or 2 Setting of Interrupt Control Mode 0 INTM1=0 and INTM0=0 Interrupt acceptance will controlled by One single bit (I bit) in Status Register CCR [Condition Control Register] Function: I bit set to 1 = allowed interrupts I bit reset to 0 = interrupts not allowed Setting of Interrupt Control Mode 2 INTM1=1 and INTM0=0 8 interrupt priorities for: 8 external interrupts sources ( = IRQ interrupts) and 16 internal interrupts sources (on-chip supporting module interrupts). Interrupt control mode 2 is described in the following

28 Current Status with respect to Exceptions System Byte tatus Register(s) Extended Control Registe Code Condition Register User Byte

29 Current Status with respect to Exceptions sed in Trace Mode esetted in Interrupt handlers System Byte Contains the current masked priority set by program (incl. handlers) tatus Register(s) Extended Control Registe Code Condition Register Used in Interrupt Control Mode 0 User Byte

30 Handling in Interrupt Mode 0

31 Feature of Exceptions Each exception is associated with a vector number. This vector number gives the address of an exception vector table entry. An exception vector table is an array of the type long (short jump addresses). The address of an exception vector table entry is the vector number multiplied by 4. Address of an Entry in EVT = Vector number (Index of EVT) x 4. All the H8S/2357 exception handler start addresses are stored in a table of 92 longwords. This table is reaching from address 0x to 0x F.

32 Exception Vector Table

33 Content of Exception Vector Table (summarized)

34 Priority of Exception Types

35 11 Interrupt Priority Registers IPRx to set the Priority Level of 21 Exceptions Sources Initialized to 0x77 that means set highest Prio-lev Block of 3 Bit => Prio-level 0 to 7 Block of 3 Bit => Prio-level 0 to 7

36 Correspondence between interrupt sources and settings in the 11 Interupt Priority Registers IPRx

37 Interrupt Controller - discussed until now

38 Phase of Exception Handling

39 Flowchart of Interrupt Phase 1 (HW Result:...? or...? Two functions:...? and...?

40 Flowchart of Interrupt Phase 1 (HW Result: Accepted (starting handler) or Held pending (do not start handler) Two functions: 1) Highest Priority will be at started first (if there more then one with different Priorities) 2) Priority equal or or lower is not accepted (the source is set to held pending )

41 List abridged see Manual if more Info necessary How handling Interrupts with same Priorities happens at the same time?

42 Interrupt Controller - discussed until now

43 Interrupt Request Status Register ISR IRQ Status Register ISR indicates the Status of an IRQ ISR flag clearing: Cleared by reading IRQnF flag when IRQnF = 1, then writing 0 to IRQnF flag. When interrupt exception handling is executed AND low-level detection is set (IRQnSCB = IRQnSCA = 0) AND IRQn input is high (again). When IRQn interrupt exception handling is executed AND falling, rising, or both edge detection is set (IRQnSCB=1 and/or IRQnSCA = 1). These Flags block the re-entry of the own handler!

44 ISR Flag clearing

45 Memory Map in the Evaluation-Board (EVB) in Lab Firmware (download, upload, serial communication, debugg...) Not allowed to write there

46 C Areas

47 Example of Shadow EVT

48 Phase as Result of Rotation Direction

49 One Page Example -Task Task: Detect the Direction of Rotation! Input: one the digital light barrier signal for interrupting the other digital light barrier signal will be polled Output: output clockwise rotation with one LED output counterclockwise rotation with one other LED Control: stop with one manual switched High Level on one Pin

50 One Page Example S1, S0 Digital Input Signals P4(2) Stop manual switch Port(1) and P5(0) Output to LED

51 One Page Example - Rules I #include <mpp1.h> volatile unsigned char direction; pre-definitions in header files... interrupt void IRQ0hnd(void) { if(port4 & 0x01 == 0) direction = 0; else direction = 1; } define a global buffer to communicate between main() void main(void) { and IRQ0hnd P5DDR= 0x03; /* P5(1) and P5(0) as outputs */ hanges independent P5DR= 0x00; of program /* flow initialize Output Clockwise = Countercl. = 0 */ => instruction to compiler SYSCR = 0x20; /* Interrupt mode 2 */ nothing to optimize IPRA = 0x30; /* Priority 3 for IRQ_0 */ } ISCRL = 0x02; /* Rising edge of IRQ_0 */ SHADOW_IH(IRQ_0) = IRQ0hnd; /* Update shadow EVT */ SHADOW_JMP(IRQ_0)= OPCODE_JMP; /* Add the JMP instruction */ and_exr(0xf8); /* Mask level = 0 */ IER =0x01; /* Enable IRQ_0 interrupt */ do { if (direction == 0) P5DR= 0x02; /* Clockwise */ else P5DR = 0x01; /* Counterclockwise */ /*... */ /* Execute additional tasks*/ } while(port4 & 0x04 == 0); /* while no stop signal */ IER & = 0xFÉ; /* Disable IRQ_0 interrupt */

52 One Page Example - Rules II #include <mpp1.h> volatile unsigned char direction; free indentifier name no parameters! interrupt void IRQ0hnd(void) { if(port4 & 0x01 == 0) direction = 0; else direction = 1; } no return value pragma interrupt void main(void) { P5DDR= 0x03; /* P5(1) and P5(0) as outputs */ P5DR= 0x00; /* initialize Output Clockwise = Countercl. = 0 */ SYSCR = 0x20; /* Interrupt mode 2 */ IPRA = 0x30; /* Priority 3 for IRQ_0 */ ISCRL = 0x02; /* Rising edge of IRQ_0 */ SHADOW_IH(IRQ_0) = IRQ0hnd; /* Update shadow EVT */ SHADOW_JMP(IRQ_0)= OPCODE_JMP; /* Add the JMP instruction */ and_exr(0xf8); /* Mask level = 0 */ IER =0x01; /* Enable IRQ_0 interrupt */ do { if (direction == 0) P5DR= 0x02; /* Clockwise */ else P5DR = 0x01; /* Counterclockwise */ /*... */ /* Execute additional tasks*/ } while(port4 & 0x04 == 0); /* while no stop signal */ IER & = 0xFÉ; /* Disable IRQ_0 interrupt */ }

53 One Page Example - Rules III #include <mpp1.h> volatile unsigned char direction; Two bits as Outputs No output at first interrupt void IRQ0hnd(void) { if(port4 & 0x01 == 0) direction = 0; else direction = 1; } void main(void) { P5DDR= 0x03; /* P5(1) and P5(0) as outputs */ P5DR= 0x00; /* initialize Output Clockwise = Countercl. = 0 */ SYSCR = 0x20; /* Interrupt mode 2 */ IPRA = 0x30; /* Priority 3 for IRQ_0 */ ISCRL = 0x02; /* Rising edge of IRQ_0 */ SHADOW_IH(IRQ_0) = IRQ0hnd; /* Update shadow EVT */ SHADOW_JMP(IRQ_0)= OPCODE_JMP; /* Add the JMP instruction */ and_exr(0xf8); /* Mask level = 0 */ IER =0x01; /* Enable IRQ_0 interrupt */ do { if (direction == 0) P5DR= 0x02; /* Clockwise */ else P5DR = 0x01; /* Counterclockwise */ /*... */ /* Execute additional tasks*/ } while(port4 & 0x04 == 0); /* while no stop signal */ IER & = 0xFE; /* Disable IRQ_0 interrupt */ }

54 #include <mpp1.h> volatile unsigned char direction; interrupt void IRQ0hnd(void) { if(port4 & 0x01 == 0) direction = 0; else direction Determine = 1; the active edge of IRQ0 } One Page Example - Rules III Interrupt mode 2 = prioritized Interrupts Give the signal IRQ3 the priority 3 void main(void) { P5DDR= 0x03; /* P5(1) and P5(0) as outputs */ Entry pointer (start address) of a self defined handler P5DR= 0x00; /* initialize Output Clockwise = Countercl. in Shadow EVT = 0 (SVT) */ SYSCR = 0x20; /* Interrupt mode 2 */ at IRQ_O number! } IPRA = 0x30; /* Priority 3 for IRQ_0 */ ISCRL = 0x02; /* Rising edge of IRQ_0 */ write the Opcode of unconditional SHADOW_IH(IRQ_0) = IRQ0hnd; /* Update shadow EVT */ Jump Opcode before the start addresses SHADOW_JMP(IRQ_0)= OPCODE_JMP; /* Add the JMP instruction */ and_exr(0xf8); /* Mask level = 0 */ IER =0x01; /* Enable IRQ_0 interrupt */ do { if (direction == 0) P5DR= 0x02; /* Clockwise */ else P5DR = 0x01; /* Counterclockwise Write 0 */ in EXR Bit 2, Bit 1, Bit 0 /*... */ /* Execute additional tasks*/ without changes of the other bits! } while(port4 & 0x04 == 0); /* while no stop signal */ IER & = 0xFÉ; /* Disable IRQ_0 interrupt */ Last step of initialization: Enable the IRQ_0 signal

55 One Page Example - Rules IV #include <mpp1.h> volatile unsigned char direction; interrupt void IRQ0hnd(void) { if(port4 & 0x01 == 0) direction = 0; else direction Start = busy 1; waiting & output loop } void main(void) { } P5DDR= 0x03; /* P5(1) and P5(0) as outputs */ P5DR= 0x00; /* initialize Output Clockwise = Countercl. = 0 */ SYSCR = 0x20; /* Interrupt mode 2 */ IPRA = 0x30; /* Priority 3 for IRQ_0 */ ISCRL = 0x02; /* Rising edge of IRQ_0 */ SHADOW_IH(IRQ_0) = IRQ0hnd; /* Update shadow EVT */ Test the content of the global buffer Output P5DR = (binary) SHADOW_JMP(IRQ_0)= OPCODE_JMP; /* Add the JMP instruction */ Output P5DR = (binary) and_exr(0xf8); /* Mask level = 0 */ IER =0x01; /* Enable IRQ_0 interrupt */ Check one Pin: P4(2) if high leave the loop do { else loop again if (direction == 0) P5DR= 0x02; /* Clockwise */ else P5DR = 0x01; /* Counterclockwise Last */ step of using interrupts is /*... */ /* Execute additional tasks*/ disabling } while(port4 & 0x04 == 0); /* while no stop signal prevents */ not wished handler starts for the future IER & = 0xFÉ; /* Disable IRQ_0 interrupt */ (here disable the IRQ_0)

56 One Page Example - Rules IV #include <mpp1.h> volatile unsigned char direction; Start busy waiting & output interrupt void IRQ0hnd(void) { loop if(port4 & 0x01 == 0) direction = 0; else direction = 1; } void main(void) { P5DDR= 0x03; /* P5(1) and P5(0) as outputs */ Test the content of the global buffer P5DR= 0x00; /* initialize Output Clockwise = Countercl. = 0 */ SYSCR = 0x20; /* Interrupt mode 2 */ IPRA = 0x30; /* Priority 3 for IRQ_0 */ ISCRL = 0x02; /* Rising edge of IRQ_0 */ SHADOW_IH(IRQ_0) = IRQ0hnd; /* Update shadow EVT Output */ P5DR = (binary) SHADOW_JMP(IRQ_0)= OPCODE_JMP; /* Add the JMP instruction */ Check one Pin: P4(2) and_exr(0xf8); /* Mask level = 0 */ if high leave the loop IER =0x01; /* Enable IRQ_0 interrupt */ else loop again do { if (direction == 0) P5DR= 0x02; /* Clockwise */ else P5DR = 0x01; /* Counterclockwise */ Output P5DR = (binary) /*... */ /* Execute additional tasks*/ Last step of using interrupts is disabling } while(port4 & 0x04 == 0); /* while no stop signal */ (here disable the IRQ_0)

57 One Page Example - Completed #include <mpp1.h> volatile unsigned char direction; interrupt void IRQ0hnd(void) { } if(port4 & 0x01 == 0) direction = 0; else direction = 1; void main(void) { P5DDR= 0x03; /* P5(1) and P5(0) as outputs */ P5DR= 0x00; /* initialize Output Clockwise = Countercl. = 0 */ SYSCR = 0x20; /* Interrupt mode 2 */ IPRA = 0x30; /* Priority 3 for IRQ_0 */ ISCRL = 0x02; /* Rising edge of IRQ_0 */ SHADOW_IH(IRQ_0) = IRQ0hnd; /* Update shadow EVT */ SHADOW_JMP(IRQ_0)= OPCODE_JMP; /* Add the JMP instruction */ and_exr(0xf8); /* Mask level = 0 */ IER =0x01; /* Enable IRQ_0 interrupt */ do { if (direction == 0) P5DR= 0x02; /* Clockwise */ else P5DR = 0x01; /* Counterclockwise */ /*... */ /* Execute additional tasks*/ } while(port4 & 0x04 == 0); /* while no stop signal */ IER & = 0xFÉ; /* Disable IRQ_0 interrupt */ }

58 Golden Rules for Exception Handler Writing Don t modify any general purpose register CPU pushes no registers automatically for interrupts! Assembler: Push the needed registers (and pop them at end - under all circumstances) C: Use local Variables only if really needed (Interrupt latency time!!) Keep Handlers short! Avoid Nested Interrupts! => Priority /Level change in Handler could be dangerous Don t forget Re-enable or Unmask Interrupts!!! Assembler : Use the proper Return instruction RTE => NOT RTS!! Stop Interrupts if not more in use

Exceptions in H8S/2357. Exercise Interrupts "Traffic Light Controller"

Exceptions in H8S/2357. Exercise Interrupts Traffic Light Controller Exceptions in H8S/2357 Exercise Interrupts "Traffic Light Controller" - Principles Time Based Event Handling - Implementation H8S/2357 as Internal TPU Controlled Interrupts - Recapitulation - Handling