Custom computing systems

Transcription

1 Custom computing systems difference engine: Charles Babbage compute maths tables digital orrery: MIT special-purpose engine, found pluto motion chaotic Splash2: Supercomputing esearch Center multi-fpga engine, for video processing, DNA computing etc Harp1: Oxford University FPGA + microprocessor (transputer) SONIC, UltraSonic: Sony + Imperial College multi-fpga, professional video processing MaxWorkstation, MaxNode: 2011, Max5: FPGA cards adopted by JP Morgan, Amazon wl

2 The Exaflop Supercomputer (2018) 1 exaflop = FLOPS (TaihuLight: 93 Petaflops) using processor cores with 8FLOPS/clock at 2.5GHz 50M CPU cores what about power? - assume power envelope of 100W per chip - Moore s Law scaling: 6 cores today ~100 cores/chip - 500k CPU chips 50MW (just for CPUs!) 100MW likely TaihuLight power consumption: 15MW source: Maxeler wl

3 The Exaflop Supercomputer (2018) 1 exaflop = FLOPS How do we program this? using processor cores with 8FLOPS/clock at 2.5GHz 50M CPU cores what about power? - assume power envelope of 100W per chip - Moore s Law scaling: 6 cores today ~100 cores/chip - 500k CPU chips 50MW (just for CPUs!) 100MW likely TaihuLight power consumption: 15MW Who pays for this? source: Maxeler wl

4 Technology comparison DSP: Digital Signal Processor Dedicated HW=ASIC/FPGA wl

5 I/O and QPI Uncore Intel 6-Core X5680 Westmere Execution Computation units Out-of-order scheduling & retirement L1 data cache Memory ordering and execution Instruction decode and microcode L2 Cache & interrupt servicing Paging Branch prediction Instruction fetch & L1 cache Core Memory controller Core Core Core Core Core Core Shared L3 cache Shared L3 cache I/O and QPI wl

6 A special purpose computer a chip customised for a specific application no instructions no instruction decode logic no branches no branch prediction explicit parallelism no out-of-order scheduling data streamed onto-chip no multi-level caches est of the world MyApplication Chip (Lots of) Memory source: Maxeler wl

7 A special purpose computer but we have more than one application impractical to optimise machines for only one application - need to run many applications in a typical system est of the world Network Network Network OtherApplication MyApplication MyApplication Chip MyApplication Chip Chip Chip Memory Memory Memory Memory source: Maxeler wl

8 A special purpose computer use reconfigurable chip: reprogram at runtime to implement: - different applications, or - different versions of the same application Network Optimized for Config 1 Application AD BC E Memory source: Maxeler wl

9 Instruction processors source: Maxeler wl

10 Dataflow/stream processors source: Maxeler wl

11 Accelerating real applications CPUs are good for: - latency-sensitive, control-intensive, non-repetitive code dataflow engines are good for: - high throughput repetitive processing on large data volumes a system should contain both Lines of code Total Application 1,000,000 Kernel to accelerate 2,000 Software to restructure 20,000 source: Maxeler wl

12 Dimms Custom computing in a PC Processor egister file L1$ L2$ North/South Bridge PCI Bus Disk where is the Custom Architecture? on-chip with access to register file co-processor w/ access to level 1 cache next to level 2 cache in adjacent processor socket, connected using QPI/Hypertransport as Memory Controller not North/South Bridge as main memory (DIMMs) as a peripheral on PCI Express bus inside peripheral, eg customizable Disk controller wl

13 Custom Architecture Embedded systems Instructions Processor egister file Data partition programs into software and hardware (custom architecture) - hardware software co-design System-on-Chip: SoC (cover later) custom architecture as extension of the processor instruction set wl

14 Where to locate custom architecture? depends on the application - avoid system bottleneck for the application possible bottlenecks - memory access latency - memory access bandwidth - memory size - processor local memory size - processor ALU resource - processor ALU operation latency - various bus bandwidths wl

15 Bottleneck example: Bing page ranking source: Microsoft wl

16 econfigurable computing with FPGAs Logic Cell (10 5 elements) Xilinx Virtex-6 FPGA DSP Block IO Block Block AM DSP Block Block AM (20TB/s) wl

17 High density compute with FPGAs: examples 1U Form Factor for racks DFE: Data Flow Engine source: Maxeler wl

18 How could we program it? schematic entry of circuits hardware Description Languages - VHDL, Verilog, SystemC object-oriented languages - C/C++, Python, Java, and related languages dataflow languages: e.g. MaxJ, OpenSPL functional languages: e.g. Haskell, uby high level interface: e.g. Mathematica, MatLab schematic block diagram e.g. Simulink domain specific languages (DSLs) wl

19 Level of Abstraction Accelerator programming models DSL DSL DS L DSL Higher Level Libraries Higher Level Libraries Flexible Compiler System: MaxCompiler/uby Possible applications wl

20 Start Acceleration development flow Original Application Identify code for acceleration and analyze bottlenecks Transform app, architect and model performance Write accelerator code Integrate with Host code Simulate NO NO Accelerated Application YES Meets performance goals? Build for Hardware YES Functions correctly? source: Maxeler wl

21 Start Acceleration development flow Original Application Identify code for acceleration and analyze bottlenecks Transform app, architect and model performance Write accelerator code Integrate with Host code Simulate Mainly for project NO NO Accelerated Application YES Meets performance goals? Build for Hardware YES Functions correctly? source: Maxeler wl

22 Customisation techniques FPGA technology offers customisation opportunities - some data may remain constant: e.g. algebraic simplification - adopt different data structures: e.g. number representation - transform: e.g. enhance parallelism, pipelining, serialisation reuse possibilities (more next lecture) - description: repeating unit, parametrisation - transforms: patterns, laws, proofs example: polynomial evaluation for numbers a i, x y = a 0 + a 1 x + a 2 x 2 + a 3 x 3 (repeat many times) wl

23 Performance estimation clocked circuit: no combinational loops gates have delay, and speed limited by propagation delay through the slowest combinational path slowest path: usually carry path clock rate: approx. 1/(delay of slowest path) assuming - edge-triggered design - register propagation delay, set-up time, clock skew etc assumed negligible lowest level: logic gates, do not worry about transistors wl

24 First polynomial evaluator compute y = a 0 + a 1 x + a 2 x 2 + a 3 x 3 simplification: assume x constant a 3 a 2 + y = 0 ; for i = y = y + a i x x i ; a 1 + a 0 problems: speed? size? repeating units? + y wl

25 Customisation possibilities 1. exploit algebraic properties 2. enhance parallelism 3. pipelining Other possibilities serialisation customise data representation - non-standard word-length, e.g. 18 bits rather than 32 bits - non-standard arithmetic, e.g. logarithmic, residue wl

26 1. Algebraic property: Horner s ule given b a b + a + a x + b x = (a + b) x then a 3 a 3 a 2 + a 2 + a 1 + a 1 + a 0 + a 0 + a 0 + a 1 x + a 2 x 2 + a 3 x 3 = a 0 + x (a 1 + x (a 2 + a 3 x)) wl

27 2. Enhance parallelism wl

28 3. Pipelining split up combinational circuit: add pipeline registers shorter cycle time, assembly-line parallelism, lower power pipelined design (if regular: systolic array more later) - mandatory: same number of additional registers for all inputs - preferable: balance delay in different stages - preferable: addition of registers preserves regularity f g h Source: M Spivey wl

29 Horner s ule for pipelining? given Q P Q then P and Q are registers, is computational component Q Q Q Q Q P P P Q wl

30 Pipelined incrementer: Verilog parameterize: - G groups of N bits - width = G*N - bits per stage = N 1-stage pipeline cin a[15..12] incrementer a[11..8] incrementer a[7..4] incrementer a[3..0] incrementer cout Verilog implementation: - decompose into: upper register triangle chain of incrementers + register (1-stage pipeline) lower register triangle - only top level shown - need to manage array indices sum[15..12] sum[11..8] sum[7..4] sum[3..0] module incr_pipe #(parameter G=4,N=4) // G groups of N bits (output [G*N-1:0] outp, input [G*N-1:0] inp, input clk); wire [G:0] carry; // carry chain wire [G*N-1:0] temp1; // output of delay triangle genvar i; // loop counter assign carry[g] = 1; // prime carry input upper_tri_delay #(G, N) tru (temp1, inp, clk); // upper reg triangle lower_tri_delay #(G, N) trl (outp, temp2, clk); // lower reg triangle generate for (i = 0; i < G; i = i + 1) // for each group generate begin // 1-stage pipelined incrementer incr_stage #(N) istg (carry[g-i-1], temp2[(i+1)*n-1:i*n], temp1[(i+1)*n-1:i*n], carry[g-i], clk); end endgenerate endmodule wl

31 Concise parametric representation given Q P Q then [P, Q] ; = ; Q, P and Q are registers Q Q Q Q Q P P P Q [ n P, Q n ] ; rdr n = rdr n ( 2 Q ; ) wl

32 Pipelined incrementer: Verilog vs uby parameterize: - G groups of N bits - width = G*N - bits per stage = N cin a[15..12] incrementer a[11..8] incrementer a[7..4] incrementer a[3..0] incrementer cout Verilog: sum[15..12] sum[11..8] sum[7..4] sum[3..0] module incr_pipe #(parameter G=4,N=4) // G groups of N bits (output [G*N-1:0] outp, input [G*N-1:0] inp, input clk); wire [G:0] carry; // carry chain wire [G*N-1:0] temp1; // output of delay triangle genvar i; // loop counter assign carry[g] = 1; // prime carry input upper_tri_delay #(G, N) tru (temp1, inp, clk); // upper reg triangle lower_tri_delay #(G, N) trl (outp, temp2, clk); // lower reg triangle generate for (i = 0; i < G; i = i + 1) // for each group generate begin // 1-stage pipelined incrementer incr_stage #(N) istg (carry[g-i-1], temp2[(i+1)*n-1:i*n], temp1[(i+1)*n-1:i*n], carry[g-i], clk); end endgenerate endmodule uby: Pipelined_incrementer G N = snd (tri G (tri N D)) ; # upper reg triangle row G (row N (halfadd ; snd D) ; # 1-stage pipelined incre fst (tri~ G (tri~ N D)) # lower reg triangle * can generate Verilog or MaxJ! wl