Advanced Computer Architecture
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1 Fiscal Year 2018 Ver a Course number: CSC.T433 School of Computing, Graduate major in Computer Science Advanced Computer Architecture 1. Design and Analysis of Computer Systems Room No.W936 Mon 13:20-14:50, Thr 13:20-14:50 Kenji Kise, Department of Computer Science kise _at_ c.titech.ac.jp CSC.T433 Advanced Computer Architecture, Department of Computer Science, TOKYO TECH 1
2 Syllabus (1/3) CSC.T433 Advanced Computer Architecture, Department of Computer Science, TOKYO TECH 2
3 Syllabus (2/3) CSC.T433 Advanced Computer Architecture, Department of Computer Science, TOKYO TECH 3
4 Processor fabrication: ingot and wafer CSC.T433 Advanced Computer Architecture, Department of Computer Science, TOKYO TECH 4
5 Processor fabrication: wafer and die Die Intel, Industry-Leading Transistor Performance Demonstrated on Intel s 90-nanometer Logic Process CSC.T433 Advanced Computer Architecture, Department of Computer Science, TOKYO TECH 5
6 Processor fabrication: die and packaging Die CSC.T433 Advanced Computer Architecture, Department of Computer Science, TOKYO TECH 6
7 The birth of microprocessors Name Year # of transistors Intel ,250 CSC.T433 Advanced Computer Architecture, Department of Computer Science, TOKYO TECH 7
8 Moore s Law Moore's law is the observation that the number of transistors in a dense integrated circuit doubles about every two years. The observation is named after Gordon Moore, the co-founder of Fairchild Semiconductor and Intel, whose 1965 paper described a doubling every year in the number of components per integrated circuit, and projected this rate of growth would continue for at least another decade. In 1975, looking forward to the next decade, he revised the forecast to doubling every two years. The period is often quoted as 18 months because of a prediction by Intel executive David House (being a combination of the effect of more transistors and the transistors being faster). WIKIPEDIA CSC.T433 Advanced Computer Architecture, Department of Computer Science, TOKYO TECH 8
9 Moore s Law CSC.T433 Advanced Computer Architecture, Department of Computer Science, TOKYO TECH 9
10 Moore s Law CSC.T433 Advanced Computer Architecture, Department of Computer Science, TOKYO TECH 10 10
11 Growth in clock rate of microprocessors From CAQA 5 th edition CSC.T433 Advanced Computer Architecture, Department of Computer Science, TOKYO TECH 11
12 Clock rate is mainly determined by Switching speed of gates (transistors) The number of levels of gates The maximum number of gates cascaded in series in any combinational logics. In this example, the number of levels of gates is 3. Wiring delay and fanout Register AND gate OR gate AND gate Register CSC.T433 Advanced Computer Architecture, Department of Computer Science, TOKYO TECH 12 12
13 Growth in processor performance From CAQA 5 th edition CSC.T433 Advanced Computer Architecture, Department of Computer Science, TOKYO TECH 13
14 Which is faster? From Tokyo to Hiroshima Time & Cost Max Speed Passengers Throughput (Speed x P) Boeing 737 1:20 32,000yen 800km/h (503km/h) ,510 (503 x 170) Nozomi 4:00 18,000yen 270km/h (205km/h) 1, ,500 (205 x 1,300) Time to run the task (ExTime) Execution time, response time, latency Tasks per day, hour, week, sec, ns (Performance) Throughput, bandwidth Based on the lecture slide of David E Culler CSC.T433 Advanced Computer Architecture, Department of Computer Science, TOKYO TECH 14
15 Defining (Speed) Performance Normally interested in reducing Response time (execution time) the time between the start and the completion of a task or a program Important to individual users Thus, to maximize performance, need to minimize execution time performance X = 1 / execution_time X If X is n times faster than Y, then performance X execution_time Y = = n performance Y execution_time X Throughput the total amount of work done in a given time Important to data center managers Decreasing response time almost always improves throughput CSC.T433 Advanced Computer Architecture, Department of Computer Science, TOKYO TECH 15
16 Performance Factors Want to distinguish elapsed time and the time spent on our task CPU execution time (CPU time) : time the CPU spends working on a task Does not include time waiting for I/O or running other programs CPU execution time # CPU clock cycles = x clock cycle time for a program for a program CPU execution time # CPU clock cycles for a program = for a program clock rate Can improve performance by reducing either the length of the clock cycle or the number of clock cycles required for a program or CSC.T433 Advanced Computer Architecture, Department of Computer Science, TOKYO TECH 16
17 Performance Factors CPU execution time # CPU clock cycles for a program = for a program clock rate Performance = clock rate x 1 / # CPU clock cycles for a program Performance = f x IPC f: frequency (clock rate) IPC: retired instructions per cycle int flag = 1; int foo(){ while(flag); } CSC.T433 Advanced Computer Architecture, Department of Computer Science, TOKYO TECH 17
18 Syllabus (3/3) CSC.T433 Advanced Computer Architecture, Department of Computer Science, TOKYO TECH 18
19 From multi-core era to many-core era Platform 2015: Intel Processor and Platform Evolution for the Next Decade, 2005 CSC.T433 Advanced Computer Architecture, Department of Computer Science, TOKYO TECH 19
20 Pollack s Rule Pollack's Rule states that microprocessor "performance increase due to microarchitecture advances is roughly proportional to the square root of the increase in complexity". Complexity in this context means processor logic, i.e. its area. WIKIPEDIA CSC.T433 Advanced Computer Architecture, Department of Computer Science, TOKYO TECH 20
21 From multi-core era to many-core era Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction, MICRO-36 CSC.T433 Advanced Computer Architecture, Department of Computer Science, TOKYO TECH 21
22 Intel Sandy Bridge, January to 8 core CSC.T433 Advanced Computer Architecture, Department of Computer Science, TOKYO TECH 22 22
23 Intel Skylake-X, Core i9-7980xe, core CSC.T433 Advanced Computer Architecture, Department of Computer Science, TOKYO TECH 23
24 Syllabus (3/3) CSC.T433 Advanced Computer Architecture, Department of Computer Science, TOKYO TECH 24
25 Homework 1 1. Install Icarus Verilog 2. Install GTKWave 3. Simulate the behavior of a 4-bit counter (sample circuit 1) using Icarus Verilog, and confirm the waveforms using GTKWave. 4. Modify the circuit and HDL code for another typical circuit (like a decoder, LFSR and ALU), then simulate and confirm the waveforms. 5. Submit a report printed on A4 paper at the beginning of the next lecture. The report should include a block diagram, a source code in Verilog HDL, and obtained waveforms of your circuit. CSC.T433 Advanced Computer Architecture, Department of Computer Science, TOKYO TECH 25 25
26 Icarus Verilog for Windows Installing Verilog HDL Simulation Environment (Windows) CSC.T433 Advanced Computer Architecture, Department of Computer Science, TOKYO TECH 26
27 GTKWave, wave viewer Installing GTKWave CSC.T433 Advanced Computer Architecture, Department of Computer Science, TOKYO TECH 27
28 Sample circuit 1 4-bit counter synchronous reset negative-logic reset, initialize or reset the value of register cnt to zero if RST_X is low module counter CLK RST_X cnt [3:0] 4 cnt CSC.T433 Advanced Computer Architecture, Department of Computer Science, TOKYO TECH 28
29 Sample Verilog HDL Code counter.v 8 module top(); 9 reg CLK, RST_X; 10 wire [3:0] w_cnt; initial begin CLK = 1; forever #50 CLK = ~CLK; end 13 initial begin RST_X = 0; #240 RST_X = 1; end 14 initial #800 $finish(); 15 initial begin 16 $dumpfile("wave.vcd"); 17 $dumpvars(0, cnt1); 18 end 19 CLK) $write("cnt1: %d %x n", RST_X, w_cnt); counter cnt1(clk, RST_X, w_cnt); 22 endmodule /**************************************************************************/ 25 module counter(clk, RST_X, cnt); 26 input wire CLK, RST_X; 27 output reg [3:0] cnt; CLK) begin 30 if(!rst_x) cnt <= #5 0; 31 else cnt <= #5 cnt + 1; 32 end 33 endmodule CSC.T433 Advanced Computer Architecture, Department of Computer Science, TOKYO TECH 29
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