Task 8: Extending the DLX Pipeline to Decrease Execution Time

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1 FB Elektrotechnik und Informationstechnik AG Entwurf mikroelektronischer Systeme Prof. Dr.-Ing. N. Wehn Vertieferlabor Mikroelektronik Modelling the DLX RISC Architecture in VHDL Task 8: Extending the DLX Pipeline to Decrease Execution Time Introduction Within this lab test, the following goals shall be achieved: Analyse assembler source code to identify potential optimisations Implement optimisations in DLX VHDL model Adapt source code to embed optimisations Test and verify VHDL model using ModelSim Synthesize extended DLX VHDL model Compare speedup and additional hardware usage Analysing the Assembler Source Code Please analyse the following assembler source code that is used in the traceback routine of the Viterbi Algorithm: srl andi r10,r10,r12 r10,r10,1 ;Rightshift of decision byte ;Mask all bits except the LSB slli add andi r12,r12,1 r12,r12,r10 r12,r12,3 ;Leftshift traceback bit pointer ;Add decision bit to traceback bit pointer ;Mask all bits except 30 and 31 of traceback bit pointer Specify two new instructions that modify the contents of registers R10 and R12 in the same way as the two code blocks above do. The name of the first instruction needs to be SLM for Shift Left and Mask. The instruction format is specified by Figure 1: Figure 1: Instruction Format of SLM instruction

2 2 The second instruction is called SRM for Shift Right and Mask. The instruction format is specified by Figure 2: Figure 2: Instruction Format of SRM instruction Another frequently used sequence of instructions is the following code that is used to compute the branch metric: xori addi srli r14,r1,3 r12,r14,1 r12,r12,1 ;Compute Hamming Distance for S0 -> S2 Develop prior to the lab test the specifications of a single instruction that computes the Hamming Distance for a given output register, the actual received symbol as one operand and the value of the possible symbol as immediate (Note: The possible symbol is the output of the encoder for a certain state transition, eg. S(0) -> S(2) => Possible symbol = 112 = 310). The name of the instruction must be BMCI for Branch Metric Calculation Immediate. The instruction format is specified in Figure 3. Figure 3: Instruction Format of BMCI instruction Implementing the Optimisations in VHDL After you specified the three new instructions, the DLX VHDL model needs to be extended to be able to perform the new instructions and hence decrease execution time of the Viterbi Algorithm. The VHDL model of the DLX architecture was developed by Gilbert, Neeb and Vogt of the Department of Electrical Engineering and Information Technology in The structure of the DLX VHDL model is depicted in Figure 4.

3 3 Figure 4: Structure of DLX VHDL Model The VHDL model consists out of four global packages. The package dlx_global.vhd defines types, subtypes and constants that are used globally, e.g. the instruction formats. The opcode package dlx_opcode_package.vhd assigns a binary value to each DLX instruction. The testbenches dlx_cache_testbench.vhd and dlx_testbench.vhd generate a clock signal and load a program to the memory from a file. The debug module dlx_debug.vhd writes a string for each instruction. The actual implementation of the DLX architecture starts with the top level module dlx_cpu.vhd. This module instantiates pipeline, instruction and data cache and the memory controller as well as all signals that are used to interconnect these modules. The module dlx_memctrl.vhd is the interface between memory and data and instruction caches. The behaviour of the data and instruction caches is defined by the modules dlx_dcache.vhd and dlx_icache.vhd, the actual hardware implementation of the caches are LUT-RAMs which are specified in the module cache_memory_sim.vhd. The module dlx_pipeline.vhd instantiates the pipeline controller, the register file specified by regfile_sim.vhd and the pipeline stages instruction fetch (dlx_pipe_if.vhd), instruction decode (dlx_pipe_id.vhd), execution (dlx_pipe_ex.vhd) and memory (dlx_pipe_mem.vhd) which includes the write back stage. Furthermore, all signals that interconnect the pipeline stages are defined. To extend the instruction set of the DLX architecture, three modules become relevant: First, the additional instructions need to be defined in the opcode package. This is a requirement because otherwise, the pipeline stage instruction decode could not recognize the instruction. The opcodes are depicted in Figures 1 to 3. The instruction decode package specifies which operation with which operands the following execution stage is going to perform. Hence, the actual operation of an instruction is specified in the execution package. Implement the three new instructions in the corresponding packages as explained above. Adapting Source Code After you implemented the new instructions in the VHDL model, the source code needs to be adapted to embed the new instructions. Browse to the directory Lab_Test_8\DLX_VHDL\asm and open the file VA.S using nedit. Enter your source code for the BMCI instruction between the specified labels in lines 57 to 60. The source code for the SLM and SRM instructions needs to be entered between lines 196 and 199.

4 4 Test and verify VHDL model using ModelSim After completing the source code, the binaries for the simulation need to be generated. The assembler is started from the terminal with the command: python asm.py [VA.s]. Subsequently, the source code and the extended DLX VHDL model can be tested. For this purpose, again ModelSim is used. After starting ModelSim with the command vsim &, all.vhdl-files need to be compiled. After the compilation, the simulation can be started. Browse the library window and start the test bench by a double click on dlx_tb. As simulation time, choose 1400µs. If your source code performed the Viterbi Algorithm correctly, the values stored in the memory (signal /dlx_tb/mem/ram) at addresses need to be identical as shown in the screenshot below: Please measure the effective execution time between fetching the first instruction and writing back the result of the last instruction. As the cycle time within the simulation is set to 50ns, you can compute the number of cycles needed to execute the Viterbi Algorithm for the 320 bit exemplary message. DLX w/o extensions DLX with extensions Number of Cycles Instructions per decoded bit Synthesizing the VHDL Model Following to the successful simulation, the DLX VHDL model can be synthesized to measure the additional hardware cost within an actual implementation on an FPGA. To start the synthesizing, the program ISE is utilized. Start it from the console with the command ise & and

5 5 create a new project. Use for target technology the Virtex 4 device family with the part xc4vlx100 with speedgrade -11 and package ff1148. All required.vhd files have to be added to the project. As first step, the synthesis needs to be performed. This process is initiated within the navigation menu on the left side as depicted in the screenshot. After the synthesis, the place and route can be performed. Following to the successful place&route, a report shows the number of used slices, the number of slice flip flops and 4input LUT's. Please note these numbers in the table below: DLX w/o extensions DLX with extensions Number of Slices Number of Slice Flip Flops Number of 4 Input LUTs Thereof Logic Cycle Time [ns] Frequency [MHz] Comparison of Speedup and Additional Hardware Usage Subsequent to the successful synthesis, the speedup needs to be compared to the additional hardware consumption. Please calculate the speedup and the relative increase in hardware usage:

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