EE 361L Digital Systems and Computer Design Laboratory

Transcription

1 University of Hawaii Department of Electrical Engineering EE 361L Digital Systems and Computer Design Laboratory Timing Simulation Version /10/2003 This document is a quick tutorial on performing Timing simulation. First, let us take a quick look at the design flow in Figure-1. Design Problem HDL model of a circuit Design Circuit Synthesize model to get a gate level description Verify/Simulate Functionality (Debugging) HDL model of a circuit (functional model) Verify/Simulate Logic and Timing Implement in hardware Make sure design is consistent in hardware Figure-1: Design Flow. Note that functional simulation tests only the functionality of your design, i. e. the correctness of the outputs in your design with respect to the inputs. However, your

2 circuits have to be implemented using real gates, flip-flops and interconnects with delays and non-ideal behavior, and you have to validate your design for the timing specifications. Note that when you synthesize your design and do a Placement/Route, you make use of vendor libraries that include timing models for their designs. Here is an example. Consider Figure-2(a), that provides an ideal model of an OR gate. When you use this gate, you only consider the functionality. Consider Figure-2(b), which consists of models of OR gates from vendors. Note that the first gate has a propagation delay of 1 ms, while the second gate has a propagation delay of 3 ms. Suppose your synthesis used the OR gate with 3ms delay and that is unacceptable to your timing requirements, you can constrain the synthesis tool to use the OR gate with 1ms delay. Propagation delay= 1ms Propagation delay= 3ms (a) Ideal OR gate - Functional model (b) OR gates from vendor libraries Figure-2: Simple example of Timing model. Now, let us consider using the ModelSim tool to perform a timing simulation for your design. This tutorial assumes that you already have synthesized your design and you are using the Xilinx FPGAs to implement your design. Also, note that this tutorial uses the design project from the Webpack tutorial. STEP 1: After you have synthesized the design in <<SetLed.v>> using Xilinx WebPack and performed a Place-and-Route, generate a PAR simulation model as shown in Figure- 3. This operation creates two files, <<display_timesim.v>> & <<display_timesim.sdf>>. The <<display_timesim.v>> is a verilog description of your design, which makes use of Xilinx libraries. The SDF stands for Standard Delay Format. SDF Output Files contain timing delay information that allow you to perform back-annotation for simulation with standards-compliant VHDL and Verilog HDL simulators; and timing analysis and resynthesis with synthesis tools.

3 Note: This process generates warnings during the process. For successful simulation, look for the file <<glbl.v>> in the following path $/verilog/src/ at the Xilinx install directory. Figure-3: Generating PAR Simulation model. STEP 2: Add the files <<display_timesim.v>> and the <<glbl.v>>, along with the testbench for your design. Note that you might have to change the order of signals in the design instantiation in your test-bench. Compile all the files as in Figure-4.

4 Figure-4: Compiling the source files. STEP 3: Before you can simulate your design, you have to include the SDF file from the Xilinx WebPACK. To add the file, click on the Simulate icon and follow steps shown in Figure-5. After you add the file, you should get a screen as in Figure-5(a). (a)

5 (b) Figure-5: Adding SDF file. STEP 4: Loading your design is similar to functional simulation. However, you have to know all the design libraries to be included (similar to the.h files in C programming). Click on all the designs in the WORK library. Also click on the SIMPRIMS_VER and UNISIM_VER libraries, as shown in Figure-6, to load your design. Figure-6: Loading your design. ModelSim also accepts command-line arguments and lets you scripting such as TCL. Here is an example, below:

6 vsim -L simprims_ver -L unisims_ver sdftyp C:/temp/361/Lab4/test/display_timesim.sdf -sdfnoerror work.display work.glbl work.test_display The above command performs the same function as STEPS 3-4. For more information, please refer to the Help and manuals from ModelSim. Note that these scripts are very useful and used by professionals extensively, as scripts can preserve the settings for compilation. However, the GUI approach is very convenient for beginners and students. An example of successful compilation is shown in Figure-7. If your design is satisfactory (both functionality & timing), you can generate the programming bits for the FPGA and load the gate array with your design. Figure-7: Simulation.