Vivado Synthesis Tips & Tricks
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1 Vivado Synthesis Tips & Tricks Presented By Balachander Krishnamurthy Sr. Product Marketing Manager October 2 nd, 2018
2 Topics for Today The UltraFast Design Methodology UFDM: Customer Case Study Waiver Mechanism Vivado Incremental Synthesis QoR: Tips & Tricks 2
3 UltraFast Design Methodology 3
4 UG1292: UFDM Timing Closure Quick Reference Card Step-by-step Analysis and Suggestions Address common timing closure challenges HLx and SDx Project and Non-project 6
5 Report Run Strategies Create custom report strategies similar to custom run strategies Improve compile time Select which reports are generated for each run Configure options for each report individually Reuse report strategies across runs and projects 5
6 UFDM: Customer Case Study 7
7 Customer Case Study: Design not functional Major Xilinx customer with tight production deadline Customer claimed Running place_design -fanout_opt caused functional issue Adding ILA to DCP, design issue is gone Not a CDC issue OneSpin equivalency checking is clean opt_design DCP compared with place_design DCP SR filed and escalated to factory 8
8 Customer Case Study: Analysis by factory Many UltraFast Methodology Violations Timing -1 Incorrect clock waveform Timing-3 Breaking clock propagation delay and potentially skew accuracy Timing-6, 27 Primary clock defined on hierarchical pin Timing-36 Inaccurate skew due to missing insertion delay on a generated clock 9
9 Customer Case Study: Analysis by factory 2 Report CDC flagged ~10K Critical violations! WE Waivers can help focus on new or un-reviewed issues CDC-11 violations introduced by placer fanout opt User allowed replication of CDC endpoint (RAMB/WE control signal) => RAMBs written in different cycles Safe CDC topology would have prevented replication Outcome Design working after addressing methodology and CDC violations 10
10 Waiver Mechanism 11
11 Waiver Mechanism Hide violations in CDC/DRC/Methodology checks in the design Focus only on what is relevant Waivers can be created, queried, reported against and deleted Track user, timestamp and description Waivers should be reviewed by the design team XDC Compatible, allows read/write and scoping Duplicate waivers ignored Recommend Don t waive Critical violations Waive Warning (after reviewing them) and Info types Xilinx IPs have adopted waiver mechanism Documentation UG906: Design Analysis and Closure Techniques UG938: Tutorial Design Analysis and Timing Closure (NEW) 12
![STARTPOINT_PIN $vio]]} { create_waiver -of $vio -description {Safe by protocol} } } Create from: manual specification of all arguments](/docs-images/93/114140498/images/12-2.jpg "Arguments are order dependent.")
12 Creating a Waiver Create from: Report CDC / DRC / Methodology result window Create from: CDC / DRC / Methodology violation objects report_cdc -name cdc_1 foreach vio [get_cdc_violations -name cdc_1 -filter {CHECK == CDC-1}] { if {[regexp {^top/sync_1} [get_property STARTPOINT_PIN $vio]]} { create_waiver -of $vio -description {Safe by protocol} } } Create from: manual specification of all arguments Arguments are order dependent. They must match order inside the violation object Notice: only description argument specified with this method. 13
13 Reporting Waivers In Report CDC / DRC / Methodology GUI (and command line) Report can be generated with the waivers Report can be generated by ignoring the waivers Can report only waived violations report_waivers Only Text Based GUI Support coming soon Report CDC/DRC/Methodology must be run prior to extract statistics Useful Waiver Commands create_waiver get_waivers delete_waivers write_waivers report_waivers 14
14 Vivado Incremental Synthesis 15
15 Incremental Synthesis Flow similar to incremental P & R Benefits: 40% synthesis runtime reduction Change is localized Iterate quickly while working on a module More design iterations in the front end Improved predictability in results Fewer changes in netlist structure when compared to previous flow Improved results/qor/runtime when used with Incremental P & R Reference Run Reference RTL synth_design write_checkpoint incremental_synth synth.incr.dcp RTL Change Synthesis Reference Checkpoint Incremental Run Revised RTL read_checkpoint incremental synth.incr.dcp synth_design 16
16 Incr. Synthesis - Cross-Boundary Optimizations Reference Run Track cross-boundary optimizations Incremental Run Re-synthesize changed modules + its dependencies Top Module (M) Top Module (M ) M 4 M 1 M 4 M 1 G 4 M 3 G 1 G 4 M 3 G 1 G 1 G 3 G 2 G 3 G G 2 M c More cross boundary optimizations leads to more re-synthesis (G 1 G 2) Changed / dissolved partitions also need to be re-synthesized 18
17 19 Log file and Non-Project Mode Flow Report has 4 sections 1. Incremental synthesis was run or Not 2. Changed Modules and %Resynthesis 3. Check point details 4. RTL partitions (Reuse and Resynthesis) Reference run run.tcl synth_design write_checkpoint incremental_synth force postsynth.dcp opt_design place_design Phys-opt_design optimizations1 route_design Incremental run write_checkpoint routed.dcp Phys-opt_design optimizations2 write_checkpoint ref_run_postroute_physopt.dcp run.tcl read_checkpoint incremental../referencerundir/postsynth.dcp synth_design write_checkpoint incremental_synth force postsynth_incr.dcp opt_design read_checkpoint incremental../referencerundir/ref_run_postroute_physopt.dcp optimizations1 + optimizations2 place_design route_design write_checkpoint routed_incr.dcp
18 QoR: Tips & Tricks 20
19 Tips and Tricks: ROM Optimization 64-deep ROM, 4-bit wide accessing different locations Loop with 30 iterations 10 ROM structures per iteration (300 ROMs in total) Data in 0-15 repeated in and Could this be 16 deep instead of 64 deep? Missing uniformity in ROM data => 64 th location 21
20 Tips and Tricks: ROM Optimization Check the condition to access the data for address#63 The ROM now can become 16-deep and 4-bit wide 22 LUT difference = Original Proposed ( ) = 1261
21 Tips and Tricks: 500 MHz Wide Multiplier Tip: Review log file 36 DSP s for 100x100 multiplier Not meeting timing, needs pipeline registers 8 pipeline registers needed for timing closure 24
22 Tips and Tricks: Multiplier => LUT mapping With max_dsp 0 Higher utilization v/s competition for multipliers Need to compare LUT based mapping Map to DSP (use_dsp48 = no ) Convert to LUT based (-max_dsp 0) With use_dsp48 = no attribute 25
23 Summary Following the UltraFast Design Methodology reduces Time-to-Market Waiver Mechanism for CDC, Methodology and DRCs enables clean reports and design sign-off Ensure Clock Domain Crossing issues are reviewed and fixed Use the waiver mechanism to focus on real issues Vivado Incremental synthesis reduces compile time Reach out to your FAE for details/issues 26
24
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