NEXYS4DRR board tutorial
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1 NEXYS4DRR board tutorial (VHDL Decoder design using Vivado ) Note: you will need the Xilinx Vivado Webpack version installed on your computer (or you can use the department systems). This tutorial shows how to create a simple combinational design (a 3 to 8 decoder using the slider switches and LEDs) that can be implemented on the Nexys4DDR board. Start Vivado Design Suite: Select Create New Project. Click Next and then enter a Project name and location for your project: Click Next and select the RTL project type: Copyright 2015 R James Duckworth, WPI 1 Rev A
2 Check the Do not specify courses at this time box and click Next: Select the corect Xilinx FPGA that is on the Nexys4DDR board (XC7A100T-1CSG324C): Copyright 2015 R James Duckworth, WPI 2 Rev A
3 Click Next, and then Finish: The Project window opens: We now need to add a VHDLg design source to describe our decoder operation. Click on Add Sources in the left Project Manager window (or select the menu item File => Add Sources: Copyright 2015 R James Duckworth, WPI 3 Rev A
4 Select Next, And then select Create File (click on the + symbol) and enter decoder for the file name: Make sure the file type is set to VHDL Then click OK and Finish. We can now specify the inputs and outputs to create our 3 to 8 decoder (we will use three switches and eight LEDs): Copyright 2015 R James Duckworth, WPI 4 Rev A
5 Click OK. Back in the Project Manager Sources window double-click the new decoder.vhd file and you will then see the VHDL file appear in the window on the right: You should add your name and a description of this file to the header description. We can now add the verilog statements to design our 3 to 8 decoder. Copyright 2015 R James Duckworth, WPI 5 Rev A
6 There are a number of ways to design the decoder in VHDL, below is an example using a conditional signal assigment statement: Now we can synthesize the design. Click Run Synthesis in the Project Manager window. After synthesis is complete there should be no errors or warnings reported (look at the Porject Summary window). If you click on Open Synthesized Design you can see a device level representation (this is mostly empty since we just have a very simple design that only uses a small fraction of the available FPGA resources): Copyright 2015 R James Duckworth, WPI 6 Rev A
7 But you can also look at a schematic representation to see the input and output buffers and the LUTs used (click on Schematic under the Synthesized Design): Copyright 2015 R James Duckworth, WPI 7 Rev A
8 Before we can implement the design we need to specify the FPGA pins that will be used for the SW inputs and LED outputs. Look at the Nexys4DDR manual to determine the FPGA pins. Next click Add Sources and select Add or create constraints : We can name the constraints file decoder: In the Souces window select the constraints file by the hierarchy Constraints => constrs_1 => decoder.xdc. We can then add location constraints for all the inputs and outputs (you can download a copy of the Nexys4DDR XDC constraints from the Digilent website just copy the pins you are using for the design): These constraints specify the pins to use for each signal and what type of interface. Copyright 2015 R James Duckworth, WPI 8 Rev A
9 Now we have specified the correct pins to use for the design (so it matches the Nexys4DDR board layout) we can implement the design. NOTE: although VHDL is not case sensitive the XDC constraints file is case sensitive and the port names need to match the port names in the VHDL entity. Click Run Implementation under Implementation in the Flow Navigator window. You will find there are two warnings after implementation. This is because we have not specified any timing constraints. For this simple combinational circuit we can ignore these warnings. Copyright 2015 R James Duckworth, WPI 9 Rev A
10 We can now generate the bitstream. Click on Generate Bitstream in the Flow Navigator window. Next step is to program the FPGA with the bitstream (you will notice another warning message regarding configuration voltage ignore this for now) On the Nexys4DDR board make sure that JP1 Mode Jumper is set to the JTAG mode and connect the USB cable to the board and turn on the power. Select the Hardware Manager in the Flow Navigator (under Program and Devug) and select Open Target and then Auto Connect. You should now see the Xilinx xc7a100t_0 in the Hardware Window: Copyright 2015 R James Duckworth, WPI 10 Rev A
11 Click on Program Device and select the decoder.bit bitstream (automatically filled in): Then select Program (ignore the warning about the missing debug core and the rule violation). Programming should just take a few seconds and then the DONE led on the Nexys4DDR board will turn on. You should now find that your decoder is implemented on the FPGA. Change the three slider switches (SW2, SW1, SW0) through all eight combinations and verify the correct corresponding LED turns on. Congratulations! You have entered a design and then Synthesized, Implemented, and programmed the FPGA with the generated bit file. This was a simple design example but the same steps are just repeated for any design. Close the Hardware manager to go back to the Project Manager window. Copyright 2015 R James Duckworth, WPI 11 Rev A
12 Programming the Serial Flash The FPGA is a volatile device and so the bit file will not be present after power cycling the board. We can load the QSPI serial flash on the Nexys4DDR board so it loads the bit file from the flash on power up. First we need to create a bin file to be able to program the serial flash. Click on the Bitstream Settings in the Program and Debug section of the Flow Navigator. Select the bin_file option: Click OK. Click on Generate Bitstream. After generation, if you look in the decoder_1 => decoder_1.runs => impl_1 directory you will see a decoder.bit and a decoder.bin file. Use the Hardware Manager to connect to the Nexys4DDR board then right-mouse click on the FPGA and select Add Configuration Memory Device: Copyright 2015 R James Duckworth, WPI 12 Rev A
13 We now need to select the serial flash device that is on thenexys4ddr board. Select Spansion as the Manufacturer, then select the 128Mb device (S25FL128S): Click OK Copyright 2015 R James Duckworth, WPI 13 Rev A
14 Click OK Select the Configuration File (decoder.bin) in the impl_1 directory. Click OK. Note: this will erase any existing design in the QSPI flash (including the configuration file shipped with the Nexys4DDR board). The QSPI Flash will now be erased and then programmed with the decoder.bin file. Once programmed, you can power off the Nexys4DDR board and change the JP1 jumper mode from JTAG to QSPI. Power back on the board and after a few seconds the DONE LED will turn on indicating that your decoder design has been automatically loaded into the FPGA from the serial flash. You can verify the decoder design by moving the slider switches and observing the leds as before. Copyright 2015 R James Duckworth, WPI 14 Rev A
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