DSP Core Instruction Set Architecture Design. Shih-Chieh Chang

Transcription

1 DSP Core Instruction Set Architecture Design Shih-Chieh Chang

2 Overview of Proposed Architecture Modified Harvard architecture (PM, XDM, YDM) Two parallel instructions per cycle Five-stage pipeline Zero-overhead Loop Dual-ALU and Dual-MAC Sixteen address generation units(agu) Compound Instructions

3 Propose Architecture

4 Experimental Results We have implemented the proposed RISC+DSP core in synthesizable Verilog HDL and targeted towards TSMC 0.35 µm cell library. 100Kgates (ex memory); 120MHz

5 Previous Results Experimental results show that our design gives reasonable computational power and provide higher code density. The results demonstrate that the compound instruction is useful to improve the performance and code density. However, compound instructions make the control logic more complex. = Control logic designed by Dynamic PLAs.

6 Dynamic PLA φ φ 1 a b AND plane O1 P1 P2 P3 P4 φ d1 OR plane O2 O3

7 Dynamic PLAs vs Standard Cell Static Standard Cell Dynamic PLA Performance Tools Capacity Slow, variation in path delay Synthesis/placemen t/routing Limited by tool Fast, all paths delays similar Layout generator, not easy to migrate to new tech. Limited by maximum size.

8 Dynamic PLAs vs Standard Cell Static Standard Cell Dynamic PLA Predictabili ty Unknown delay and area until before routing. Potentially large change with small logic modification. Wire delay is predictable Area and delay can be easily predicted. Very slightly change with logic modification.

9 Dynamic PLAs Previous design examples Dynamic PLA style is adopted in IBM 1 GHz processor [1998] Arrays of dynamic PLAs vs Standard cell style: 15% less delay [2000,Berkeley] Dynamic PlA vs standard cell style: 50% less delay in a real industrial control unit design in a microprocessor

10 Dynamic PLA compiler Architecture selection Floor plan design Leaf Cell design Buffer resizing) Layout generation by Skill code

11 SOP => PLA Layout

12 Compiler Optimizations with DSP-Specific Semantic Descriptions Yung-Chia Lin, NTHU, Taiwan Yuan-Shin Hwang, NTOU, Taiwan Jenq Kuen Lee, NTHU, Taiwan (Also in LCPC 2002)

13 DSPI: Digital Signal Processing Interface The design of Digital Signal Processing Interface ( DSPI ) is to provide: DSP-specific operation semantics Architectural preference for code generation Additional information for directive-based optimizations to work with compilers. DSPI is like the method used in OpenMP and HPF, but specialized in DSP-related domain.

14 Primitive Design of DSPI Using C/C++ standard compiler directive description: #pragma dspi directive-name [clause [,clause] ] Directives are categorized into: Environment Depiction Operation Intention Data Storage Characterization Parallelism Commentary

15 Environment Depiction To specify compiler optimization directives and user control options, like global data format, data precision, To control portability #pragma dspi algorithm_type fxp /* fixed-point computation */ #pragma dspi int_type 32bit /* integer is 32bits fixed-point number */

16 Operation Intention To specify DSPspecific computations To provide multilevel semantics Basic math operators, vector operators, matrix operators, etc. #pragma dspi fxp a:=<16:16> #pragma dspi fxp b:=<16:16> #pragma dspi fxp sadd:=<16:16>,saturated #pragma dspi op sadd:=a.add<b> Int sadd(int a, int b) /* saturated addition of two 32bits fixedpoint number */ { } Operator Examples: Basic Operator.ADD Addition Vector Operator Matrix Operator.CONV.KRONT Convolution Tensor product

17 Data Storage Characterization To provide manipulation knowledge for DSPcustomary data types. To specify accessing features that utilize specific architectural ability, like circular buffer #pragma dspi fxp a:=<24:16> int a; /* 24bits fixed-point number, 16 bits integer part */ #pragma dspi fxp d:=<24:16>,circular int d[160]; /* circular buffer of above type */

18 Parallelism Commentary To provide data parallelism constructs and simultaneous operation semantics To assist compiler in ILP, SIMD, and multiprocessor code generation To match synonymy in OpenMP #pragma dspi parallel_region [shared:var1 ] { } #pragma dspi parallel_for [schedule:=chunksize] for( ) { }

19 On-going Retargetable Compiler Construction We are developing the infrastructure based on SUIF and SPAM. We are working on retargetable code generation with ADL. Source Program Directive Preprocessor SUIF Front-end S U IF IR Architectural Code Generator Low-level IR Architecture-Reform -Interphase S p ecified Transformations Target Machine Specification Optim ization Layers Target Code

20 Preliminary Experiments Due to that the compiler construction is still in progress, we use a semi-manual code generation to evaluate some early experiments. We did only limited transformations of DSPI directives in our two test-suites; one is adopted from DSPstone, the other is the reference G codec from ITU-T. Target processor in this experiment is TI TMS320 C6

21 Experiments of Small Kernels Name conv mat1x3 lms fir iir n_complex matrix multiplication least mean square FIR filter Description convolution IIR filter in biquads complex number computation DSPI.CONV, parallelism, parallelism,.firf, parallelism,.firf, circular buffer,.iirf, circular buffer, complex data,

22 Results Illustration % Benchmark Testsuite 1 (32bit) original DSPI % Benchmark Testsuite 2 (16bit) original DSPI % % Execution Time 80.00% 60.00% 40.00% Execution Time 80.00% 60.00% 40.00% 20.00% 20.00% 0.00% conv mat1x3 lms fir iir 0.00% mat1x3 iir n_complex

23 Experiments of Large Applications G reference codec program is far larger than small kernels in test-suite1. The entire program is loaded into first-level off-core memory and on-core memory is enabled as cache when executing Cycles Program Coder 6.3K Coder 5.3K Decoder 6.3K Decoder 5.3K Original DSPI

24 Results Illustration Cycles Coder 6.3K Coder 5.3K Original DSPI Cycles Decoder 6.3K Decoder 5.3K Original DSPI

25 Decomposition of Instruction Decoder for Low Power Design TingTing Hwang

26 Motivation Execution-frequency of instructions is uneven Decomposition of instruction decoder Most of time, only a small component of decoder is activated

27 Instruction Occurrence Instruction execution frequency ARM 7TDMI instruction set (130 instructions) Statistics from DSPStone ADC(3) ADD(3) AND(3) B(2) BIC(3) CMN(3) CMP(3) EOR(3) LDM(12) LDR(30) MUL(6) MOV(3) MVN(3) ORR(3) RSB(3) RSC(3) SBC(3) STR(18) SUB(3) TEQ(3) TST(3) STM(12) SWP(2) Instruction Group (instruction count)

28 Model for Decomposed Decoder Activate Control Instruction Decoder... FF1 FF2 FF32 Instruction Control FSM Instr. Decoder instruction... Instr. Decoder_1... Instr. Decoder_2 Control Signals Decoder Intermediate code Activate ControlControl Signal Decoder... Intermediate code Other Information Instruction State Registers Control Signals Registers Control Signals Decoder_1 Control Signals Decoder_

29 Methods Instruction Decoder From instruction decode-tree (op-code) Control Signal Decoder From output control signals Intermediate code re-assignment

30 Benchmarking Process Target on ARM 7tdmi Apply to control path Instruction Decoder Control Signal Decoder Power estimated on DSPStone and Powerstone with block activated

31 Results-DSPStone

32 Results-Powerstone