Research Progress on Compilers for DSP Cores with Specifications

Transcription

1 Research Progress on Compilers for DSP Cores with Specifications Ching-ren Lee, Jenq-Kuen Lee Programming Language Research Lab. Department of Computer Science National Tsing-Hua Univ.

2 Outline of Current Research Progress System Software for Power Managements Compilers Operating Systems Portability with Efficient DSP Libraries Pseudo Assembly (with Architectural Description Language) Annotation Languages for Compiler Optimizations Fast Prototyping of Compiler Toolkits with Specification in Architecture Description Language Automatic Toolkits Generation from ADL Compiler Optimizations from ADL 2001/6/25 1

3 Directions with Low Power Issues Relationships between CPU s component activities & power consumptions. A strategy to integrate different compiler schemes for low-power. Instruction sets to control power constructions. Evaluate power consumption models and simulators. 2001/6/25 2

4 Power ManagementsM at OS Layer Minimize Power Consumption while Meet the Deadline of Real-Time Tasks Accepted by IEEE Workshop on Power Management for Real-Time and Embedded Systems. 2001/6/25 3

5 Specifications for DSP libraries (Our Approach ) Pseudo Assembly with Architecture Description Languages Specification Compound Instruction Descriptions Equation Descriptions Matrix Operation Descriptions 2001/6/25 4

6 DSP Compilers DSP Compiler for TMS320C62x Optimizing Core-routine in Internet Telephony (G etc) An initial testbed for experimenting retargetting of dsp libraries 2001/6/25 5

7 DSP compiler for TMS320C62x Compiler Prototype based on SUIF and Our Back-End Part Machine-dependent Code Generation for TMS320C62x SUIF IR Scalar Optimization Machine-dependent Code Optimization 2001/6/25 6

8 Example of Equation Descriptions /*annotate( x= Sat(y+z), x,y,z:16) */ Word16 add(word16 var1,word16 var2) { Word16 var_out; Word32 L_somme; Word16 add(word16 var1,word16 var2) { return(_sadd((word32)var1<<16,(word3 2)var2<<16)>>16); L_somme = (Word32) var1 + (Word32) var2; var_out = sature(l_somme); return(var_out); Replacement with intrinsic assembly routines 2001/6/25 7

9 Annotations for Array Computations Example 1: /*$Annotation void matrix(matrix_name;dimension) */ /*$Annotation void matrix(matrix_name;(a11 a12 )(a21 a22 ) ) */ /*$Annotation void diagonal(matrix_name,d1 d2 ) */ /*$Annotation void transpose(matrix_name;dimension) */ /*$Annotation void permutation(matrix_name,p1 p2 ) */ /*$Annotation matrix kron(matrix ) */ /*$Annotation matrix compose(matrx,matrix result) */ Example 2: F 8 =( F 2 I 4 )( I 2 F 4 ) ( where is Kronerker tensor product) /* $Annotate compose( kron((f;2),(i;4)),(t;8;4), kron((i;2),(f;4)),(l;8;2), (F;8) ) */ 2001/6/25 8

10 Early Experiment Result in Performance Effects with Durbin routines in G (Equation Descriptions) Cycles With Equation Descriptions Original Code 0 No Optimization O0 O1 O2 O3 Original Code With Equation Descriptions 2001/6/25 9

11 Compiler Toolkits for DSP/SOC/Embedded System Rapid System Software Prototyping for DSP/SOC/E mbedded System System-On-a-Chip CPU/DSP core ROM SRAM DRAM peripherals ASIC DMA Retargetable Compilers and SDK Kits Architectural Description Language Simulator Environment 2001/6/25 10

12 Benefits of our ADL approaching ADL is a formalized specification that we can check the design if error exists at the early time by some (formal) verification and consistency checking like normal programming language Modification could be done easily with different target architectures and memory organizations for design space exploration Driving automatically the backend toolkits generation from a single specification Fast prototyping of HDL-based high level synthesis by translation from ADL s hardware structure information 2001/6/25 11

13 Optimizations with Specification in ADL Timing model information ( instruction execution cycles, memory access cycles ) directs compiler optimizations in speed. Power model information ( function unit and memory storage operation power consumption ) directs compiler optimizations in low power consumption. Resource model and operation behavior model (pipeline information, data path constraints, ) provide detail compiler optimization issues in instruction selection, resource allocation, scheduling. 2001/6/25 12

14 ORISAL An Object oriented Instruction Set Architecture Language Java-like ISA description language Available on instruction set level and cycleaccurate level modeling SoC IP interconnection configuration Power consumption model simulation 2001/6/25 13

15 ORISAL Features Object Oriented styles will reduce specification writing efforts from scratch and also give the designers a more natural view of reconfigurable IPs. Object Oriented styles will reduce mistakes compared to other imperative language based ADL. Simulator could be generated directly through the JAVA compiler and JVM without efforts. Power model gives the possibility of compiler optimizations in low power consumption and power estimation with simulator. 2001/6/25 14

16 Retargetable environment ORISAL semantics ORISAL syntax syntax ORISAL coding coding Compiler Assembler behavior Binary executable Simulator ORISAL behavior ORISAL activation ORISAL coding coding 2001/6/25 15

17 ORISAL Principles Resource declarations and operations construct ORISAL descriptions which describe the behaviors of the ISA Resources hold the state of the programmable architecture in form of the stored data value Operation definitions collect the description of different property of the system, i.e. operation behavior, ISA information, and timing. All the resources and operations are extensible and inheritable. 2001/6/25 16

18 ORISAL architecture sections Resource section: memory, register, ALU and functional unit definition. Operation section: general operations for instruction and could be consisted of some instruction instances. Instruction set section: atomic instruction operations Assembly spec. section: assembly spec and binary format Compiler spec. section: compiler back-end optimization information Runtime environment spec. section: User-defined section 2001/6/25 17

19 Resource declaration example { Hardware components spec. Predefined types : FUnit,Storage,Port,Connection,resource Primitive type: bit, byte,ubyte,int,uint,long,ulong Class FetchUnit extends Funit Fetch Unit Latch fetdeclatch; port fetporgport; FetchUnit.Timing[]= new int []{1,1,0; FetchUnit.Power []= new int []{20,10,5; Timing Maybe piplned timing Power An uniform unit Timing and Power are static data members of FUnit 2001/6/25 18

20 Resource declaration example (con t) Class DRAM extends Storage { byte type; uint size; byte width; uint accesstime; in(ras,cas,port); out(ras,cas,port); ; Class Register extends Storage { byte type; byte width; in(port); port out(); Register DataRegister[16]; statusregister StatusWord; DataRegister.type = {Register; DataRegister.width = 32; 2001/6/25 19

21 Resource declaration example (con t) lass fetprogport extends Port Connection ProgBus; etprogport.width = 256; lass PBUS1 extends Connection Bus1.Attach = {FetchUnit,PMBank1; Bus1.Width = 128; Class PBUS2 extends PBus1 {Attach = {FetchUnit,PMBank2; Grouping {PBus1,PBus2 ProgBus; Class PMBank1 extends DRAM { Connection PBus1; AccessWidth = 128; port read(uint index); write(unit index,port); 2001/6/25 20

22 Resource declaration example (con t) lass PMBank2 extends PMBank1; rouping {PMBank1,PMBank2 ProgMem; rogmem.accessaddress ={0,1024; rogmem.interleave = 2; lass DecodeUnit extends FUnit Latch fetdeclatch; Latch decexlatch1; Latch decexlatch2; Class ALU extends FUnit { resource source,dest,statusword; dest add(source,dest,statusword) { dest = source + dest; setflags(statusword); dest sub(source,dest,statusword) { dest = source - dest; setflags(statusword); 2001/6/25 21

23 Example of instruction ADD Class ALU1 extends ALU { Latch decexlatch1; Class ALU2 extends ALU { Latch decexlatch2; Class IS extends instruction { bit opcode[12:15]; bit opmode[9:11]; bit EffectiveAddress[0:10]; storage Operand[]; IS.operand = 2; DRAM Memory; Memory.type = {DRAM; Memory.size = 0x1000; Memory.width = 32; Memory.accessTime = /6/25 22

24 Example of instruction ADD Class add extends IS { uint opcode = 0xa; int operandtype[]=new int [] {Register, Register, Register; ALIAS Src Operand[0]; ALIAS Dest Operand[1]; void operation(void){ if (opmode == 0x01) Dest.in(ALU.add(Src.out(), Dest.out())); add.latancy = 1; 2001/6/25 23

25 Example of instruction JMP Class IS2 extends instruction { bit opcode[12:15]; bit EffectiveAddress[0:10]; Register PC; Class JMP extends IS2 { void operation(void){ PC.in(ProgMEM.read(EffectiveAddress)); 2001/6/25 24

26 Example of instruction Bcc Conditional jump Class statusregister extends Register { byte type; byte width; in(port,bit); port out(bit); Register PC; Class Bcc extends JMP { bit condition EffectiveAddress[7:10]; bit offset Effective[0:6]; void operation(void){ switch (condition) { case 0x01: if (statusword.out(1)) PC.in(ProgMEM.read(EffectiveAddress)); break; case 0x02: break; 2001/6/25 25

27 Conclusions Portability for efficient DSP libraries presents challenging research issues. ADL based specification is a major research topic in recent HW/SW co-design and retargetable software toolkits generation. Refining ORISAL is our first work 2001/6/25 26