Hanbat National University Prof. Lee Jaeheung

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1 Sun, HH yy ee -Se ung Hanbat National University Prof. Lee Jaeheung

2 5.1.1 always, a l w a y s, i n i t i a l, t a s k, f u n c t i o n always always [@(sensitivity_list)] begin blocking_or_nonblocking (s e n s i t i v i t y _ l i s t ) a l w a y s sensitivity_list () (event) a lw a ys b eg in b eg in b lo c k ing no nb lo c k ing 2

3 5.1.1 always module sample(a, b, out); input a, b; output out; reg out; 2 OR or b) begin if(a==1 b==1) out = 1; // blocking else out = 0; // blocking module 5.1 3

4 5.1.1 always module dff(clk, din, qout); input clk, din; output qout; reg qout; clk) qout <= din; // Non-blocking module D 5.2 4

5 5.1.1 always always se n si t i v i t y_ li st ( ) a l w a y s, R T L (@*) / : / :,, // equivalent or b or c or d or f) y =(a & b) (c & d) f; 5

6 5.1.1 always module mux21_bad(a, b, sel, out); input [1:0] a, b; input sel; output [1:0] out; reg [1:0] out; or b) // sel is omitted if(sel ==0) out = a; else out = b; module sel 5.3 6

7 5.1.1 always always zero-d el a y ( i n f i n i t e l oop ) ( d ea d l oc k ) always clk = ~clk; // zero-delay infinite loop always #20 clk = ~clk; // 40ns clk 7

8 5.1.2 initial i n i t i al initial begin blocking_or_nonblocking statements;, initial begin areg = 0; // initialize areg for(index = 0; index < size; index = index + 1) memory[index] = 0; //initialize memory word 8

9 5.1.2 initial initial begin din = 6'b000000; // initialize at time zero #10 din = 6'b011001; // first pattern #10 din = 6'b011011; // second pattern #10 din = 6'b011000; // third pattern #10 din = 6'b001000; // last pattern 9

10 5.1.2 initial module behave; reg a, b; 5.4 initial begin // a = 1'b1; b = 1'b0; always #50 a = ~a; always #100 b = ~b; module 1 0

11 5.2 reg, i n t eg er, t i m e, rea l, rea l t i m e ( ex ec u t e) : (e v e n t ), n e t (d r i v e ) B l oc k i n g = N on b l oc k i n g < = 1 1

12 5.2.1 Blocking B lo c k i n g reg_lvalue = [delay_or_event_operator] expression; initial begin rega = 0; // reg regb[3] = 1; // regc[3:5] = 7; // mema[address] = 8'hff; // {carry, acc} = rega + regb; // 1 2

13 5.2.2 Nonblocking N o n b lo c k i n g b l oc k i n g ( a s s i g n m en t s c h ed u l i n g ), reg_lvalue <= [delay_or_event_operator] expression; 1 3

14 5.2.2 Nonblocking module non_blk1; output out; reg a, b, clk; initial begin a = 0; b = 1; clk = 0; always clk = #5 ~clk; module blk1; output out; reg a, b, clk; initial begin a = 0; b = 1; clk = 0; always clk = #5 ~clk; clk) begin clk) begin a <= b; b <= a; a = b; b = a; // a=1 // b=a=1 module 5.5-(a) module 5.5-(b) 1 4

15 5.2.2 Nonblocking Nonblocking Blocking 1 5

16 5.2.2 Nonblocking module non_block2; reg a, b, c, d, e, f; //blocking assignments with intra-assignment delay initial begin a = #10 1; // a will be assigned 1 at time 10 b = #2 0; // b will be assigned 0 at time 12 c = #4 1; // c will be assigned 1 at time 16 //non-blocking assignments with intra-assignment delay initial begin d <= #10 1; // d will be assigned 1 at time 10 e <= #2 0; // e will be assigned 0 at time 2 f <= #4 1; // f will be assigned 1 at time 4 module

17 5.2.2 Nonblocking module non_block3; reg a, b, c, d, e, f; //blocking assignments with delay initial begin #10 a = 1; // a will be assigned 1 at time 10 #2 b = 0; // b will be assigned 0 at time 12 #4 c = 1; // c will be assigned 1 at time 16 //non-blocking assignments with delay initial begin #10 d <= 1; // d will be assigned 1 at time 10 #2 e <= 0; // e will be assigned 0 at time 12 #4 f <= 1; // f will be assigned 1 at time 16 module 1 7

18 5.2.2 Nonblocking non_block2 non_block3 1 8

19 5.2.2 Nonblocking Nonblocking module multiple2; reg a; 5.7 initial a = 1; initial begin a <= #4 1; // schedules a = 1 at time 4 a <= #4 0; // schedules a = 0 at time 4 #20 $stop; // At time 4, a = 0 module 1 9

20 5.2.2 Nonblocking Nonblocking module multiple; reg r1; reg [2:0] i; 5.8 initial begin r1 = 0; for(i = 0; i <= 5; i = i+1) r1 <= #(i*10) i[0]; module 20

21 5.3 if i f if(expression) statement_true; [else statement_false;] (0 ), s t a t e m e n t _ t r u e (0, x, z ), s t a t e m e n t _ f a l s e e l s e, (l a t c h ) i f (n e s t e d ) (, i f i f ) if else, else if begin 21

22 5.3 if if(index > 0) // IF-1 if(rega > regb) // IF-2 result = rega; else // else of the IF-2 result = regb; if(index > 0) begin // IF-1 if(rega > regb) result = rega; // IF-2 else result = regb; // else of the IF-1 22

23 5.3 if module mux21_if(a, b, sel, out); input [1:0] a, b; input sel; output [1:0] out; reg [1:0] out; or b or sel) if(sel == 1'b0) // if(!sel) out = a; else out = b; module if

24 5.3 if module dff_sr_async(clk, d, rb, sb, q, qb); input clk, d, rb, sb; output q, qb; reg q; clk or negedge rb or negedge sb) begin if(rb==0) q <= 0; else if(sb==0) q <= 1; else q <= d; assign qb = ~q; set/reset D module

25 5.3 if

26 5.4 case case case(expression) case_item {, case_item} : statement_or_null; default [:] statement_or_null; case case case_ i t em 0, 1, x, z c a s e c a s e_ it em case_ i t em d ef au l t d ef au l t case d ef au l t 26

27 5.4 case case 2 1 module mux21_case(a, b, sel, out); input [1:0] a, b; input sel; output [1:0] out; reg [1:0] out; or b or sel) begin case(sel) 0 : out = a; 1 : out = b; case module

28 5.4 case reg [15:0] rega; reg [9:0] result; case begin case(rega) 16'd0: result = 10'b ; 16'd1: result = 10'b ; 16'd2: result = 10'b ; 16'd3: result = 10'b ; 16'd4: result = 10'b ; 16'd5: result = 10'b ; 16'd6: result = 10'b ; 16'd7: result = 10'b ; 16'd8: result = 10'b ; 16'd9: result = 10'b ; default: result = 10'bx; case 28

29 5.4 case case x z case(select[1:2]) 2'b00 : result = 0; 2'b01 : result = flaga; 2'b0x, 2'b0z : result = flaga? 'bx : 0; 2'b10 : result = flagb; 2'bx0, 2'bz0 : result = flagb? 'bx : 0; default : result = 'bx; case case x z case(sig) 1'bz: $display("signal is floating"); 1'bx: $display("signal is unknown"); default: $display("signal is %b", sig); case 29

30 5.4 case don't care cas e casez : z d o n t - c a r e d o n ' t car e? casex : x z d o n t - c a r e reg [7:0] ir; casez(ir) 8'b1???????: instruction1(ir); 8'b01??????: instruction2(ir); 8'b00010???: instruction3(ir); 8'b000001??: instruction4(ir); case 3 0

31 5.4 case module pri_enc_casex(encode, enc); input [3:0] encode; output [1:0] enc; reg [1:0] enc; casex 3 (priority encoder) begin casex(encode) 4'b1xxx : enc = 2'b11; 4'b01xx : enc = 2'b10; 4'b001x : enc = 2'b01; 4'b0001 : enc = 2'b00; case module

32 5.4 case

33 5.4 case module pri_enc_case(encode, enc); input [3:0] encode; output [1:0] enc; reg [1:0] enc; case 3 begin case(1) encode[3]: enc = 2'b11; encode[2]: enc = 2'b10; encode[1]: enc = 2'b01; encode[0]: enc = 2'b00; default : $display("error: One of the bits expected ON"); case module

34 5.5 forever repeat x z 0, while for forever statement; repeat(expression) statement; while(expression) statement; for(variable_assign); expression; variable_assign) statement; 3 4

35 5.5 repeat shift-add module multiplier_8b(opa, opb, result); parameter SIZE = 8, LongSize = 2*SIZE; input [SIZE-1:0] opa, opb; output [LongSize-1:0] result; reg [LongSize-1:0] result, shift_opa, shift_opb; or opb) begin shift_opa = opa; // multiplicand shift_opb = opb; // multiplier result = 0; repeat(size) begin if(shift_opb[0]) result = result + shift_opa; shift_opa = shift_opa << 1; shift_opb = shift_opb >> 1; module

37 5.5 module cnt_one(rega, count); input [7:0] rega; output [3:0] count; reg [7:0] temp_reg; reg [3:0] count; 8 rega 1 begin count = 0; temp_reg = rega; while(temp_reg) begin if(temp_reg[0]) count = count + 1; temp_reg = temp_reg >> 1; module

39 5.5 for 8 (priority encoder) module enc_for(in, out); input [7:0] in; output [2:0] out; reg [2:0] out; integer i; begin : LOOP out=0; for(i = 7; i >= 0; i = i-1) begin if(in[i]) begin out=i; disable LOOP; module in[7:0] out[2:0] 0000_ _ _ _ _ _ _ _

41 5.5 module tb_dff ; reg clk, d; forever dff U1 (clk, d, q); initial begin clk = 1'b0; forever #10 clk = ~clk; initial begin d = 1'b0; forever begin #15 d = 1'b1; #20 d = 1'b0; #30 d = 1'b1; #20 d = 1'b0; module 4 1

42 5.6 : delay operator : # ( ) x z 0 2 u n s i g n ed #10 rega = regb; #d rega = regb; // d is defined as a parameter #((d+e)/2) rega = regb; // delay is average of d and e ev ent ev en t operator ev en t n et ev en t 4 2

43 5.6 negedge 1 0, x, z, x, z 0 ev ent posedge 0 x, z, 1, x, z 1 ev ent ev ent 1, L S B 5.1 posedge negedge event From To 0 1 x z 0 No edge posedge posedge posedge 1 negedge No edge negedge negedge x negedge posedge No edge No edge z negedge posedge No edge No edge 4 3

44 5.6 delay_control ::= # delay_value #( mintypmax_expression ) delay_or_event_control ::= delay_control event_control repeat( expression ) event_control event_control event_expression ::= expression hierarchical_identifier posedge expression negedge expression event_expression or event_expression event_expression, event_expression 4 4

45 5.6 module dff(clk, d, q); input clk, d; output q; reg q; D clk) q <= d; module

46 5.6 named event event event ev ent na m ed event event event event list_of_event_identifiers; // event -> event_identifier; // event trigger 46

47 5.6 named event D module ff_event(clock, reset, din, q); input reset, clock, din; output q; reg q; event upedge; // event clock) -> upedge; or negedge reset) begin if(reset==0) q = 0; else q = din; module

49 5.6 event or event o r (, ) clk_a or posedge clk_b or trig) rega = regb; clk_a, posedge clk_b, trig) rega = regb; w a i t w a i t, wait(expression) statement_or_null; begin wait(!enable) #10 a = b; #10 c = d; 49

50 5.6 intra-as s ig nm e nt event, blocking_assignment ::= variable_lvalue = [ delay_or_event_control ] expression nonblocking_assignment ::= variable_lvalue <= [ delay_or_event_control ] expression delay_control ::= # delay_value #( mintypmax_expression ) delay_or_event_control ::= delay_control event_control repeat( expression ) event_control event_control 5 0

51 5.6 fork #5 a = b; #5 b = a; join // result will be a=b fork join a b, fork join race condition a b. fork a = #5 b; // intra-assignment delay b = #5 a; // intra-assignment delay join // data swap a b,, fork join a b 5 1

52 5.6 module fork_join(); reg a, b, c, d; initial begin a = 0; b = 1; c = 0; d = 1; or b or c or d) begin fork #20 a = b; #20 b = a; join fork c = #20 d; d = #20 c; join module 5 2

53 5.6 fork // data shift a clk) b; b clk) c; join a <= clk) data; 5 3

54 5.6 module intra_delay1(clk, d, out); input clk, d; output out; reg out; out = clk) d; module module intra_delay1_eq(clk, d, out); input clk, d; output out; reg out,temp; begin temp = clk) out = temp; module

56 Equivalent model of Intra assignment timing control With intra assignment construct a = #5 b; a clk) b; a = clk) b; Without intra assignment construct begin temp = b; #5 a = temp; begin temp = clk) a = temp; begin temp = clk) a = temp; 5 6

57 5.7 b eg i n : : f o r k j o i n : : 5 7

58 5.7 parameter d = 50; reg [7:0] r; begin // a waveform controlled by sequential delay #d r = 8'h35; #d r = 8'hE2; #d r = 8'h00; #d r = 8'hF7; #d -> _wave; //trigger an event called _wave fork join #50 r = 8'h35; #100 r = 8'hE2; #150 r = 8'h00; #200 r = 8'hF7; #250 -> _wave; fork join #250 -> _wave; #200 r = 8'hF7; #150 r = 8'h00; #100 r = 8'hE2; #50 r = 8'h35; 5 8

59 5.7 begin #ta wa = 0; #ta wa = 1; #ta wa = begin #tb wb = 1; #tb wb = 0; #tb wb = 1; join event event 5 9

P-1/P-105. Samir Palnitkar. Prentice-Hall, Inc. INSTRUCTOR : CHING-LUNG SU.

P-1/P-105. Samir Palnitkar. Prentice-Hall, Inc. INSTRUCTOR : CHING-LUNG SU. : P-1/P-105 Textbook: Verilog HDL 2 nd. Edition Samir Palnitkar Prentice-Hall, Inc. : INSTRUCTOR : CHING-LUNG SU E-mail: kevinsu@yuntech.edu.tw Chapter 7 P-2/P-105 Chapter 7 Behavioral Modeling Outline