Verilog For Synthesis

Transcription

1 Coding with Coding with always This is separate from command. In C procedures are executed when called. In Verilog procedures are executed continuously by default. In an always block the code starts executing when the simulation starts. When the of the block is reached, it comes back and starts to execute all over again. inside the always forces execution to stop and wait for some edge. One can have waits inside one block in a simulation. Always Comment on Slide 19 Modified; September 21, 1999 Strategic Microelectronics Consortium Digital Circuits p. 37 Coding with Incomplete Trigger Lists What happens The Design Compiler from Synopsys generated an AND-OR gate here as specified. My theory is that because the gate was so explicitly expressed it decided to generate it without the latch. Other synthesizers might put in latches. One synthesis engine, no longer available, made a logic block which returned a constant Y=0. Moral Put all the input variable in the trigger list unless you are trying to build latches. Input variables are: all variables on the right-hand side of the equal sign, all control variables for if and case. Comment on Slide 20 Modified; September 21, 1999 Strategic Microelectronics Consortium Digital Circuits p. 38

2 Coding With Coding With Verilog for Synthesis gives a flip-flop, a latch or combinational logic. Flip-Flops Positive-Edge Flip-Flops module flipflop(q,d,clk); input D,Clk; output Q; reg Q; Q <= D; module Latches Latch Inference module latch(q,d,clk); input D,Clk; output Q; reg Q; or D) if (Clk==1) Q <= D; module Positive-edge trigger This is the statement that tells the logic compiler to generate flip flops. There is a negedge also Level Sensitive Trigger or D) This may generate a latch. It may give just combinational logic. All inputs between and must go through double-edge sensitive trigger. The always indicates a procedure. Slide 19 Modified; September 21, 1999 Strategic Microelectronics Consortium Digital Circuits p. 39 Nonlatches Using Always@ Combinational Inference Nonlatches Using Always@ Used to allow procedural code for combinational logic. if, for, case,... Include all inputs in trigger list Bad Combinational Gate module gate(y, A,B,C); input A,B,C; output Y; reg Y; or B) Y = A (B&C); module Good Combinational Gate... or B or C) Y = A (B&C);... Y is recalculated only when a trigger variable changes A C B For the Bad gate Y Simulator: C changes are only noted when triggered by a change in A or B. Compilier: Generates an AND-OR gate and a hopefully a warning. SNAWS Simulation may Not Agree With Synthesis Avoid problems by including all right-hand side variables in the trigger list. for the Good Gate Including all variables in the trigger list removes all problems. Slide 20 Modified; September 21, 1999 Strategic Microelectronics Consortium Digital Circuits p. 40

3 Coding with Latch Insertion Latches are inserted if the else branch is not explicitly stated. This is a very common error. The easy way to make sure all else cases are covered is to assign a default value to all outputs a t the start of the procedure. Then use the if...else to overwrite it. Comment on Slide 21 Modified; September 21, 1999 Strategic Microelectronics Consortium Digital Circuits p. 41 Functions Never Infer Latches Functions Never Infer Latches An incomplete specification The possible combinatorial alternatives are:- Z=C D, Z=C D, Z=D + C, or Z=D. The and_function shown was sent through the Design Compiler, and it generated an AND gate. It did not generate the simplest logic treating the unspecified cases as don t cares. That would give Z=D. It did treat the unspecified cases as zero which gives Z=C D. Moral Until a definite principle is generally known, assume anything may come out of the unspecified case. Use functions only to save writing C D 0 1 A function can be used to define a block of code which will be repeated. That is clearer and shorter than typing multiple detailed copies. 0 1 C D C D D + C Z=D Comment on Slide 22 Modified; September 21, 1999 Strategic Microelectronics Consortium Digital Circuits p. 42

4 Inserting Latches With or Without Your Latch Inference Inserting Latches With or Without Your Asking Latches From IFs Latch Inference from if module latch(q,d,c); input D,C; output Q; reg Q; or D) if (C==1) Q <= D; module D C 1D C1 Q There is no else HDLs infer no else as hold the old value. Here a latch was probably wanted. Often the else is ignored through ignorance and generates a latch. No Latch Inference from if module nolatch(z,d,c); input D,C; output Z; reg Z; or D) Z<=1 b0; //Initialize if (C==1) Z <= D; module C D Z There is an effective else Either use an else. or initialize before the if. Then no latch is assumed. or D) if (C==1) Z <= D; else Z <= 0; //Used else Slide 21 Modified; September 21, 1999 Strategic Microelectronics Consortium Digital Circuits p. 43 Functions Never Infer Latches Functions Never Infer Latches No Latch Inference from if module nolatch(z,d,c); input D,C; output Z; reg Z; or D) Z=and_func(C,D); function and_func; input D,C; reg Z; if (C==1) Z = D; // No else and_func=z; function module Functions One or more inputs. One output; may be a concatenation of stuff. Functions forget everything between calls. Hence latches are not generated. Functions generate only combinational logic. But no clear principle says what takes the place of inferred latches. Avoid latch-inferring inferences. Functions contain no timing control, delay or event checking statements. Tasks can contain timing statements; but clk). Functions must be contained within a module. Their argument passing is too weak to go outside. Functions can call functions. Slide 22 Modified; September 21, 1999 Strategic Microelectronics Consortium Digital Circuits p. 44

5 Case Generated Latches Case Generated Latches In case as well as if, it is easy to make paths though the procedure that do not generate every output. These will up as latches when synthesized. Comment on Slide 23 Modified; September 21, 1999 Strategic Microelectronics Consortium Digital Circuits p. 45 Flip-Flop Inference Flip-Flop Inference Comment on Slide 24 Modified; September 21, 1999 Strategic Microelectronics Consortium Digital Circuits p. 46

6 Latch Inference (Cont) Latch Inference (Cont) Latches Inferred From Case Latch Inference from case module dec_decode(y,in); input [3,0] in; output [10:1] Y; reg Y; case(in) 4 h1: Y= ; 4 h2: Y= ; 4 h3: Y= ; 4 h4: Y= ; 4 h5: Y= ; 4 h6: Y= ; 4 h7: Y= ; 4 h8: Y= ; 4 h9: Y= ; 4 ha: Y= ; case module // dec-decode These are undefined cases 4 h0: Z= ; 4 hb: Z= ; 4 hc: Z= ; 4 hd: Z= ; 4 he: Z= ; 4 hf: Z= ; If one occurs Z will stay at its previous values. Thus synthesis will infer 10 latches. To avoid latches Either include all cases, or equivalently use h9: Y= ; 4 ha: Y= ; default: Y= ; Slide 23 Modified; September 21, 1999 Strategic Microelectronics Consortium Digital Circuits p. 47 Latch Inference (Cont) Flip-Flop Inference Flip-Flops Positive-Edge Flip-Flops module flipflop(q,d,clk); input D,Clk; output Q; reg Q; Q <= D; module D Clk 1D C1 Q Negative-edge trigger C) If negative edge ff in library fine. If not check what happens, Both in one design 1D Are you sure you want to do this? C1 Group in separate levels of hierarchy to keep timing analysis simple. Will your test methods cover having both at once? Automatically inserted scan has to be coerced! 1D C1 1D C1 Slide 24 Modified; September 21, 1999 Strategic Microelectronics Consortium Digital Circuits p. 48

7 Flip-Flops with Asynchronous Reset Flip-Flops with Asynchronous Reset Comment on Slide 25 Modified; September 21, 1999 Strategic Microelectronics Consortium Digital Circuits p. 49 Flip-Flops with Asynchronous Reset Flip-Flops with Synchronous Reset Comment on Slide 26 Modified; September 21, 1999 Strategic Microelectronics Consortium Digital Circuits p. 50

8 Flip-Flops With Asynchronous Reset Flip-Flops With Asynchronous Reset Fussy Flip-Flop With Asynchronous Reset module ff_w_ar(q, D, Clk, R_n); input D, Clk, R_n; output Q; reg Q; Clk or negedge R_n) if (!R_n) Q<=0; else Q <= D; module //ff_w_ar This Format Must Be Followed R and Clk are single-bit variables Here R_n means asserted low reset. Clk) or ---edge R) if (R)... else //what happens on active clk edge if A second reset must go in an else if if immediately follows: Else automatically assumes it will only be done on a positive(neg) Clk edge. Condition is restricted to: if (R) if (~R_n) if (!R_n) if (R == 1'b1) if (R_n == 1'b0) if (R[1]) is not allowed. if (R >(2-1)) is not allowed. Clearly negedge R_n inplies if (~R_n), if (!R_n), etc. Slide 25 Modified; September 21, 1999 Strategic Microelectronics Consortium Digital Circuits p. 51 Flip-Flops With Synchronous Reset Flip-Flops With Synchronous Reset Easy Flip-Flop With Synchronous Reset module ff_w_ar(q, D, Clk, Rsy_n); input D, Clk, Rsy_n; output Q; reg Q; if (!Rsy_n) Q<=0; else Q <= D; module //ff_w_ar Much Less Rigid Format Leave off the or negedge Rsy_n. The if - else could be replaced by: Q<= (!R)&D; Synchronous resets are easy.but- They should not be used as asynchronous resets. 1. They have setup and hold times 2. Using them for power up reset is bad. a. The reset signal may violate the setup time. b. Machine will up half in the reset state, and half in state one. Slide 26 Modified; September 21, 1999 Strategic Microelectronics Consortium Digital Circuits p. 52

9 Compiler Directives // synopsys async_set_reset // synopsys sync_set_reset //synopsys async_set_reset_local //synopsys one_hot applies directive to specified signals in a named block indicates only one of a list of signals is true at a time. Useful to show set and rest are never both applied at once. Compiler Directives Comment on Slide 27 Modified; September 21, 1999 Strategic Microelectronics Consortium Digital Circuits p. 53 Minimizing Flip-Flops Minimizing Flip-Flops Comment on Slide 28 Modified; September 21, 1999 Strategic Microelectronics Consortium Digital Circuits p. 54

10 Complier Directives Complier Directives Tell the compiler for sure. Force Asynchronous Reset module latch(q,d,c,r); input D,C,R; output Q; reg Q; // synopsys asynch_set_reset R or R) : if (R) Q = 0; else if (C) Q = D; module Look in the Synopsys manual There are many of these compiler directives. Specialized for one compiler Does overcome some language problems. However it is nearly always possible to avoid them by proper coding. The // synopsys is not read by the simulator. Thus simulation will agree with synthesis only if it was coded properly. Slide 27 Modified; September 21, 1999 Strategic Microelectronics Consortium Digital Circuits p. 55 Minimizing Flip-Flops Minimizing Flip-Flops Do Not Declare Extra Registers Inside ---) Procedure reg [2:0] count reg andy, ory; ; Clk or posedge R) if (R) count=0; else count=count+1; andy= & count; ory = count; module; //gross; wire andy, ory Clk or posedge R) if (R) count=0; else count=count+1; assign andy= & count; assign ory = count; Too much ---) andy and ory do not need storage. Storing count is enough. Move them outside into combinational logic. The upper square will generate 5 ff, the lower square 3 ff. Slide 28 Modified; September 21, 1999 Strategic Microelectronics Consortium Digital Circuits p. 56

11 Blocking and Nonblocking Blocking and Nonblocking Top Figure Normal shift register Z=Y; // Z get old Y Y=X; //Y gets input X Next Figure Down Y=X; // Y gets input Z=Y; // In C this would also make Z=X. So does it here. Bottom Two Figures Here the values of Y and X are saved when the procedure is entered. Changing Y on the left (output) side does not change it on the input side. Comment on Slide 29 Modified; September 21, 1999 Strategic Microelectronics Consortium Digital Circuits p. 57 Nonblocking Nonblocking In synthesis nonblocking will act as though all right-hand variables were sampled on procedure entry Even for variables calculated within the procedure. Example or b or c) b<=a; if (b) // will be old b Blocking means the next statement is blocked until the present statement is completed. initial #1 a=1; #1 b=2; // completed at t=2 #1 c<=b; // completed at t=3 using b=2. #1 b<=4; // completed at t=3, the nonblocking statement does not delay it #1 e=b; // completed at t=3, using b=2; neither nonblocking statements delay it. #1 f=5; // completed at t=4, the last blocking statement delays it. Rule for Synthesizable Procedures Use blocking = for all combinational logic. This allows code to overwrite other code with predictable results. Use nonblocking <= for flip-flops and registers. Blocking behaves like D-flip-flops, transferring all data simultaneously. or b) y=3 b000; if (a) y[2]=1; if (b) y[1]=1; Comment on Slide 30 Modified; September 21, 1999 Strategic Microelectronics Consortium Digital Circuits p. 58

12 Blocking or Nonblocking Blocking or Nonblocking Using <= or = Shift Registers module shifty(z, X, Clk} input Clk, X; output Z; reg Z,Y; Z=Y; Y=X; Y=X; Z=Y; Z<=Y; Y<=X; Y<=X; Z<=Y; Z 1D Y X 1D C1 C1 Z Y X 1D 1D C1 C1 But Y is now X Z 1D Y 1D X C1 C1 Z 1D Y 1D X C1 C1 The Nonblocking Assignment <= Used when flip-flops feed back/ This is like a real flip-flop. On the clock edge, the old outputs are grabbed and used as the right-hand side inputs. The outputs are all revised as the block is left. The Blocking Assignment = Like a C++ program. Statements at the top can change inputs beneath them. You Can t Use Both Verilog for simulation lets you use a reasonable mix of = and <=. Most Synthesizers will not allow both in one block. Certainly not both for one variable in one block. Slide 29 Modified; September 21, 1999 Strategic Microelectronics Consortium Digital Circuits p. 59 Parallel Procedures Races From Blocking = Assignments Parallel Procedures Blocking assignments follow order of statements Parallel procedures have no order. blocking clk) a = b; clk) b = a; nonblocking clk) a <= b; clk) b <= a; Parallel procedures blocking With Blocking both start at same time. a could transfer to b first. b could transfer to a first. nonblocking This is two parallel flip-flops Both clocked at same time. Think: next-state <= previous state a + <= b; b + b b + 1D <= a; a + C1 1D C1 a Slide 30 Modified; September 21, 1999 Strategic Microelectronics Consortium Digital Circuits p. 60

13 Multiple Assignments Multiple Assignments If both statements are in the same procedure, the En2 would replace the En1 result in zero time. In synthesis this would mean the En2 result would take priority over En1. This type of coding is common for synthesis. if (En1) Q=D1; if (En2) Q=D2; It should not matter whether the assignments are blocking or nonblocking. If delays are put on the statements simulation could give a glitch. if (En1) #2 Q<=D1; if (En2) #3 Q<=D2; What happens if: if (En1) Q=D1; if (~En1) Q=D1; Comment on Slide 31 Modified; September 21, 1999 Strategic Microelectronics Consortium Digital Circuits p. 61 Using case Using case Comment on Slide 32 Modified; September 21, 1999 Strategic Microelectronics Consortium Digital Circuits p. 62

14 Two Outputs Connected Together Multiple Assignments Two Outputs Connected Together if (En1) Q<=D1; if (En2) Q<=D2; Multiple Assignment The two assignments apparently could not happen together. We say they are mutually exclusive. If the were in one if-else statement the compiler would assume that would never happen together. Here it does not know. Possible Results The compiler chooses one result. The compiler generates two flip-flops and ANDs the result. All outputs my be disconnected. Slide 31 Modified; September 21, 1999 Strategic Microelectronics Consortium Digital Circuits p. 63 Mux Inference from case Using Case Statements Mux Inference from case module decode(y,in); input [2,0] in; output [7:0] Y; reg Y; case(in) 3 d1: Y=8 b ; 3 d2: Y=8 b ; 3 d3: Y=8 b ; 3 d4: Y=8 b ; 3 d5: Y=8 b ; 3 d6: Y=8 b ; 3 d7: Y=8 b ; 3 d0: Y=8 b ; case module// decode No undefined or parallel cases The compiler can statically determine that all possible cases are covered. The compiler can statically determine that no two cases are active at once. Full Case All cases are covered. It avoids latches Parallel Case (Mutually Exclusive) No two cases can be active at once. It can be implemented as a mux. in G DEMUX Y [7:0] Slide 32 Modified; September 21, 1999 Strategic Microelectronics Consortium Digital Circuits p. 64

15 Not Obvious Full-Case Not Obvious Full-Case If a case contains all 2 n cases no latches will be generated. If it contains less than 2 n cases, latches will be generated unless it is very obvious all cases are covered. Synthesizers do not look back very far to determine if all cases are covered. Use Default The default statement does no harm if it is used and not needed. Always put in a default, whether you need it or not, unless you want the latches. Placing xxxx as a default If you know the default will never be selected by the case, then you can put in anything you want. The logic that is easiest to minimize is x (don t care). Comment on Slide 33 Modified; September 21, 1999 Strategic Microelectronics Consortium Digital Circuits p. 65 Parallel-Case Parallel-Case Whenever two or more lines of the case statement may be selected at once, the simulation executes the first line encountered in the listing. This is like a priority encoder. In a parallel case, the synthesizer assumes some other circuit keeps two lines from being selected at once. //synopsis directives One can use the directives for parallel-case but one can also write the code to explicitly say what is desired. This latter method is synthesizer indepent. Such code may require the casex command described on the next slide. Coding for the three types of case Y[1] Y[2] Y[3] Y[1] Y[2] Y[3] Y[1] Y[2] Y[3] or y or z) case({x,y,z}) 3 b100 : Y=3 b100; 3 b010 : Y=3 b010; 3 b001 : Y=3 b001; default: Y=3 b000; case Full decoding: Assumes more than one of x, y, z can be 1 and removes those cases. or y or z) casex({x,y,z}) 3 b1xx : Y=3 b001; 3 b01x : Y=3 b010; 3 b001 : Y=3 b001; default: Y=3 b000; case Priority decoder Assumes more than one of x, y, z can be 1 but takes the first one as correct or y or z) casex({x,y,z}) 3 b1xx : Y=2 b100; 3 bx1x : Y=2 b010; 3 bxx1 : Y=2 b001; default: Y=2 bxxx; case Parallel case Assumes only one of x, y, z can be 1 at a time. Deps on some other circuit to enforce this. Comment on Slide 34 Modified; September 21, 1999 Strategic Microelectronics Consortium Digital Circuits p. 66

16 Latch Inference in Case Latch Inference in Case Not Obvious Full-Case, Case with a restricted input reg [6:1] Y; // if a,b,c = 1,1,1 make c1=0 assign c1 = (a&b&c)? 0 : c; or b or c) case({a,b,c1}) 3 d0: Y=000000; 3 d1: Y=000001; 3 d2: Y=000010; 3 d3: Y=000100; 3 d4: Y=001000; 3 d5: Y=010000; 3 d6: Y=100000; case Apparent undefined cases 3 d7: Y=000000; a,b,c = 1,1,1 cannot occur. Synthesis does not know that. Thus synthesis will infer 7 latches. To avoid latches Put in default d5: Y=010000; 3 d6: Y=100000; default: Y=000000; Better default A better default is: default: Y=xxxxxx; It gives the synthesizer more choice. Slide 33 Modified; September 21, 1999 Strategic Microelectronics Consortium Digital Circuits p. 67 Nonfull and/or Nonparallel Case Nonfull and/or Nonparallel Case NOT Full case(in) 3 d1: Y= ; 3 d2: Y= ; 3 d3: Y= ; case NOT Mutually Exclusive or y or z) case(1 b1) x: Y=2 b01; y: Y=2 b10; z: Y=2 b11; default: Y=2 b00; case FORCE Mutually Exclusive (Parallel) or y or z) case(1 b1)//synopsys parallel_case x: Y=2 b01; y: Y=2 b10; z: Y=2 b11; default: Y=2 b00; case Nonfull Case Latches are inserted Not Mutually Exclusive (nonparallel) Case Two cases can be active at once. Priority encoder generated. x y z Synopsys Comment Compiler directive(comment) Tells Synopsys x, y and z can never happen at the same time. You have to know and check this. Force Full Case HPRI / BIN Y[1] Y[0] // synopsys full_case will avoid creation of latches // synopsys full_case parallel_case avoids both Slide 34 Modified; September 21, 1999 Strategic Microelectronics Consortium Digital Circuits p. 68

17 Casex Casex For simulation In theory case treats comparison items as x. Thus:- assign a = 3b 1x0... case (a) 3 b110:... // This would not match a because 1 does not match x with a case statement. 3 b1x0:... // This would match a. By using casex, all values x and z values in the case block are taken as don t cares. Thus:- casex (a) 3 b1x0:... // This would match a because 1 does match x with a casex statement. For synthesis Since no x values ever propagate in synthesis case will sometimes work for casex. Don t be lazy, type casex if there are don t cares in the case block. Comment on Slide 35 Modified; September 21, 1999 Strategic Microelectronics Consortium Digital Circuits p. 69 Negative Numbers Negative Numbers Sign Extension All two s compliment numbers of different lengths must be sign exted when added. Thus: reg [4:0] x ; reg [5:0] y, z; z = {x[4], x} +y; // sign ext x to 5 bits. If the bits represent unsigned numbers, then do not sign ext. Comment on Slide 36 Modified; September 21, 1999 Strategic Microelectronics Consortium Digital Circuits p. 70

18 Using casex Allows don t cares in case-items module decode(y,in); input [2,0] in; output [1:0] Y; reg Y; always (in) casex(in) 3 bxx1: Y=2 b01; 3 bx10: Y=2 b10; 3 b100: Y=2 b11; default Y=2 b00; case mpdule// decode Using casex Generates a priority encoder for sure xx1 has the highest priority. Default Covers only 3 b000. Don t Cares In Right-Hand Side or y or z) casex(1 b1) x: Y=2 b01; y: Y=2 b10; z: Y=2 b11; default: Y=2 bxx; case Don t Cares Can Simplify Logic Don t force the defaults to zero if you don t care. It makes the logic larger. Slide 35 Modified; September 21, 1999 Strategic Microelectronics Consortium Digital Circuits p. 71 Confusion Between Reg and Integer Confusion Between Reg and Integer Integers are 2 s Complement Negative Numbers Integers declarations default to a 32-bit 2 s complement number. The compiler will eventually decide how many bits are needed. Reg numbers are nonzero integers The length of registered numbers is given in the declaration. integer B,C; reg [4:0] X; X = -5'd7; B = 10; C = B + X; Value of X X will hold a 5-bit Reg numbers are never negative, Hence is taken as 25. B will hold (32 or less bits) B + X = = Did you want 35 or 3? Slide 36 Modified; September 21, 1999 Strategic Microelectronics Consortium Digital Circuits p. 72

19 Hardware Loops 1 Loops give multiple copies of a basic instance. The code in the loop will be synthesized, a different instance for each iteration. Output leads from one block with the same name as as an input will connect between iterations. See the variable c in the program. Hardware Loops While loops are partially supported but are rather special. They must have all loops broken by clock) statement. Thus:- clock) while ( b >9 (posedge clock); // break the zero delay loop b <= b+2; 1. Palnitakar, Verilog, Prentice Hall, 1998, p..285 Comment on Slide 37 Modified; September 21, 1999 Strategic Microelectronics Consortium Digital Circuits p. 73 Mapping to a specific module Mapping to a specific module meanings // synopsys label greasedincr labels the + operation with name greasedincr. This label is bound to the instantiation bootspecial by the ops = greasedinc ; statement. The resource is module DW01_inc, in the designware library DW01 The specific implementation in the library is cla. Libraries are fairly automatic In general the simulator will choose an implementation to fit your criteria. Comment on Slide 38 Modified; September 21, 1999 Strategic Microelectronics Consortium Digital Circuits p. 74

20 Confusion Between Reg and Integer Using For Loops For Building Iterative Hardware Build an 5-bit ripple-carry adder. reg [4:0] A, B, S; reg c, c_out; // S is the sum, c the carry out. or A or B) c = c_in; for(i=0; i <=4; i=i+1) {c, S[i]} = A[i] + B[i] + c; // Concatenate the outputs into a 2-bit vector. c_out = c; A 4 B 4 A 3 B 3 A 2 B 2 A 1 B 1 A 0 B 0 c_out c c c c c c c c c c c_in S 4 S 3 S 2 S 1 S 0 Slide 37 Modified; September 21, 1999 Strategic Microelectronics Consortium Digital Circuits p. 75 Forcing Synopsys Designware Forcing Synopsys Designware Synopsys uses designware to implement counters, adders, comparators, etc. Control the type of function used by inserting compiler directives into your code. Example: The increment function can be ripple carry or carry look-ahead. Force a DW01_inc block to be implemented as a carry look-ahead incriminator. (count) : bill //named procedure /* synopsys resource bootspecial: map_to_module = "DW01_inc", implementation = "cla", ops = "greasedincr"; */ count = count + 1; //synopsys label greasedincr Must insert only in a nonclocked, named procedure or function. i.e bootspecial will be the name given this instantiation. "DW01_inc" and "cla" are from the library list of DW01 The label applies to the most recently parsed function. count = count + 1 /* synopsys label greasedincr */ Slide 38 Modified; September 21, 1999 Strategic Microelectronics Consortium Digital Circuits p. 76

21 Comment on Slide 39 Modified; September 21, 1999 Strategic Microelectronics Consortium Digital Circuits p. 77 Comment on Slide 40 Modified; September 21, 1999 Strategic Microelectronics Consortium Digital Circuits p. 78

22 Slide 39 Modified; September 21, 1999 Strategic Microelectronics Consortium Digital Circuits p. 79 Slide 40 Modified; September 21, 1999 Strategic Microelectronics Consortium Digital Circuits p. 80