Prerequisite Quiz September 3, 2003 CS252 Computer Architecture and Engineering

Transcription

1 University of California, Berkeley College of Engineering Computer Science Division EECS Fall 2003 John Kubiatowicz Prerequisite Quiz September 3, 2003 CS252 Computer Architecture and Engineering This prerequisite quiz will be used in determining class admissions. Good Luck! Your Name: SID Number: Discussion Section: Total 1

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3 Problem 1: Memory Hierarchy Problem 1a: Assume that we have a 32-bit processor (with 32-bit words) and that this processor is byte-addressed (i.e. addresses specify bytes). Suppose that it has a 512-byte cache that is twoway set-associative, has 4-word cache lines, and uses LRU replacement. Split the 32-bit address into tag, index, and cache-line offset pieces. Which address bits comprise each piece? tag: index: cache-line offset: 3 0 (we ll give you this one). Problem 1b: How many sets does this cache have? Explain. Problem 1c: Draw a block diagram for this cache. Show a 32-bit address coming into the diagram and a 32-bit data result and Hit signal coming out. Include, all of the comparators in the system and any muxes as well. Include the data storage memories (indexed by the Index ), the tag matching logic, and any muxes. You can indicate RAM with a simple block, but make sure to label address widths and data widths. Make sure to label the function of various blocks and the width of any buses. 3

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5 Problem 1d: Below is a series of memory read references set to the cache from part (a). Assume that the cache is initially empty and classify each memory references as a hit or a miss. Identify each miss as either compulsory, conflict, or capacity. One example is shown. Hint: start by splitting the address into components. Show your work. Address Hit/Miss? Miss Type? 0x300 Miss Compulsory 0x1BC 0x206 0x109 0x308 0x1A1 0x1B1 0x2AE 0x3B2 0x10C 0x205 0x301 0x3AE 0x1A8 0x3A1 0x1BA Problem 1e: Calculate the miss rate and hit rate. 5

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7 1H[W3& $ G G H U 1H[W 6(43& $ G G H U ; =HUR" $GGUHVV 0HPRU\,),' 56 5HJ)LOH,'(; 0 8 ; $/8 (;0(0 6LJQ ([WHQG,PP 5' 5' 5' 'DWD 0HPRU\ 0(0:% 0 8 ; WD D ' % : Figure 1: A simple 5-stage pipeline Problem 2: Basic Pipelining Problem 2a: How many branch delay slots does this pipeline have? Explain Problem 2b: Suppose that we include complex branch conditions: eg: bisqrt $r1, $r2, somewhere ; branch If $r1 square root of $r2 Is this likely to change the number of branch delay slots? If not, explain. If so, how many will there be now? Problem 2c: What is a load delay-slot? Is it a feature of the instruction set or of a particular implementation? Problem 2d: Suppose that the data cache takes 1 cycle to access on a hit and 100 cycles for a miss. How many load delay slots will there be? Explain. Problem 2e: Suppose that cache hits (both instructions and data) take 4 cycles but are pipelined. What does this affect? 7

8 Problem 2f: Modify the following datapath to handle forwarding. Be careful (don t forget forwarding for branches!). Pick an economical solution and make sure to include control signals. You can draw something below if required. 1H[W3& $GGHU 1H[W 6(43& $GGHU 56 08; =HUR" $GGUHVV 0HPRU\,),' 56 5HJ)LOH,'(; 08; $/8 (;0(0 'DWD 0HPRU\ 0(0:% 08;,PP 6LJQ ([WHQG 5' 5' 5' :%'DWD Problem 2g: Why might the following instruction sequence be important? Is there any way that we can handle it without stalling? lw sw $r1, 0($r2) $r1, 0($r3) 8

9 Problem 3: State Machine control In this problem, you must design a four-state finite state machine (FSM) that implements a saturating counter that either counts up or down in normal binary. The counter only changes when the COUNT signal is asserted (i.e. = 1). When counting up (the UP signal asserted), the counter will count as follows: 0, 1, 2, 3, 3, 3. When counting down (the UP not asserted), the counter will count as follows: 3, 2, 1, 0, 0, The RESET signal will take the counter to the 0 state. We call this the SatCounter. Problem 3a: Complete the Following State Transition Diagram for the SatCounter count output. Include the COUNT and UP signals. Ignore RESET:

10 Problem 3b: Construct a State Transition Table for this FSM. Encode the state as 2 bits, S 1 and S 0, where S 1 is the MSB (i.e. S 1 S 0 =10 for state 2). Ignore RESET. Problem 3c: Derive Next-State Logic Equations given the state transition table. Include the RESET signal in your equations. You will have 2 equations. Simplify these as much as possible (i.e. combine together terms as much as possible): S 0 = S 1 = 10

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