436 Nuclear Instruments and Methods in Physics Research A278 (1989) North-Holland, Amsterdam. 2. The detector

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1 436 Nuclear Instruments and Methods in Physics Research A278 (1989) North-Holland, Amsterdam VLSI STRUCTURES FOR TRACK FINDING Mauro DELL'ORSO Dipartimento di Fisica, Università di Pisa, Piazza Torricelli 2, Pisa, Italy Luciano RISTORI INFN Sezione di Pisa, Via Vecchia Livornese 582a, S. Piero a Grado (PI), Italy Received 24 October 1988 We discuss the architecture of a device based on the concept of associative memory designed to solve the track finding problem, typical of high energy physics experiments, in a time span of a few microseconds even for very high multiplicity events. This "machine" is implemented as a large array of custom VLSI s. All the s are equal and each of them stores a number of "patterns". All the patterns in all the s are compared in parallel to the data coming from the detector while the detector is being read out. 1. Introduction The quality of results from present and future high energy physics experiments depends to some extent on the implementation of fast and efficient track finding algorithms. The detection of heavy flavor production, for example, depends on the reconstruction of secondary vertices generated by the decay of long lived particles, which in turn requires the reconstruction of the majority of the tracks in every event. Particularly appealing is the possibility of having detailed tracking information available at trigger level even for high multiplicity events. This information could be used to select events based on impact parameter or secondary vertices. If we could do this in a sufficiently short time we would significantly enrich the sample of events containing heavy flavors. Typical events feature up to several tens of tracks each of them traversing a few position sensitive detector layers. Each layer detects many hits and we must correctly correlate hits belonging to the same track on different layers before we can compute the parameters of the track. This task is typically time consuming : it is usually solved using "constraint equations" which apply to hits from the same track and going through a large number of different hit combinations using a "trial and error" approach. We propose here to use modern VLSI technology to build a device capable of solving the pattern recognition problem in a time span of a few microseconds even for the most complicated events. 2. The detector In this discussion we will assume that our detector consists of a number of layers, each layer being segmented into a number of bins. When charged particles cross the detector they hit one bin per layer. No particular assumption is made on the shape of trajectories : they could be straight or curved. Also the detector layers need not be parallel nor flat. This abstraction is meant to represent a whole class of real detectors (drift chambers, silicon microstrip detectors etc.). In the real world the coordinate of each hit will actually be the result of some computation performed on "raw" data: it could be the center of gravity of a cluster or a charge division interpolation or a drift-time to space conversion depending on the particular class of detector we are considering. We assume that all these operations are performed upstream and that the resulting coordinates are "binned" in some way before being transmitted to our device. 3. The pattern bank For each event we know which bins have been hit and from this information we want to reconstruct the trajectories of all the particles. We call this process track finding. The problem of track finding can be solved, at least conceptually, by a "brute force" approach. We consider all the possible tracks that go through our detector /89/$03.50 C Elsevier Science Publishers B.V. (North-Holland Physics Publishing Division)

2 437 Each track generates a hit pattern. Since the detector has a finite spatial resolution (bin size), many different tracks generate the same hit pattern. The number of different hit patterns generated by all the tracks is finite and it is possible to store all of them in a sufficiently large memory. The collection of all these patterns defines both the space of the tracks we are looking for and how they appear in the detector : we will refer to this collection as the pattern bank. For each event, a number of tracks traverse the detector and a particular configuration of hits is thus generated : we will refer to this configuration as the event. A conceptually simple way to perform the track finding algorithm is to scan the pattern bank and compare each pattern to the event. A track candidate is found whenever all the hits in the pattern are present in the event. Going through the totality of the patterns in the bank yields a number of track candidates. The number of different patterns to be stored in the bank depends on the detector granularity and geometry, and on the characteristics of the tracks we want to detect. As an example we will consider the situation shown in fig. 1 : the detector consists of four parallel planes and each plane is segmented into n bins. We consider all straight tracks crossing all four planes. We want to estimate the number of different patterns (NP ) that can be generated by a single track. A fairly good approximation is NP = 3n 2. Fig. 2. Roads and subroads. By selecting one bin in plane 1 and one bin in plane 4 we define a road : there are n 2 different roads. From fig. 2 it should be obvious that all the tracks belonging to a road generate three different patterns correspond ing to the three subroads delimited by dotted lines. Expression (1) can be generalized as follows : Np = (m-1)n 2, (2) m where NP = number of patterns, m = number of detector planes, n = number of bins/plane. The main problem with this approach is that the number of patterns to store in the bank for a practical situation may be very large. For example, if we consider 4 planes with 256 bins/plane we obtain : Np = 3x256 2 =2x10 5. To deal with such a large number of patterns we need a lot of memory and we expect the process of matching all the patterns sequentially to be very time consuming. 4. Associative memory The Pattern Bank Fig. 1. Straight tracks traversing four parallel detector layers. The pattern matching algorithm can be easily implemented on a parallel architecture because different patterns can be compared to the event independently and in any order ; in particular, any number of comparisons can be performed in parallel provided that this is allowed by the hardware. If our main goal is speed, we can try to push the degree of parallelism to the limit and compare all the

3 438 Layer 1 Layer 2 Layer 3 Layer 4 Cell o ~ffl mm lui Cell 1 i Cell 2 m Cell ~~ Data Bus 1 Data Bus 2 Data Bus 3 Data Bus 4 Fig. 3. Associative memory architecture. patterns to the event at once. To do this we need a special type of associative memory to store the pattern bank : each cell of the memory is big enough to hold one pattern and has enough logic built in to compare its contents to the event. A possible architecture for this device is shown in fig. 3. Each row represents one cell and is designed to store one pattern. Each cell is structured into a number of words, one word per detector layer (four of them are shown). Each word stores the address of one hit on the corresponding layer. All the words in a cell define a pattern by specifying one hit per layer. The Data Bus connects all the words in the same layer, this bus is used to load the pattern data into the memory cells during the initialization phase. During normal operation, for every event, the coordinates of all the hits in each layer are transmitted one after the other on the corresponding Data Bus ; all the words continuously compare their contents to what is on the bus and if a match is found the corresponding flip-flop (FF) is set. After all the hits have been transmitted, any cell that has all the flip-flops set is a track candidate because all the hits that define that pattern are present in the event. The addresses of all the track candidates are transmitted sequentially on the Output Bus. It is important to note that each hit needs to be fed into the associative memory only once. When a hit coordinate is placed on the bus all the flip-flops in all the cells containing that hit will be set simultaneously. Feeding a whole event into the associative memory will take a time proportional to the number of hits and will usually be performed in parallel with the detector readout. The actual pattern recognition process takes place within the associative memory during the time needed to extract the information from the detector. By the time all the hits have been read out, all the track information is also available. 5. VLSI Typical applications require a number of cells of the order of 100k or more. The amount of logic involved rules out the possibility of using standard components and requires the development of appropriate ASICs (Application Specific Integrated Circuits). Using the present VLSI technology, large numbers of logic gates can be integrated on a single. The structure we are proposing is basically a large array of very simple cells made of a memory bit and a comparator. A significant effort can be devoted to the design and optimisation of this cell in terms of silicon area and this basic building block can then be assembled into arrays of different size. In this way we believe we can design a CMOS with 256 cells of 32 bits (4 planes x 8 bits). We could then implement a system with 100k cells using only 400 s. A characteristic of VLSI technology is that s can be manufactured in large quantities at relatively low cost ; the input/output architecture of our should then be designed to facilitate the assembling of many of them into arrays of arbitrary size. One possible solution is described in the following sections. 6. The Fig. 4 shows the associative memory () and its input/output signals.

4 K _ ADDRESS BUS > DATA BUS CONTROLBUS OR 439 Fig. 4. Associative memory and 1/O signals. OR Data Bus : is used to input pattern data and event data. The number of bits depends on the number of layers and bins/layer in the detector. Address Bus : is used to input pattern addresses while loading the memory and to output pattern addresses when reading out track candidates. The number of bits depends on the number of cells in the. Control Bus : specifies the function to be performed (Reset, Read, Write, Compare, etc.). Output Ready (OR) : signals the presence of at least one track candidate ready to be output. Select () : directs the to output the first track candidate in the output queue on the Address Bus. The main functions that can be performed are : Write : patterns are loaded into the memory through the Data Bus at the address specified by the Address Bus. Compare : hit coordinates are input through the Data Bus, one coordinate per clock cycle. Readout : addresses of track candidates are output on the Address Bus, one track per clock cycle. ADDR[O-n] 7. Large arrays ADDR[n+5..n+8] ADDR[n+1..n+4] ADDR[n+9..n+12] Fig. 6. A large array. Fig. 5 shows how a number of s (16 in this case) can be connected to implement a larger associative memory. The logic in the shaded area is what is needed to expand the memory by a factor 16 : we will call it "glue". During readout the OR signals are priority encoded and only the leftmost is enabled by. As soon as all track candidates from one have been read out, the OR from that goes away and is automatically transferred to the next with available data. When all the ORs are off then also the global GROUT signal is turned off. The output from the priority encoder identifies the being read out and it is used to form the high order bits on the address bus, 4 ADDRESS BUS DATA BUS CONTROLBUS EXPANDED ADDRESS BUS RD'IN WRITE PRI ENC GROUT 6 DEC glue IN Fig s tied by the "glue".

5 M. Dell'Orso, L. Ristori / VLS1 structures for track finding low order bits being the pattern address within the. During write operations, the high order bits are input from the bus and fed to the decoder to select only the appropriate. In this way we obtain a device which contains 16 times the number of patterns but has the same I/O lines and protocol as a single with four additional address lines. It is then straightforward to replicate this structure hierarchically to expand our associative memory to an arbitrary size. Fig. 6 shows how to implement a very large array of s. The overall structure is tree-like the leaves being s and the nodes being "glue" s. Each level in the tree deals with a number of address lines (four in our case). Each link from one level to the next represents on OR line going to the right and a line going to the left ; other control signals and the Data Bus are broadcast to all the s in parallel. 8. Two-stage track finding In some cases, when the number of detector bins is large, the size of the associative memory required to solve completely the track finding problem might be too big. Tracking systems with thousands of channels per layer are often required by modern HEP experiments leading to an order of magnitude of many million patterns, a number which is certainly out of reach of present technology. What would be the use fo associative memory in this case? If the number of bins is too large we should treat the detector as if it had lower resolution by logically ORing adjacent bins (which is easily done by simply ignoring a number of low order bits in hit addresses) and perform a first stage of track finding in the associative memory at this reduced level of spatial definition. We can then pass track candidates to a second stage which will refine the definition of the track down to the detector limit. The key point here is that this second stage can be implemented with more conventional techniques (e.g. a sequential processor) since virtually all of the combinatorial problem which makes track finding so time consuming has already been solved. This happens because the number of patterns in the associative memory is orders of magnitude larger than the number of tracks in one event and therefore the probability of having two tracks "hitting" the same pattern is negligibly small.