SOFTWARE ARCHITECTURE For MOLECTRONICS

Transcription

1 SOFTWARE ARCHITECTURE For MOLECTRONICS John H. Reif Duke University Computer Science Department In Collaboration with: Allara, Hill, Reed, Seminario, Tour, Weiss Research Report Presentation to DARPA: Sept 30, 1999 DARPA Moletronics Program

2 Title of DARPA Research Effort: Moleware and the Molecular Computer overall PI of DARPA Contract: James M. Tour, Rice University Background: The Hardware Tour's contract is developing a software architecture for a molecular scale computational system, which will be termed here a Molecular Computer(MC). The MC is to use moleware components of molecular scale (e.g., organic molecules that act as diodes and transistors) connected in a regular array. On the other hand, at this time, the wiring between these moleware components is assumed at this time to be conventional, with reconfigurable interconnections between moleware components.

3 MOLEWARE SOFTWARE ARCHITECTURE Subcontract PI Name: John Reif Our Areas of Investigation in Software There are two aspects of this that we at Duke are investigating: A. Evolutionary software for the design of new moleware components. The approach was considered by Reif and a Duke graduate student Richard Kisley and described in some detail in the recent ONR report this summer, But this work is not the primary objective this fall, B. Techniques for Programming and Simulating the MC to do a well specified task (e.g., an 8 bit adder). This is our primary objective this fall, 1999, and is described below. A Duke master student Christopher J. Butler is currently working with Reif on this.

4 Programming the MC: Summary The immediate goal is to produce a bit-serial adder, which is a simple feed-forward, combinatoric type device (requiring no loop-back circuits that may cause the devices to have different states). It is assumed that the only moleware components of molecular scale are the organic molecules that act as diodes and transistors, and that these are connected in a regular array, but that the wiring between these moleware components is assumed at this time to be conventional, with reconfigurable interconnections between moleware components. We are using a modular approach to programming the MC; the programming of each module reduces to a combinatorial optimization problem (which may be solved by a variety of heuristic techniques including evolutionary methods), and the communication between the modules makes use of a conventional VLSI interconnect topology.

5 I/O of the MC: The MC is assumed to have certain I/O wires used for input and output. When programming the MC, these wires are partitioned into three categories: "input" wires for input of the Boolean values of the computational problem. "output" wires for output of the Boolean values of the computational problem. "control" wires used to control the behavior of the MC. These might be set to rational values on the range from 0 to 1 (that is, they are not necessarily Boolean). Given a specific well specified computational task, we would like to rewire the interconnect topology of the MC, and set the "control" wires to the MC to fixed values, so the MC will execute the specified computational task.

6 MOLEWARE ARCHITECTURE: Moletronics Processing Array Contains basic logic gates Surrounded by: Reconfigurable Interconnects INPUTs: X = vector of m data inputs Y = vector of l control inputs X Y OUTPUT: O(X,Y) O(X,Y)= vector of n outputs Initial Conditions of System: random interconnects meaningless output for a given data input

7 Detailed Discussion of Programming the MC: Modular Decomposition While any computational task can be specified by a table relating the values of the input wires to output wires, an arbitrary true table with n Boolean inputs, for even moderate size n, has size too large to easily work with. Instead we wish to make (portions of) the MC simulate a circuit (we will give below an example of a carry-adder circuit) that can be modularly decomposed. That way, the programming problem for the MC is reduced to many smaller problems that can be efficiently solved by appropriately programming selected portions of the MC, as described below. Using Modular Decomposition By using a modular approach to programming the MC, we can determine and separate key functional modules to be executed, and thus to separately program and test these modules.

8 Assumptions of Modular Decomposition: we need to assume the MC has some way to do the following: (i) select sub-portions of the MC by external control (ii) wire together distinct portions of the MC that execute distinct modules. Both of these problems (i) and (ii) can be solved by the use of conventional reconfigurable VLSI wiring technology, which we are assuming to be on-chip. Note: The problem is not Feasible for Large Circuits: In the case where there no mechanism to solve (i) and (ii), then we need to consider the entire MC as a black box, and the problem of programming such a MC has no known efficient solution. In particular, then the problem is NP hard (i.e., equivalent to the SAT problem). There are only heuristics for such problems; no known fast solutions, and they will only in general give approximate circuits that may not always work correctly. Further Note: An Analogy with the Human Brain: The human brain (which has inspired our ideas for programming the MC) makes an important use of a similar selection mechanism, viewable by magnetic resonance imaging, that essentially provides a mechanism for problem (i); it is used for example when we concentrate on learning or executing specific tasks within the limbic and the prefrontal cortex.

9 Programming the MC Using Modular Decomposition for a 8 bit adder: The 8 bit adder circuit can be decomposed into a sequence of 8 distinct 1 bit carry-adder subcircuits, with "glue" logic between these. Each of these 1 bit carry-adder subcircuits has three inputs: the carry bit, and two input bits from the numbers to be added. Each of these 1 bit carry-adder subcircuits constitutes a module which needs to be programmed on separate portions of the MC, and wired together using the interconnect topology. These modules communicate via the interconnect technology (recall that the wiring between these moleware components is assumed at this time to be conventional, with reconfigurable interconnections between moleware components). Our software will attempt to locate these modules so that consecutive modules are close together, minimizing distance communications between them.

10 Determining a Modular Decomposition: A modular decomposition of a computational task can be done for many key computational tasks. We are developing some software to do this task semiautomatically in the case where the computational task is of a class known as prefix computation ; the class includes: integer arithmetic, scan operations and many much larger tasks. Can use techniques developed in the field of parallel algorithms (see the text "Synthesis of Parallel Algorithms", edited by J Reif, published by Morgan Kaufmann.).

11 Training the MC: To execute a specified module, we need to train the MC, by (1) determining a specified portion of the MC to be selected by use of the interconnect topology, and (2) determining, if possible, the settings for the "control" wires which make that portion of the MC execute the base module. Both of these problems associated with training the MC are combinatorial optimization problems that can needs to be solved. To do this, we will be testing some combinatorial optimization techniques, including: Genetic Algorithms(GA) and Simulated Annealing(SA). In addition, the chemistry of the moleware components could be changed (e.g., by the addition of new solvents, or by burnout ) at least somewhat during training, possibly necessitating a sequence of iterations of the training procedure as the chemistry evolves. The key point is that as long as the module is of bounded size, then the computational effort to train the MC is modest.

12 Modeling and Simulating the MC To demonstrate the feasibility of programming the MC in this manner, it is essential that we do software simulations of the programming process. This implies we need: a software model to model and simulate the MC. Modeling Moleware Components Some of the moleware components (e.g., diodes) have already been: demonstrated by Tour and Reed, and electrical properties have both been empirically measured by Reed, and simulated by Jorge M. Seminario using ab initio functional density methods. We will use the signal thresholds and analog response curves (e.g., current, voltage curves) that they have experimentally determined for multiple samples of moleware components.

13 TESTING METHODOLOGY for MOLECTRONICS: Testing System: may be Symmetric MultiProcessors (SMPs) Interface to Testing System: During Assembly: via I/O leads After Assembly: via input & output wires Multiple Testing Stages in Fabrication & Assembly Components to be Tested: Individually & In Place

14 TESTING for DIGITAL RESPONSE: DETERMINING FAULT LOCATIONS COMPONENT I/O Tests: For each logical component: Test if usable truth table output obtained Cycle through subsets of inputs to determine truth tables BUNDLED I/O Tests: Decreases Number of I/O testing Combinations Increases Likelihood of Overcoming Single Fault Locations AGGREGATE Fault Testing on Subcircuits: May employ Sophisticated Software Routines developed fo VLSI testing [Reif, 1993]

15 MEASURING and MODELING ANALOG RESPONSE 1 st Year: using 2D probed configuration may use hybrid on-chip multiplexer INITIAL VALIDATIONS: characterize & tune: electrode configuration, individual components, signal value/thresholds [1] APPROXIMATE Numerical Parameters signal thresholds response curves [2] Develop Software MODELS: for component performance [3] TUNE MANUFACTURE of Components Goal: INCREASE YIELDS of working Components [4] Use ITERATIVE REFINEMENT of Above In Later Years: Full 3D structure NOT always Accessible to Surface Probes Will Use Previously Developed Numerical Software Models

16 Possible Variability of Moleware Components: 1) in their number, chemical properties, & spatial location 2) variable electrical characteristics & prone to faults. Variability in the experimental results will be useful: it will allow us to develop a statistical model for the probability distribution of the electrical characteristics of the moleware components. Statistical Modeling: We are developing a statistical model for the probability distribution is to model the curves by a fixed function (e.g., exponential and polynomials) with a fixed number of numerical parameters; then the probability distribution can simply be generated from interpolated probability distributions on these parameters. Using this statistical model: We can artificially generate an example set of moleware components have variable electrical characteristics, and some of which are likely to be faulty. May also be used to predict the affect of errors within subcircuits and possibly also tune the manufacture of the moleware components to increase yields of working components.

17 Simulating the MC using SPICE We are using a UNIX version (i.e., PSPICE) of the circuit simulator SPICE to provide a circuit simulation of the MC; the wires are simulated using the conventional models for VLSI wires, whereas the moleware components of the MC will be simulated by choosing a sample of the moleware components using the learnt statistical model. While moleware components for wires and diodes have been demonstrated, others such as transistors have not been demonstrated, and so we have no empirical data for their behavior. Hence, we can simulate only an MC without restoring logic provided by transistors. Goals: We intend to determine the rate that the signals will degrade with the number of steps of the computation, due to both to the lack of restoring logic and also the variability in individual moleware components.

18 Fall, 1999 Demonstration Example: an Adder Circuit As a concrete example of these techniques for programming and simulating the MC, we will attempt to demonstrate this fall, 1999, by software simulation, the programming of an 8 bit adder. This is a simple feed-forward, combinatoric type device (requiring no loop-back circuits that may cause the devices to have different states).

19 The Modular versus the Neural Network Approach to Programming the MC Neural network learning works well for tasks involving approximation, clustering, etc. Our task under the current DARPA contract is to get an adder working on the MC. The task of addition and other arithmetic tasks are not at all well suited for neural network learning, since this is a task that allows for no errors or approximation. For the task of addition, the process of neural network learning amounts to simply memorizing the entire addition table, and that requires roughly as many nodes as the number of items to be memorized. (exponential in the number of bits). Also, for that task, the neural network approach does not work efficiently: for we need to iterate and test the system on the average at least the size of the truth table (exponential in the number of bits). Other Heuristic Methods: (In addition to Neural Network Learning) that may Speed Up Convergence Somewhat (but all still are exponential in the number of bits). Evolutionary Programming Techniques Simulated Annealing Techniques Nested Annealing Techniques [Reif]

20 When the Neural Network Approach Works for Programming the MC It is feasible to use a neural network approach (or any one of a number of other heuristic approaches) for training the MC to execute tasks involving a very small number of bits. That s another reason why it is essential to use a modular decomposition of the problem. Further Analogy with Human Brain: Again, consider the human brain. We learn the addition table for a digit or so (about 3 bits), then we start using sequential algorithm for addition. So the brain uses exactly the sort of modular technique as described. We do not memorize the entire addition table for even moderate size numbers because that is not an efficient use of memory resources and learning effort.

21 Additional Slides on ERROR-RESILIENT PROGRAMMING METHODOLOGIES for MOLECTRONICS

22 ERROR RESILIENCY Key Software Problem: PROGRAMMING a moletronic computer to do useful computation when: Use highly UNRELIABLE components Some components may be only PARTIALLY functional Coping With Dynamic Faults: Programming Needs To Do: Efficient DETECTION of Faulty Components on an ongoing basis REPAIR Faults by Bypassing Faulty Components ERROR-RESILIENT PROGRAMMING TECHNIQUES: (3) Fault Resiliency Using REDUNDANCY [von Neumann, 1950s] (4) MODULAR Fault Resilient Software Architecture e.g., [Gacs,1989][Gacs,Reif,1990] (5) Task RE-ASSIGNMENT e.g., [Kar, Nikolaou,Reif,1984]

23 ERROR-RESILIENT PROGRAMMING TECHNIQUE #1 Fault Resiliency Using REDUNDANCY [von Neumann, 1950s] Transform Digital Circuit with Faulty Components Using 3-way Redundancy Replicate Logical Components and use Majority Voting Replication Majority Voting

24 ERROR-RESILIENT PROGRAMMING TECHNIQUE #2: MODULAR Fault Resilient Software Architecture [Gacs,1989][Gacs,Reif,1990] Use Hierarchical Structured Fault Detection and Correction Decision Making via Majority o-director Co-Director Co-Director Level 2 Manager Level 2 Manager Level 2 Manager Level 1 Manager Level 1 Manager Level 1 Manager processor processor processor

25 ERROR-RESILIENT PROGRAMMING TECHNIQUE #3: Task RE-ASSIGNMENT [Kar, Nikolaou,Reif,1984] Re-Mapping Algorithm Uses Decomposition of Task Network Re-Mapping to Sub-Network of Reliable Components