Lars Schor, and Lothar Thiele ETH Zurich, Switzerland
|
|
- Luke Carpenter
- 5 years ago
- Views:
Transcription
1 Iuliana Bacivarov, Wolfgang Haid, Kai Huang, Lars Schor, and Lothar Thiele ETH Zurich, Switzerland
2 Efficient i Execution of KPN on MPSoC Efficiency regarding speed-up small memory footprint portability Distributed Operation Layer (DOL): efficient MPSoC design flow based on KPN Highlight: software synthesis on CELL BE 2
3 Outline Introduction to Distributed Operation Layer Efficient MPSoC design in DOL Runtime environment Software synthesis Some experimental results on CELL BE 3
4 DOL Vision: Write Once, Run Anywhere task-level parallelism Single-processor systems instruction-level ti l parallelism sequential Use C/C++ and a platform-dependent compiler (Heterogeneous) multi-processor systems Mapping: binding and scheduling Execution: distributed computation and communication 4
5 Streaming Applications Application domains Consumer electronics Communication systems Medical systems, etc. Real-time applications (Array) signal processing Audio & video (de)coding di High-performance computing WFS+ WFS+ WFS+ WFS+ 5
6 Applications Specified as KPN Dataflow semantics Matches structure of many streaming applications Separates computation and communication Enables design automation Untimed model of computation Facilitates implementation on MPSoCs Iuliana Bacivarov Efficient Execution of KPNs on CELL 6
7 Distributed ib t Memory Architectures t IBM/Sony/Toshiba CELL BE: PowerPC and 8 SPEs connected via ring bus Problem: efficient programming, no parallelism on SPEs Iuliana Bacivarov Efficient Execution of KPNs on Cell CELL 7
8 Goal: Efficient Execution of KPNs on MPSoCs 8
9 DOL Software Design Flow Goals Efficiency Predictability Portability Challenges Scalable specification Automated synthesis Design space exploration System-level performance analysis Strengths Abstraction Automation 9
10 DOL Vision: i Write Once, Run Anywhere 10
11 DOL Synthesis on Cell Goal Efficient execution on MPSoC Key issues Mapping optimization Efficient runtime environment Automatic ti software synthesis 11
12 Outline Introduction to Distributed Operation Layer Efficient MPSoC design in DOL Runtime environment Software synthesis Some experimental results on Cell BE 12
13 Runtime Environment Requirements Required quasi-parallelism on each processor protothreads intra- and inter-processor comm. windowed FIFOs not needed global scheduler (apply local, data-driven execution) full preemption (apply cooperative scheduling) 13
14 FIFO Communication Standard FIFO x 3 x2 float i; read(port_in, &i, sizeof(float)); i = i * i; write(port_out, OUT &i, sizeof(float)); Windowed FIFO float *i, *j; capture(port_in, &i, sizeof(float)); reserve(port_out, &j, sizeof(float)); *j = *i * *i; consume(port_in); release(port_out); x4 x x x4 x 3 24x x x x Remarks Windowed FIFOs preserve Kahn semantics [Huang, ASAP07] Inter-processor windowed FIFO (using DMA) is the only platform-dependent part of the runtime environment 14
15 Windowed d FIFO Implementation ti intra-processor WFIFO Write window inter-processor WFIFO Read window 15
16 Quasi-Parallelism li Using Threads Components Program code & data Context: registers, PC, SP, etc. Stack Limitations High context switch overhead example: SPE has B registers copy 4kB to switch context Multiple stacks consume memory Implementation using assembler code 16
17 Protothreads th [Adam Dunkels 2005] struct pt{unsigned short lc;}; #define PT_BEGIN(pt) switch(pt->lc){ case 0: #define PT_WAIT_UNTIL(pt, cond) pt->lc= LINE ; case LINE : if(!(cond)) return 0 #define PT_END(pt) } pt->lc=0; return 1 01 int protothread(struct pt *pt) { 02 PT_BEGIN(pt); PT_WAIT_UNTIL(pt, wfifo->capture(...)); PT_ END(pt); C pre- processor 07 } 01 int protothread(struct pt *pt){ 02 switch(pt->lc){ case 0: pt->lc=4; case 4: if(!wfifo->capture(...)) return 0; } pt->lc=0; return 1; 07 } Iuliana Bacivarov Efficient Execution of KPNs on CELL
18 P t th Protothreads d [Adam [Ad D Dunkels k l 2005] struct pt{unsigned short lc;}; #define PT_BEGIN(pt) #define PT_WAIT_UNTIL(pt, cond) #define PT_END(pt) 01 int protothread(struct pt *pt) { 02 PT_BEGIN(pt); PT_WAIT_UNTIL(pt, wfifo->capture(...)); C pre06 PT_END(pt); (p ); processor 07 } Iuliana Bacivarov switch(pt->lc){ case 0: pt->lc= LINE ; case LINE : if(!(cond)) return 0 } pt->lc=0; return 1 01 int protothread(struct pt *pt){ 02 switch(pt->lc){ case 0: pt->lc=4; case 4: if(!wfifo->capture(...)) return 0; } pt->lc=0; p ; return 1; ; 07 } Efficient Execution of KPNs on CELL
19 Automated t Software Synthesis square_fire(localdata p){ READ(PORT_IN,&(p->i),4,p); p->i = p->i * p->i; WRITE(PORT_OUT,&(p->i),4,p); } software synthesis int main(){ square_fire(localdata p){ //init process network PT_BEGIN(p); PT_WAIT_UNTIL(p, while(1){ p->fifo_in->read(&(p->i),4)); producer_fire(p_data); data); p->i = p->i * p->i; square_fire(s_data); PT_WAIT_UNTIL(p, consumer_fire(c_data); p->fifo_out->write(&(p->i),4)); } PT_END(p); } } 19
20 Outline Introduction to Distributed Operation Layer Efficient MPSoC design in DOL Runtime environment Software synthesis Some experimental results on Cell BE 20
21 Different Thread/FIFO Implementations ti cles] Exec cution Time [clock cy stack-less threads (protothreads) not applicable user-space threads (YAPI) user-space threads (SystemC) kernel-space threads (pthreads) context switch WFIFO access FIFO access (4 bytes) FIFO access (4096 bytes) Protothreads introduce the smallest context switching overhead 8x - 18x faster w.r.t. user-space threads 200x faster w.r.t. kernel-space threads Windowed FIFO is considerably more efficient for large accesses Protothreads are efficient context switch duration ~ 300 cycles and wfifo access ~ 150 cycles 21
22 Context-Switch/FIFOs t on CELL 22
23 MJPEG Decoder Mapping on Cell 23
24 MJPEG Decoder with Different Granularities Time to Decode 3100 JPEG Frames (320x240 pixels) 25 7 ution Tim me [s] Exec Sp peed-up [1] coarse-grained version fine-grained version speedup (coarsegrained version) 0 PPE only1 SPE 2 SPEs 3 SPEs 4 SPEs 5 SPEs 6 SPEs 24 0
25 Summary Efficient execution of KPN on MPSoC Run-time environment based on protothreads and windowed FIFOs - Low run-time overhead - Small memory footprint - Easily portable Automated software synthesis Implementation transparent to programmer Available online 25
26 26
27 Demo: Finding Nemo on Cell BE PowerPC + 6 SPEs PowerPC only 27
28
Iuliana Bacivarov, Wolfgang Haid, Kai Huang, Lars Schor, and Lothar Thiele
Iuliana Bacivarov, Wolfgang Haid, Kai Huang, Lars Schor, and Lothar Thiele ETH Zurich, Switzerland Efficient i Execution on MPSoC Efficiency regarding speed-up small memory footprint portability Distributed
More informationDistributed Operation Layer Integrated SW Design Flow for Mapping Streaming Applications to MPSoC
Distributed Operation Layer Integrated SW Design Flow for Mapping Streaming Applications to MPSoC Iuliana Bacivarov, Wolfgang Haid, Kai Huang, and Lothar Thiele ETH Zürich MPSoCs are Hard to program (
More informationDistributed Operation Layer
Distributed Operation Layer Iuliana Bacivarov, Wolfgang Haid, Kai Huang, and Lothar Thiele ETH Zürich Outline Distributed Operation Layer Overview Specification Application Architecture Mapping Design
More informationCoupling MPARM with DOL
Coupling MPARM with DOL Kai Huang, Wolfgang Haid, Iuliana Bacivarov, Lothar Thiele Abstract. This report summarizes the work of coupling the MPARM cycle-accurate multi-processor simulator with the Distributed
More informationEfficient Execution of Kahn Process Networks on Multi-Processor Systems Using Protothreads and Windowed FIFOs
Efficient Execution of Kahn Process Networks on Multi-Processor Systems Using Protothreads and Windowed FIFOs Wolfgang Haid, Lars Schor, Kai Huang, Iuliana Bacivarov, Lothar Thiele Computer Engineering
More informationIBM Cell Processor. Gilbert Hendry Mark Kretschmann
IBM Cell Processor Gilbert Hendry Mark Kretschmann Architectural components Architectural security Programming Models Compiler Applications Performance Power and Cost Conclusion Outline Cell Architecture:
More informationLightweight, Low-Power IP
Lightweight, Low-Power IP Adam Dunkels, PhD Swedish Institute of Computer Science adam@sics.se 1A part of Swedish ICT Adam Dunkels IP is lightweight The Message but weight has performance implications
More informationHardware-Software Codesign. 6. System Simulation
Hardware-Software Codesign 6. System Simulation Lothar Thiele 6-1 System Design specification system simulation (this lecture) (worst-case) perf. analysis (lectures 10-11) system synthesis estimation SW-compilation
More informationIntroduction to Contiki Kristof Van Laerhoven, Embedded Systems, Uni Freiburg
Kristof Van Laerhoven, Embedded Systems, Uni Freiburg kristof@ese.uni-freiburg.de Contiki Operating System ê memory-efficient: 2 kb RAM, 40 kb ROM typically* ê provides IP support (its uipv6 stack is IPv6
More informationArchitectures and Applications for Wireless Sensor Networks ( ) Node Programming
Architectures and Applications for Wireless Sensor Networks (01204525) Node Programming Chaiporn Jaikaeo chaiporn.j@ku.ac.th Department of Computer Engineering Kasetsart University Outline Microcontroller
More informationParallel Exact Inference on the Cell Broadband Engine Processor
Parallel Exact Inference on the Cell Broadband Engine Processor Yinglong Xia and Viktor K. Prasanna {yinglonx, prasanna}@usc.edu University of Southern California http://ceng.usc.edu/~prasanna/ SC 08 Overview
More informationAutomated Space/Time Scaling of Streaming Task Graphs. Hossein Omidian Supervisor: Guy Lemieux
Automated Space/Time Scaling of Streaming Task Graphs Hossein Omidian Supervisor: Guy Lemieux 1 Contents Introduction KPN-based HLS Tool for MPPA overlay Experimental Results Future Work Conclusion 2 Introduction
More informationCellSs Making it easier to program the Cell Broadband Engine processor
Perez, Bellens, Badia, and Labarta CellSs Making it easier to program the Cell Broadband Engine processor Presented by: Mujahed Eleyat Outline Motivation Architecture of the cell processor Challenges of
More informationExpandable Process Networks to Efficiently Specify and Explore Task, Data, and Pipeline Parallelism
Expandable Process Networks to Efficiently Specify and Explore Task, Data, and Pipeline Parallelism Lars Schor, Hoeseok Yang, uliana Bacivarov, and Lothar Thiele Computer Engineering and Networks Laboratory
More informationHigh Performance Computing. University questions with solution
High Performance Computing University questions with solution Q1) Explain the basic working principle of VLIW processor. (6 marks) The following points are basic working principle of VLIW processor. The
More informationEE382V: System-on-a-Chip (SoC) Design
EE382V: System-on-a-Chip (SoC) Design Lecture 10 Task Partitioning Sources: Prof. Margarida Jacome, UT Austin Prof. Lothar Thiele, ETH Zürich Andreas Gerstlauer Electrical and Computer Engineering University
More informationThe SARC Architecture
The SARC Architecture Polo Regionale di Como of the Politecnico di Milano Advanced Computer Architecture Arlinda Imeri arlinda.imeri@mail.polimi.it 19-Jun-12 Advanced Computer Architecture - The SARC Architecture
More informationOn the Portability and Performance of Message-Passing Programs on Embedded Multicore Platforms
On the Portability and Performance of Message-Passing Programs on Embedded Multicore Platforms Shih-Hao Hung, Po-Hsun Chiu, Chia-Heng Tu, Wei-Ting Chou and Wen-Long Yang Graduate Institute of Networking
More informationSimulink -based Programming Environment for Heterogeneous MPSoC
Simulink -based Programming Environment for Heterogeneous MPSoC Katalin Popovici katalin.popovici@mathworks.com Software Engineer, The MathWorks DATE 2009, Nice, France 2009 The MathWorks, Inc. Summary
More informationContiki a Lightweight and Flexible Operating System for Tiny Networked Sensors
Contiki a Lightweight and Flexible Operating System for Tiny Networked Sensors Adam Dunkels, Björn Grönvall, Thiemo Voigt Swedish Institute of Computer Science IEEE EmNetS-I, 16 November 2004 Sensor OS
More informationA Time-Triggered View. Peter PUSCHNER
Predictable Timing on MPSoC A Time-Triggered View Peter PUSCHNER 1 st Workshop on Mapping Applications to MPSoCs Schloss Rheinfels, Germany June 2008 Focus goal: build safety-critical hard real-time systems
More informationModeling and Simulation of System-on. Platorms. Politecnico di Milano. Donatella Sciuto. Piazza Leonardo da Vinci 32, 20131, Milano
Modeling and Simulation of System-on on-chip Platorms Donatella Sciuto 10/01/2007 Politecnico di Milano Dipartimento di Elettronica e Informazione Piazza Leonardo da Vinci 32, 20131, Milano Key SoC Market
More informationEmbedded Systems. 6. Real-Time Operating Systems
Embedded Systems 6. Real-Time Operating Systems Lothar Thiele 6-1 Contents of Course 1. Embedded Systems Introduction 2. Software Introduction 7. System Components 10. Models 3. Real-Time Models 4. Periodic/Aperiodic
More informationCUDA GPGPU Workshop 2012
CUDA GPGPU Workshop 2012 Parallel Programming: C thread, Open MP, and Open MPI Presenter: Nasrin Sultana Wichita State University 07/10/2012 Parallel Programming: Open MP, MPI, Open MPI & CUDA Outline
More informationCompilation for Heterogeneous Platforms
Compilation for Heterogeneous Platforms Grid in a Box and on a Chip Ken Kennedy Rice University http://www.cs.rice.edu/~ken/presentations/heterogeneous.pdf Senior Researchers Ken Kennedy John Mellor-Crummey
More informationMutekH embedded operating system. January 10, 2013
MutekH embedded operating system January 10, 2013 Table of Contents Table of Contents History... 2 Native heterogeneity support... 3 MutekH kernel overview... 6 MutekH configuration... 17 MutekH embedded
More informationIntroduction to CELL B.E. and GPU Programming. Agenda
Introduction to CELL B.E. and GPU Programming Department of Electrical & Computer Engineering Rutgers University Agenda Background CELL B.E. Architecture Overview CELL B.E. Programming Environment GPU
More informationThe University of Texas at Austin
EE382N: Principles in Computer Architecture Parallelism and Locality Fall 2009 Lecture 24 Stream Processors Wrapup + Sony (/Toshiba/IBM) Cell Broadband Engine Mattan Erez The University of Texas at Austin
More informationComputer Architecture
Computer Architecture Slide Sets WS 2013/2014 Prof. Dr. Uwe Brinkschulte M.Sc. Benjamin Betting Part 10 Thread and Task Level Parallelism Computer Architecture Part 10 page 1 of 36 Prof. Dr. Uwe Brinkschulte,
More informationAn Ultra High Performance Scalable DSP Family for Multimedia. Hot Chips 17 August 2005 Stanford, CA Erik Machnicki
An Ultra High Performance Scalable DSP Family for Multimedia Hot Chips 17 August 2005 Stanford, CA Erik Machnicki Media Processing Challenges Increasing performance requirements Need for flexibility &
More informationA Tuneable Software Cache Coherence Protocol for Heterogeneous MPSoCs. Marco Bekooij & Frank Ophelders
A Tuneable Software Cache Coherence Protocol for Heterogeneous MPSoCs Marco Bekooij & Frank Ophelders Outline Context What is cache coherence Addressed challenge Short overview of related work Related
More informationAutomatic Instrumentation of Embedded Software for High Level Hardware/Software Co-Simulation
Automatic Instrumentation of Embedded Software for High Level Hardware/Software Co-Simulation Aimen Bouchhima, Patrice Gerin and Frédéric Pétrot System-Level Synthesis Group TIMA Laboratory 46, Av Félix
More informationEvaluating the Portability of UPC to the Cell Broadband Engine
Evaluating the Portability of UPC to the Cell Broadband Engine Dipl. Inform. Ruben Niederhagen JSC Cell Meeting CHAIR FOR OPERATING SYSTEMS Outline Introduction UPC Cell UPC on Cell Mapping Compiler and
More informationSerial. Parallel. CIT 668: System Architecture 2/14/2011. Topics. Serial and Parallel Computation. Parallel Computing
CIT 668: System Architecture Parallel Computing Topics 1. What is Parallel Computing? 2. Why use Parallel Computing? 3. Types of Parallelism 4. Amdahl s Law 5. Flynn s Taxonomy of Parallel Computers 6.
More informationTowards a codelet-based runtime for exascale computing. Chris Lauderdale ET International, Inc.
Towards a codelet-based runtime for exascale computing Chris Lauderdale ET International, Inc. What will be covered Slide 2 of 24 Problems & motivation Codelet runtime overview Codelets & complexes Dealing
More informationA Process Model suitable for defining and programming MpSoCs
A Process Model suitable for defining and programming MpSoCs MpSoC-Workshop at Rheinfels, 29-30.6.2010 F. Mayer-Lindenberg, TU Hamburg-Harburg 1. Motivation 2. The Process Model 3. Mapping to MpSoC 4.
More informationOut-of-Order Parallel Simulation of SystemC Models. G. Liu, T. Schmidt, R. Dömer (CECS) A. Dingankar, D. Kirkpatrick (Intel Corp.)
Out-of-Order Simulation of s using Intel MIC Architecture G. Liu, T. Schmidt, R. Dömer (CECS) A. Dingankar, D. Kirkpatrick (Intel Corp.) Speaker: Rainer Dömer doemer@uci.edu Center for Embedded Computer
More informationHow to Write Fast Code , spring th Lecture, Mar. 31 st
How to Write Fast Code 18-645, spring 2008 20 th Lecture, Mar. 31 st Instructor: Markus Püschel TAs: Srinivas Chellappa (Vas) and Frédéric de Mesmay (Fred) Introduction Parallelism: definition Carrying
More informationIntroduction to Parallel Programming Models
Introduction to Parallel Programming Models Tim Foley Stanford University Beyond Programmable Shading 1 Overview Introduce three kinds of parallelism Used in visual computing Targeting throughput architectures
More informationEasy Multicore Programming using MAPS
Easy Multicore Programming using MAPS Jeronimo Castrillon, Maximilian Odendahl Multicore Challenge Conference 2012 September 24 th, 2012 Institute for Communication Technologies and Embedded Systems Outline
More informationMapping Stream based Applications to an Intel IXP Network Processor using Compaan
Mapping Stream based Applications to an Intel IXP Network Processor using Compaan Sjoerd Meijer (PhD Student) University Leiden, LIACS smeijer@liacs.nl Outline Need for multi-processor platforms Problem:
More informationIntroduction to Parallel Computing
Portland State University ECE 588/688 Introduction to Parallel Computing Reference: Lawrence Livermore National Lab Tutorial https://computing.llnl.gov/tutorials/parallel_comp/ Copyright by Alaa Alameldeen
More informationAutomated Design Flow for Coarse-Grained Reconfigurable Platforms: an RVC-CAL Multi-Standard Decoder Use-Case
XIV International Conference on Embedded Computer and Systems: Architectures, MOdeling and Simulation SAMOS XIV - 2014 July 14 th - Samos Island (Greece) Carlo Sau, Luigi Raffo DIEE Università degli Studi
More informationReference Model and Scheduling Policies for Real-Time Systems
ESG Seminar p.1/42 Reference Model and Scheduling Policies for Real-Time Systems Mayank Agarwal and Ankit Mathur Dept. of Computer Science and Engineering, Indian Institute of Technology Delhi ESG Seminar
More informationWindowed FIFOs for FPGA-based Multiprocessor Systems
Windowed FIFOs for FPGA-based Multiprocessor Systems Kai Huang David Grünert Lothar Thiele khuang@tik.ee.ethz.ch davidgr@ee.ethz.ch thiele@tik.ee.ethz.ch Swiss Federal Institute of Technology Zurich Computer
More informationMassively Parallel Architectures
Massively Parallel Architectures A Take on Cell Processor and GPU programming Joel Falcou - LRI joel.falcou@lri.fr Bat. 490 - Bureau 104 20 janvier 2009 Motivation The CELL processor Harder,Better,Faster,Stronger
More informationMartin Kruliš, v
Martin Kruliš 1 Optimizations in General Code And Compilation Memory Considerations Parallelism Profiling And Optimization Examples 2 Premature optimization is the root of all evil. -- D. Knuth Our goal
More informationMethod-Level Phase Behavior in Java Workloads
Method-Level Phase Behavior in Java Workloads Andy Georges, Dries Buytaert, Lieven Eeckhout and Koen De Bosschere Ghent University Presented by Bruno Dufour dufour@cs.rutgers.edu Rutgers University DCS
More informationThroughput-optimizing Compilation of Dataflow Applications for Multi-Cores using Quasi-Static Scheduling
Throughput-optimizing Compilation of Dataflow Applications for Multi-Cores using Quasi-Static Scheduling Tobias Schwarzer 1, Joachim Falk 1, Michael Glaß 1, Jürgen Teich 1, Christian Zebelein 2, Christian
More informationMay 1, Foundation for Research and Technology - Hellas (FORTH) Institute of Computer Science (ICS) A Sleep-based Communication Mechanism to
A Sleep-based Our Akram Foundation for Research and Technology - Hellas (FORTH) Institute of Computer Science (ICS) May 1, 2011 Our 1 2 Our 3 4 5 6 Our Efficiency in Back-end Processing Efficiency in back-end
More informationParallel Discrete Event Simulation of Transaction Level Models
Parallel Discrete Event Simulation of Transaction Level Models Rainer Dömer, Weiwei Chen, Xu Han Center for Embedded Computer Systems University of California, Irvine, USA doemer@uci.edu, weiwei.chen@uci.edu,
More informationhigh performance medical reconstruction using stream programming paradigms
high performance medical reconstruction using stream programming paradigms This Paper describes the implementation and results of CT reconstruction using Filtered Back Projection on various stream programming
More informationA Deterministic Concurrent Language for Embedded Systems
A Deterministic Concurrent Language for Embedded Systems Stephen A. Edwards Columbia University Joint work with Olivier Tardieu SHIM:A Deterministic Concurrent Language for Embedded Systems p. 1/30 Definition
More informationParallel Computing: Parallel Architectures Jin, Hai
Parallel Computing: Parallel Architectures Jin, Hai School of Computer Science and Technology Huazhong University of Science and Technology Peripherals Computer Central Processing Unit Main Memory Computer
More informationA Deterministic Concurrent Language for Embedded Systems
A Deterministic Concurrent Language for Embedded Systems Stephen A. Edwards Columbia University Joint work with Olivier Tardieu SHIM:A Deterministic Concurrent Language for Embedded Systems p. 1/38 Definition
More informationIntroduction to CUDA Algoritmi e Calcolo Parallelo. Daniele Loiacono
Introduction to CUDA Algoritmi e Calcolo Parallelo References q This set of slides is mainly based on: " CUDA Technical Training, Dr. Antonino Tumeo, Pacific Northwest National Laboratory " Slide of Applied
More informationMoCC - Models of Computation and Communication SystemC as an Heterogeneous System Specification Language
SystemC as an Heterogeneous System Specification Language Eugenio Villar Fernando Herrera University of Cantabria Challenges Massive concurrency Complexity PCB MPSoC with NoC Nanoelectronics Challenges
More informationMain Points of the Computer Organization and System Software Module
Main Points of the Computer Organization and System Software Module You can find below the topics we have covered during the COSS module. Reading the relevant parts of the textbooks is essential for a
More informationDesign methodology for multi processor systems design on regular platforms
Design methodology for multi processor systems design on regular platforms Ph.D in Electronics, Computer Science and Telecommunications Ph.D Student: Davide Rossi Ph.D Tutor: Prof. Roberto Guerrieri Outline
More informationMulti-Level Computing Architectures (MLCA)
Multi-Level Computing Architectures (MLCA) Faraydon Karim ST US-Fellow Emerging Architectures Advanced System Technology STMicroelectronics Outline MLCA What s the problem Traditional solutions: VLIW,
More informationIntroduction to Parallel Programming
Introduction to Parallel Programming David Lifka lifka@cac.cornell.edu May 23, 2011 5/23/2011 www.cac.cornell.edu 1 y What is Parallel Programming? Using more than one processor or computer to complete
More informationSysteMoC. Verification and Refinement of Actor-Based Models of Computation
SysteMoC Verification and Refinement of Actor-Based Models of Computation Joachim Falk, Jens Gladigau, Christian Haubelt, Joachim Keinert, Martin Streubühr, and Jürgen Teich {falk, haubelt}@cs.fau.de Hardware-Software-Co-Design
More informationMapping Multiple Processes onto SPEs of the CELL BE Platform using the SCO Model of Computation
Mapping Multiple Processes onto SPEs of the CELL BE Platform using the SCO Model of Computation A Master s thesis Computer Science Nadia Ramjiawan January 19, 2009 Abstract The Cell Broadband Engine platform
More informationThe Bifrost GPU architecture and the ARM Mali-G71 GPU
The Bifrost GPU architecture and the ARM Mali-G71 GPU Jem Davies ARM Fellow and VP of Technology Hot Chips 28 Aug 2016 Introduction to ARM Soft IP ARM licenses Soft IP cores (amongst other things) to our
More informationReconOS: An RTOS Supporting Hardware and Software Threads
ReconOS: An RTOS Supporting Hardware and Software Threads Enno Lübbers and Marco Platzner Computer Engineering Group University of Paderborn marco.platzner@computer.org Overview the ReconOS project programming
More informationParallel Execution of Kahn Process Networks in the GPU
Parallel Execution of Kahn Process Networks in the GPU Keith J. Winstein keithw@mit.edu Abstract Modern video cards perform data-parallel operations extremely quickly, but there has been less work toward
More informationAn Efficient Stream Buffer Mechanism for Dataflow Execution on Heterogeneous Platforms with GPUs
An Efficient Stream Buffer Mechanism for Dataflow Execution on Heterogeneous Platforms with GPUs Ana Balevic Leiden Institute of Advanced Computer Science University of Leiden Leiden, The Netherlands balevic@liacs.nl
More informationFunctional modeling style for efficient SW code generation of video codec applications
Functional modeling style for efficient SW code generation of video codec applications Sang-Il Han 1)2) Soo-Ik Chae 1) Ahmed. A. Jerraya 2) SD Group 1) SLS Group 2) Seoul National Univ., Korea TIMA laboratory,
More informationMapping of Applications to Multi-Processor Systems
Springer, 2010 Mapping of Applications to Multi-Processor Systems Peter Marwedel TU Dortmund, Informatik 12 Germany 2014 年 01 月 17 日 These slides use Microsoft clip arts. Microsoft copyright restrictions
More informationKampala August, Agner Fog
Advanced microprocessor optimization Kampala August, 2007 Agner Fog www.agner.org Agenda Intel and AMD microprocessors Out Of Order execution Branch prediction Platform, 32 or 64 bits Choice of compiler
More informationPerformance Issues in Parallelization Saman Amarasinghe Fall 2009
Performance Issues in Parallelization Saman Amarasinghe Fall 2009 Today s Lecture Performance Issues of Parallelism Cilk provides a robust environment for parallelization It hides many issues and tries
More informationTesla GPU Computing A Revolution in High Performance Computing
Tesla GPU Computing A Revolution in High Performance Computing Mark Harris, NVIDIA Agenda Tesla GPU Computing CUDA Fermi What is GPU Computing? Introduction to Tesla CUDA Architecture Programming & Memory
More informationDEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING UNIT-1
DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING Year & Semester : III/VI Section : CSE-1 & CSE-2 Subject Code : CS2354 Subject Name : Advanced Computer Architecture Degree & Branch : B.E C.S.E. UNIT-1 1.
More informationCOSC 6385 Computer Architecture - Data Level Parallelism (III) The Intel Larrabee, Intel Xeon Phi and IBM Cell processors
COSC 6385 Computer Architecture - Data Level Parallelism (III) The Intel Larrabee, Intel Xeon Phi and IBM Cell processors Edgar Gabriel Fall 2018 References Intel Larrabee: [1] L. Seiler, D. Carmean, E.
More informationEmbedded Systems. 7. System Components
Embedded Systems 7. System Components Lothar Thiele 7-1 Contents of Course 1. Embedded Systems Introduction 2. Software Introduction 7. System Components 10. Models 3. Real-Time Models 4. Periodic/Aperiodic
More informationAuto-parallelisation of Sieve C++ programs
Auto-parallelisation of Sieve C++ programs Alastair Donaldson 1, Colin Riley 1, Anton Lokhmotov 2, and Andrew Cook 1 1 Codeplay Software 45 York Place, Edinburgh, EH1 3HP, UK 2 Computer Laboratory, University
More informationComputational Process Networks a model and framework for high-throughput signal processing
Computational Process Networks a model and framework for high-throughput signal processing Gregory E. Allen Ph.D. Defense 25 April 2011 Committee Members: James C. Browne Craig M. Chase Brian L. Evans
More informationIndustrial Multicore Software with EMB²
Siemens Industrial Multicore Software with EMB² Dr. Tobias Schüle, Dr. Christian Kern Introduction In 2022, multicore will be everywhere. (IEEE CS) Parallel Patterns Library Apple s Grand Central Dispatch
More informationPS3 programming basics. Week 1. SIMD programming on PPE Materials are adapted from the textbook
PS3 programming basics Week 1. SIMD programming on PPE Materials are adapted from the textbook Overview of the Cell Architecture XIO: Rambus Extreme Data Rate (XDR) I/O (XIO) memory channels The PowerPC
More information( ZIH ) Center for Information Services and High Performance Computing. Event Tracing and Visualization for Cell Broadband Engine Systems
( ZIH ) Center for Information Services and High Performance Computing Event Tracing and Visualization for Cell Broadband Engine Systems ( daniel.hackenberg@zih.tu-dresden.de ) Daniel Hackenberg Cell Broadband
More informationCSL 860: Modern Parallel
CSL 860: Modern Parallel Computation Course Information www.cse.iitd.ac.in/~subodh/courses/csl860 Grading: Quizes25 Lab Exercise 17 + 8 Project35 (25% design, 25% presentations, 50% Demo) Final Exam 25
More informationInstruction Set Principles and Examples. Appendix B
Instruction Set Principles and Examples Appendix B Outline What is Instruction Set Architecture? Classifying ISA Elements of ISA Programming Registers Type and Size of Operands Addressing Modes Types of
More informationVenezia: a Scalable Multicore Subsystem for Multimedia Applications
Venezia: a Scalable Multicore Subsystem for Multimedia Applications Takashi Miyamori Toshiba Corporation Outline Background Venezia Hardware Architecture Venezia Software Architecture Evaluation Chip and
More informationCompilation of Parametric Dataflow Applications for Software-Defined-Radio-Dedicated MPSoCs DREAM seminar
Compilation of Parametric Dataflow Applications for Software-Defined-Radio-Dedicated MPSoCs DREAM seminar Mickaël Dardaillon Research Intern with NOKIA Technologies January 27th, 2015 2 / 33 What we know
More informationDIGITAL VS. ANALOG SIGNAL PROCESSING Digital signal processing (DSP) characterized by: OUTLINE APPLICATIONS OF DIGITAL SIGNAL PROCESSING
1 DSP applications DSP platforms The synthesis problem Models of computation OUTLINE 2 DIGITAL VS. ANALOG SIGNAL PROCESSING Digital signal processing (DSP) characterized by: Time-discrete representation
More informationCover Page. The handle holds various files of this Leiden University dissertation
Cover Page The handle http://hdl.handle.net/1887/32963 holds various files of this Leiden University dissertation Author: Zhai, Jiali Teddy Title: Adaptive streaming applications : analysis and implementation
More informationCS/CoE 1541 Final exam (Fall 2017). This is the cumulative final exam given in the Fall of Question 1 (12 points): was on Chapter 4
CS/CoE 1541 Final exam (Fall 2017). Name: This is the cumulative final exam given in the Fall of 2017. Question 1 (12 points): was on Chapter 4 Question 2 (13 points): was on Chapter 4 For Exam 2, you
More informationSoftware Design and Integration for Embedded Multimedia Applications by Successive Refinement
Software Design and Integration for Embedded Multimedia Applications by Successive Refinement Katalin Popovici katalin.popovici@mathworks.com The MathWorks, France 2008 The MathWorks, Inc. Acknowledgement
More informationRAMP-White / FAST-MP
RAMP-White / FAST-MP Hari Angepat and Derek Chiou Electrical and Computer Engineering University of Texas at Austin Supported in part by DOE, NSF, SRC,Bluespec, Intel, Xilinx, IBM, and Freescale RAMP-White
More informationMulticore SoC is coming. Scalable and Reconfigurable Stream Processor for Mobile Multimedia Systems. Source: 2007 ISSCC and IDF.
Scalable and Reconfigurable Stream Processor for Mobile Multimedia Systems Liang-Gee Chen Distinguished Professor General Director, SOC Center National Taiwan University DSP/IC Design Lab, GIEE, NTU 1
More informationXen and the Art of Virtualization. CSE-291 (Cloud Computing) Fall 2016
Xen and the Art of Virtualization CSE-291 (Cloud Computing) Fall 2016 Why Virtualization? Share resources among many uses Allow heterogeneity in environments Allow differences in host and guest Provide
More informationPorting an MPEG-2 Decoder to the Cell Architecture
Porting an MPEG-2 Decoder to the Cell Architecture Troy Brant, Jonathan Clark, Brian Davidson, Nick Merryman Advisor: David Bader College of Computing Georgia Institute of Technology Atlanta, GA 30332-0250
More informationPOSIX Threads: a first step toward parallel programming. George Bosilca
POSIX Threads: a first step toward parallel programming George Bosilca bosilca@icl.utk.edu Process vs. Thread A process is a collection of virtual memory space, code, data, and system resources. A thread
More informationMapping the AVS Video Decoder on a Heterogeneous Dual-Core SIMD Processor. NikolaosBellas, IoannisKatsavounidis, Maria Koziri, Dimitris Zacharis
Mapping the AVS Video Decoder on a Heterogeneous Dual-Core SIMD Processor NikolaosBellas, IoannisKatsavounidis, Maria Koziri, Dimitris Zacharis University of Thessaly Greece 1 Outline Introduction to AVS
More informationCSE 120 Principles of Operating Systems
CSE 120 Principles of Operating Systems Fall 2015 Lecture 4: Threads Geoffrey M. Voelker Announcements Project 0 due Project 1 out October 6, 2015 CSE 120 Lecture 4 Threads 2 Processes Recall that a process
More informationUsing Industry Standards to Exploit the Advantages and Resolve the Challenges of Multicore Technology
Using Industry Standards to Exploit the Advantages and Resolve the Challenges of Multicore Technology September 19, 2007 Markus Levy, EEMBC and Multicore Association Enabling the Multicore Ecosystem Multicore
More informationSpring 2011 Prof. Hyesoon Kim
Spring 2011 Prof. Hyesoon Kim PowerPC-base Core @3.2GHz 1 VMX vector unit per core 512KB L2 cache 7 x SPE @3.2GHz 7 x 128b 128 SIMD GPRs 7 x 256KB SRAM for SPE 1 of 8 SPEs reserved for redundancy total
More informationPerformance Issues in Parallelization. Saman Amarasinghe Fall 2010
Performance Issues in Parallelization Saman Amarasinghe Fall 2010 Today s Lecture Performance Issues of Parallelism Cilk provides a robust environment for parallelization It hides many issues and tries
More informationIntroduction to Parallel Computing. CPS 5401 Fall 2014 Shirley Moore, Instructor October 13, 2014
Introduction to Parallel Computing CPS 5401 Fall 2014 Shirley Moore, Instructor October 13, 2014 1 Definition of Parallel Computing Simultaneous use of multiple compute resources to solve a computational
More informationModern Processor Architectures. L25: Modern Compiler Design
Modern Processor Architectures L25: Modern Compiler Design The 1960s - 1970s Instructions took multiple cycles Only one instruction in flight at once Optimisation meant minimising the number of instructions
More information