DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING UNIT-1

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1 DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING Year & Semester : III/VI Section : CSE-1 & CSE-2 Subject Code : CS2354 Subject Name : Advanced Computer Architecture Degree & Branch : B.E C.S.E. UNIT-1 1. What are the approaches to exploit ILP? 2. Write down the formula to calculate the pipeline CPI? 3. What do you mean by Loop level parallelism? 4. Define the different types of dependences? 5. Define register renaming? 6. List out the constraints imposed by control dependences? 7. Define dynamic scheduling? List the advantages if dynamic scheduling? 8. When an exception is said to be imprecise? Why does the imprecise exception occur? 9. Differentiate in-order and out-order execution of instruction. 10. What are the three stages of Tomasulo algorithm? 11. What are the components of hardware based speculation? 12. List out the fields in each ROB entry? 13. What is loop unrolling? 14. What are the benefits of speculating through multiple branches? 15. What are the basic ideas in pipeline scheduling? 16. Why do we need branch prediction? Page 1

2 17. What are the strategies of branch predictor? 18. Differentiate static and dynamic branch prediction approaches 19. Give the classification of data hazards? 20. When does name dependence occur? 16 MARKS QUESTIONS 1.Describe the classical 5-stage pipelining for a RISC processor. 2. Explain in detail how the pipelining is implemented with reference to a MIPS processor? 3. Describe in detail what makes pipelining hard to implement? 4. What are exceptions? Mention its types. Explain its requirements and need for maintaining precise exceptions. 5. What is dynamic scheduling? Explain with suitable examples the Tomasulo s algorithm for MIPS processor. 6. What is branch prediction? Explain the various schemes in detail. 7. Compare Tomasulo s algorithm and hardware based speculation 8. Briefly describe any techniques to reduce the control hazard stalls. 9. Explain how ILP is achieved using dynamic scheduling. 10. Identify and justify the following fallacies/pitfalls a. Processors with lower CPI will always be faster b.processors with faster clock rate will always be better. UNIT-2 1. Explain static multiple issues with respect to VLIW approach? 2. Compare local scheduling and global scheduling. 3. What is trace scheduling? 4. Discuss the various problems associated with the VLIW processor and measures for their mitigation. Page 2

3 5. What is the need to detect loop dependences? How does the compiler detect it? 6. What is inter-procedural analysis? 7. What is copy propagation? 8. What is tree height reduction? 9. What are recurrences? 10. What is symbolic loop unrolling and mention its techniques? 11. Explain the methods involved in trace scheduling. 12. What is tail duplication? 13. What are predicated instructions? What are its limitations? Give the processors that support conditional move. 14. Mention the methods to speculate ambitiously preserving the exception behavior. 15. What are poison bits? 16. What is a sentinel? 17. What are the various components of IA-64 register model? 18. What is a register stack engine? 19. What are NaTs and NaTVals? 20. What do you mean by software pipeline loop? 16 MARK QUESTIONS: 1. With an example, explain static multiple issue in a VLIW processor? 2. Explain in detail about multiple issue in a EPIC processor? 3. Explain in detail how compiler support can be used to increase the amount of Parallelism That can be exploited in a program. 4. With examples, explain how do you detect and enhance Loop Level Parallelism? 5. Explain software pipelining techniques in detail. 6. Explain the need for hardware support for exposing more parallelism at compile time. 7. Explain briefly about conditional or predicated instructions and the limiting factors affecting their complete usefulness. Page 3

4 8. Explain compiler speculation with hardware support. 9. Compare Hardware and Software speculation mechanisms. 10. Explain Intel IA-64 Architecture in detail with suitable reference to Itanium processor. UNIT-3 1. What are centralized shared memory architectures and symmetric shared memory multiprocessors? 2. What are ownership misses and coherence misses? 3. Compare true sharing and false sharing misses. 4. What are cold misses, coherence misses and conflict misses? 5. What is the need for distributed shared-memory architectures? 6. What are local node, home node and remote node? 7. What are the various atomic synchronization primitives? 8. What is load locked and store conditional instructions? 9. What are spin locks with exponential back-off? 10. What are gather stage and release stage in barrier synchronization technique? 11. What is sense-reversing barrier? 12. What are queuing locks? How does it work? 13. What are DVMs and SVMs? 14. How performance of parallel processors is measured? 15. Compare memory constrained and time constrained scaling. 16. Give a summary of performance of distributed shared memory multiprocessors. 17. What is SMT? What are the design challenges in SMT processors? 18. Define the models used for consistency 19. What are the operations that a directory based protocol handle? 20. What are the disadvantages of symmetric shared memory? Page 4

5 16 MARK QUESTIONS: 1. Give an overview of the taxonomy of parallel architectures. 2. Explain in detail the various performance metrics for communication mechanisms and discuss their advantages and challenges of parallel processing. 3. Explain in detail the symmetric shared memory architectures with reference to multiprocessor cache coherence problem. 4 Explain in detail the schemes available for enforcing coherence. Discuss its implementation techniques with suitable state diagrams. 5. With relevant graphs, discuss the performance of symmetric shared-memory multiprocessors for various workloads. 6. Explain in detail the distributed shared memory architecture highlighting the directory based cache coherence protocol. Substantiate your explanation with suitable examples and state diagrams. 7. Explain in detail the need for synchronization and how it is achieved in a multiprocessor? Discuss the associated implementation issues. 8. Explain in detail the memory consistency models. 9. Explain how thread level parallelism within a processor can be exploited? With suitable diagrams, explain simultaneous multithreading, its design challenges and potential performance enhancements. 10. Explain Cache coherence protocols in detail. UNIT-4 1. Define the terms: Cache, Cache hit and Cache miss 2. Define Miss rate and Miss penalty. 3. Compare temporal and spatial locality. 4. What is a page fault? 5. What is a memory stall cycle and give its formula? Page 5

6 6. What is average memory access time and give its formula? 7. Give the relation between average memory access time and processor performance. 8. For an out-of-order execution processor, how do you define miss penalty? 9. What are the various cache optimizations available? Summarize them categorically. 10. How to reduce cache miss penalty? What are the various optimizations available? 11. Compare local and global miss rate. 12. What is multilevel inclusion? 13. What are critical word first and early restart techniques? 14. Define the terms: (a) Seek time (b) Rotational latency with reference to hard disk. 15. What is memory mapped I/O and Interrupt driven I/O? 16. What is Berkeley s Tertiary disk? 17.What is DMA and virtual DMA? 18. How does speculative execution of conditional instructions affect the memory system? 19. Explain hardware pre-fetching of instructions and data 20. What is hit under multiple miss or miss under miss? 16 MARK QUESTIONS: 1. Discuss in detail the various techniques available for reducing cache miss penalty? 2. Explain with a neat diagram, the interfacing of storage devices in detail. 3. Discuss how reducing cache miss penalty or miss rate by parallelism would provide scope for performance improvement in a memory module? 4. Explain how reducing hit time in a cache would speedup the memory module? 5. Describe in detail how performance improvement of main memory could be targeted? 6. With a neat hypothetical memory hierarchical picture, describe the concept of virtual memory and analyze the memory hierarchical questions with reference to it. Explain how performance improvement is achieved? 7. Explain the paged and segmented virtual memory protections each with a suitable example. Compare them. 8. Explain the Bus standards and the interfaces. With timing diagrams, explain the Page 6

7 read and write operations occurring in a typical bus. 9. Explain RAID architecture in detail. 10. Describe in detail the process involved in designing an I/O system. UNIT-5 1. What is multithreading? 2. Write short notes on multi-core processors? 3. What are the different hardware multithreading techniques? 4. What is cycle-by-cycle interleaving, 5.Write short notes on block interleaving? 6. What is simultaneous multithreading.? 7. Discuss Flynn s taxonomy? 8. List out the components of IBM cell processor. 9. What do you mean by SISD, MIMD? 10. List out the disadvantages of heterogenous multi-core processors. 11. Define SIMD? 12. What is Simultaneous multithreading? 13. Define Chip multiprocessing 14. List out the goals of Multithreaded architecture 15. Differentiate fine grained and coarse grained multithreading 16. What are the goals of multi-core architectures 17. Define memory flow controller? 18. What are the design challenges of SMT? 19. List the factor that limits the issue slot usage? 20. How can the performance of SMT be improved? Page 7

8 16 MARK QUESTIONS: 1. Explain Multicore architecture concept and its importance? 2. Discuss in detail the benefits of multicore architectures? 3. Explain in detail about software multithreading? 4. Discuss Flynn s taxonomy? 5. Explain in detail the hardware multithreading techniques? 6. Discuss the design issues of CMP and SMT architecture? 7. Discuss the concept involved in Intel multi-core architecture. 8. Describe in detail about SUN CMP architecture 9.Discuss in detail about heterogenous multi-core processors. 10. Explain with diagram the CMP architecture and SMT architecture? Page 8

ROEVER ENGINEERING COLLEGE DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING

ROEVER ENGINEERING COLLEGE DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING 16 MARKS CS 2354 ADVANCE COMPUTER ARCHITECTURE 1. Explain the concepts and challenges of Instruction-Level Parallelism. Define