Functional modeling style for efficient SW code generation of video codec applications

Transcription

1 Functional modeling style for efficient SW code generation of video codec applications Sang-Il Han 1)2) Soo-Ik Chae 1) Ahmed. A. Jerraya 2) SD Group 1) SLS Group 2) Seoul National Univ., Korea TIMA laboratory, France

2 Summary Challenges in video codec system design Complex High-performance within short design time Classical RTL design methodology is too slow Requirements in video codec system design System level design methodology with functional model Explicit parallelism and conditional in functional model Existing modeling styles Data-driven model lacks explicit conditional (ex: SDF lacks conditionals) Event-driven model lacks explicit parallelism (ex: SM lacks distributed imp.) Proposed modeling style Abstract clock synchronous model (ACSM): An extension of CSM for RTL Both parallelism and conditional with an abstract global clock 02/01/06 2

3 The scope of this work System-level design methodology Target Application Target Architecture Modeling ACSM Model Scope Mapping Evaluation Mixed Algo./Arch. Model Automatic Generation Scope Modeling style to generate efficient SW code. Implementation of System 02/01/06 3

4 Introduction Proposed modeling style Contents Comparison with existing modeling styles Experiment Conclusion and Perspective 02/01/06 4

5 Target application Macroblock-based video codecs MPEG-2, H.263, MPEG-4, H.264, and WMV9 W Frame/Slice VLD Macroblock VLD Inverse Scan Quantization Inverse Transform + Deblocking Filter H Video Bit Stream Spatial Prediction Modes Decoded Frame Store Multiple Previous Frame Store Spatial Compensation Process Motion Compensation Process Switch Intra/ Inter MB A frame = WxH macroblocks Exploit temporal redundancy Exploit spatial redundancy Current Frame Store Motion Vectors Block diagram of an H.264 decoder 02/01/06 5

6 Challenges and Requirements (1) 1) Computation Complexity Ex: 10 Gops/sec for 4VGA decoding Explicit parallelism Parallel and pipelined computation execution 2) Communication Complexity Ex: 500 MB/sec external memory bandwidth for 4VGA decoding Explicit and predictable communication Parallel computation and communication execution Efficient communication scheme e.g. burst transfer 02/01/06 6

7 Challenges and Requirements (2) 3) Specification Complexity Ex: Curr. MB has dependency with prev., upper., upper prev. MB Higher level synchronization Function- and thread-level synchronization 4) Control Complexity Ex: 4x4 intra, 16x16 intra, 4x4 inter, 8x8 inter, MB prediction modes Explicit data-dependent comp./comm. Sophisticated control operations e.g. memory management 02/01/06 7

8 Contribution Propose modeling style for video codecs Abstract clock synchronous model (ACSM) An extension of clocked synchronous model for RTL Coarser clock: Abstract clock 1)Partially ordered dependency at function level Computation Complexity, 2)Explicit comm. channel with fixed buffer size Communication Complexity 3)Coarser clock granularity than physical clock Specification Complexity 4)Explicit conditionals through global abstract clock Control Complexity 02/01/06 8

9 Introduction Contents Proposed modeling style Comparison with existing modeling styles Experiment Conclusion and Perspective 02/01/06 9

10 Proposed modeling style Abstract clock synchronous model Structure Network of state-less functions Memory elements Abstract clock F 0 F 2 Delay F 1 F 3 Abstract clock Hypothesis : Lock step execution model In every abstract clock cycle, new values propagate in the network 02/01/06 10

11 RTL model vs ACSM Difference: Granularity of clock and components RTL model ACSM * - / + Delay F 0 F 2 F 1 F 3 Delay clk Abstract clock Network of combinational gates Memory elements (delay) No loops in combinational logics Synch: Lock step model Synch. interval: clock Network of state-less functions Memory elements (delay) No loops in network of functions Synch: Lock step model Synch. interval: abstract clock 02/01/06 11

12 Basic components i 0,,, i n If/ else F 0 o 0,,, Z -K F 0 F 1 o m Z -K (a) module (b) delay (c) arc IAS 1 Data D Demux F 2 Control F 1 F M Mux 3 token = (tag, value) Merge 0..3 FIS 1 IAS i F 4 F 5 D F 0 M (d) If-action subsystem (IAS) (e) For-iterator subsystem (FIS) Rule on execution: If one token on all input ports, fired. Except Merge block Rule on absent token: absent token with global abstract clock. absent token = (tag, empty value) 02/01/06 12

13 Abstract clock for video codecs Hierarchical iterations in video decoder and encoder Frame level index: too coarse to express parallelism. Sub-macroblock level index: irregular delay depth Macroblock level index: proper granularity and regular delay depth QCIF image (a) Decoding order of macroblock PrevMB UperMB Delay depth : 166 Delay depth : (b) Decoding order of 4x4 block Abstract clock for video codecs: Macroblock index 02/01/06 13

14 Implementations of RTL model and ACSM RTL model ACSM model + - / * Delay F 0 F 2 F 1 F 3 Delay clk Abstract clock 16bit Carry lookahead Adder RISC processor add div sub mul register F 0 F 2 IP 1 IP 3 SRAM 02/01/06 clk Abstract clock 14

15 A simplified ACSM of H.264 decoder Fr. VLD Video Bit Stream Z -1 Z -W Z -1 Z -W MB VLD x8 IQ 8x8 IT + FIS 1 M 8x8 DF Video Out Intra/ Inter MB D If/ else 4 MC Types D 8x8 SC IAS 1 In the full model 16MVs D 0..3 D 8x8 IF 4x4 IF 8x8 MC 4x4 MC IAS 2 IAS 3 FIS 1 M 83 Modules 24 delays 286 arcs 43 IASs 5 FISs Previous Frames Current Frame 02/01/06 15

16 Introduction Proposed modeling style Contents Comparison with existing modeling styles Experiment Conclusion and Perspective 02/01/06 16

17 Synchronous Dataflow (SDF) If/else Z -j If/else Z -j F 2 F 2 F 1 F 4 F 1 F mux F 6 F 3 F 3 Z -k Z -k (a) ACSM (b) SDF SDF: Concurrent actors communicate with one-way FIFO channels Rule on execution: If sufficient non-zero tokens on all input ports, fired Rule on absent token: No concept of absent token. Difficulty: No explicit conditionals (!req. 4) Redundant computation : One of F 2 and F 3 Redundant commutation : One of (Z -j F 2 ) and (Z -k F 3 ) 02/01/06 17

18 Boolean Dataflow (BDF) If/else Z -j If/else Z -j F 1 F 2 F 3 F 4 F 1 SWITCH T F F 2 F 3 T F SELECT F 4 Z -k Z -k (a) ACSM (b) BDF BDF: Concurrent actors communicate with one-way FIFO channels Rule on execution: If sufficient non-zero tokens on all input ports, fired Except SWITCH and SELECT blocks Rule on absent token: Absent token without global clock. Difficulty: Buffer overflow problem. (!req. 4) Accumulate tokens between (Z -j F 2 ) and (Z -k F 3 ) To solve this problem, a lot of additional switches: 138 switches/83 modules in case of H.264 decoder 02/01/06 18

19 Other modeling styles Khan Process Network (KPN) Difficulty1: Task-level coarse granularity (!req 1) Difficulty2: Comp./comm./control mixed (!req 2,!req4) Synchronous Dataflow with embedded control (SDF+eCtrl) Difficulty1: Coarser granularity. (!req. 1) Difficulty2: Still Redundant communication (!req. 4) Synchronous model (SM) Rule on execution: If one present token on one or more input ports, fired Rule on absent token: Absent tokens with virtual clock. Difficulty: distributed implementation (!req 1) 02/01/06 19

20 Summary of Modeling styles Models KPN SDF SDF BDF SM RTL ACSM Requirements +ectrl Explicit fine-grain parallelism Explicit communication Higher level synchronization Explicit datadependent op. Model Type Data-driven Event-driven Clock-driven Clock No global clock Virtual clks Physic clk Abstract clk Analysis No absent token (or without clock) Explicit conditionals Unrestricted absent token Restricted absent token with global clock Distributed Execution Data-driven 02/01/06 system Absent token Event-driven 20

21 Contents Introduction Proposed modeling style Comparison with existing modeling styles Experiment Conclusion and Perspective 02/01/06 21

22 Experiment environment Target application H.264 baseline decoder Foreman QCIF format with QP=28 and IntraPeriod=5 All search modes are supported. Xtensa Target architecture Tensilica Xtensa single processor DMA + memory I/F Mapping Frames are stored in global memory. Image fetch process is executed on DMA. All other processes are executed on Xtensa. In Out Global Mem0 Interconnection DMA/ Mem I/F Proc0 local mem 02/01/06 22

23 Experiment Handed code H.264 decoder SDF (4x4 w/o IAS) Modeling SW code by RTW C codes ACSM (4x4) Profile with Xtensa ISS Cycle and Memory access Xtensa Single proc. Simulink models Opt. ACSM (4x4, 8x8) 02/01/ Execution cycle SDF ACSM Opt. ACSM Handed code 100 External memory access SDF ACSM Opt. ACSM Handed code Etc Rec IT VLD Chrom DF Luma DF Chrom MC Luma MC Top control Write Chrom Write Luma Read Chrom Read Luma

24 Experiment result: Comparison Compared to SDF Reduce 32% execution time Due to Redundant computation of SDF Reduce 46% external memory access Due to redundant communication of SDF Compared to SDF+eCtrl Similar execution time, but SDF+eCtrl limits design space. Reduce 46% external memory access Due to redundant communication of SDF+eCtrl Compared to BDF Buffer overflow, or a lot of switches required (138 switches/83 modules) 02/01/06 24

25 Contents Introduction Contribution Basics of target application and architecture Proposed modeling style Comparison with existing modeling styles Experiment Conclusion and Perspective 02/01/06 25

26 Conclusion Conclusion and perspective ACSM suitable for video codec application An high level RTL model Satisfies the requirements of functional model Efficient SW code generation from Simulink with RTW Reduce 32% execution time than SDF Reduce 46% external memory access than SDF Perspective SW generation tool for distributed implementation. 02/01/06 26

27 Thank you!!! Question? 02/01/06 27