Automated Design Flow for Coarse-Grained Reconfigurable Platforms: an RVC-CAL Multi-Standard Decoder Use-Case

Transcription

1 XIV International Conference on Embedded Computer and Systems: Architectures, MOdeling and Simulation SAMOS XIV July 14 th - Samos Island (Greece) Carlo Sau, Luigi Raffo DIEE Università degli Studi di Cagliari Francesca Palumbo POLCOMING Università degli Studi di Sassari Endri Bezati, Simone Casale-Brunet, Marco Mattavelli SCI STI MM École Politecnique Fédérale de Lausanne Automated Design Flow for Coarse-Grained Reconfigurable Platforms: an RVC-CAL Multi-Standard Decoder Use-Case

2 Introduction Problem Statement Two Step Problem Solving Outline Step 1: Coarse-Grained Reconfigurability Step 2: Dataflow Model of Computation and RVC-CAL Generation of Multi-Dataflow Graphs Automated Design Flow Composition: the Multi-Dataflow Composer Optimization: TURNUS Co-Exploration Framework RTL Generation: Xronos High Level Synthesis Tools Integration Experimental Results An MPEG-4 SP Decoder Use Case Synthesis Results Performance Results Conclusions 1

3 Introduction Problem Statement Two Step Problem Solving Outline Step 1: Coarse-Grained Reconfigurability Step 2: Dataflow Model of Computation and RVC-CAL Generation of Multi-Dataflow Graphs Automated Design Flow Composition: the Multi-Dataflow Composer Optimization: TURNUS Co-Exploration Framework RTL Generation: Xronos High Level Synthesis Tools Integration Experimental Results An MPEG-4 SP Decoder Use Case Synthesis Results Performance Results Conclusions 2

4 Problem Statement Electronic devices are converging to platforms that are: portable: dimensions and battery life limits have to be taken into consideration. multimedial: different applications have to be executed, very often at the same time. higly efficient: real time response is needed in many cases.. easily evolvable: technology and algorithms fast evolution have to be followed by the devices. 3 SOURCE: Merging Media 2013 in Vancouver Canada by Gary Hayes

5 Problem Statement Electronic devices are converging to platforms that are: portable: dimensions and battery life limits have to be taken into consideration. multimedial: different applications have to be executed, very often at the same time. higly efficient: real time response is needed in many cases.. easily evolvable: technology and algorithms fast evolution have to be followed by the SOURCE: Merging Media 2013 in Vancouver Canada by Gary Hayes devices. 3

6 Problem Statement Electronic devices are converging to platforms that are: portable: dimensions and battery life limits have to be taken into consideration. multimedial: different applications have to be executed, very often at the same time. higly efficient: real time response is needed in many cases.. easily evolvable: technology and algorithms fast evolution have to be followed by the SOURCE: Merging Media 2013 in Vancouver Canada by Gary Hayes devices. need of new design flows to address this complex scenario 3

7 Two Step Problem Solving Step 1: Coarse-Grained Reconfigurability Systems are required to be flexible and efficient. 4

8 Flexibility Two Step Problem Solving Step 1: Coarse-Grained Reconfigurability Systems are required to be flexible and efficient. Reconfigurable Paradigm (RP) to hardware design: specialized computing platforms, capable of changing configuration to serve the targeted computations. GPP DSP RP ASIC Performance 4

9 Flexibility Two Step Problem Solving Step 1: Coarse-Grained Reconfigurability Systems are required to be flexible and efficient. Reconfigurable Paradigm (RP) to hardware design: specialized computing platforms, capable of changing configuration to serve the targeted computations. The more the hardware is specialized, the more it is difficult to program. GPP DSP RP ASIC Performance FINE- GRAINED (FG) Bit-level COARSE- GRAINED (CG) Word-level Flexibility Reconf. Speed Config. Storage 4

10 Two Step Problem Solving Step 2: Dataflow Model of Computation and RVC-CAL (1) A dataflow program is a directed graph of functional units (actors) exchanging sequences of data (tokens) through dedicated channels. actions state Actors encapsulate their state and communicate exclusively by sending and receiving tokens. Such an absence of race conditions, along with the intrinsic modularity of the dataflow graphs, make it possible to explicit the algorithmic parallelism of the programs. 5

11 Two Step Problem Solving Step 2: Dataflow Model of Computation and RVC-CAL (2) CAL[1] = Cal Actor Language, high-level programming language for describing dataflow actors. Decoder Composition Mechanism VTL [2] (RVC-CAL FUs) Abstract Decoder Model (XDF + RVC-Cal) Decoder Implementation Standard RVC Model Proprietary Tool Library Decoder Solution Proprietary Decoder [1] MPEG-B part 4 (2009), [2] MPEG-C part 4 (2010) 6

12 Generation of Multi-Dataflow Graphs (1) RVC-CAL dataflow specifications A C D B 7

13 Generation of Multi-Dataflow Graphs (1) RVC-CAL dataflow specifications HW platform A A C D 1:1 C D B B clock 7

14 Generation of Multi-Dataflow Graphs (1) RVC-CAL dataflow specifications HW platform A A C D 1:1 C D B B clock A C D B B E D 7

15 Generation of Multi-Dataflow Graphs (1) RVC-CAL dataflow specifications HW platform A A C D 1:1 C D B B clock A B C D 2:1 HW CG reconfigurable platform A clock C B E D B D E 7

16 Generation of Multi-Dataflow Graphs (2) Challenges of the modern electronic devices design: low area and power (portability) flexibility (multimediality) performances (high efficiency) code reusability (fast evolution) 8

17 Generation of Multi-Dataflow Graphs (2) Challenges of the modern electronic devices design: resource sharing low area and power (portability) CG reconfiguration flexibility (multimediality) dataflow parallelism highlighting performances (high efficiency) dataflow modularity (VTL) code reusability (fast evolution) 8

18 Generation of Multi-Dataflow Graphs (2) Challenges of the modern electronic devices design: resource sharing low area and power (portability) CG reconfiguration flexibility (multimediality) dataflow parallelism highlighting performances (high efficiency) dataflow modularity (VTL) code reusability (fast evolution) perfect matching, but 8

19 Generation of Multi-Dataflow Graphs (2) Challenges of the modern electronic devices design: resource sharing low area and power (portability) CG reconfiguration flexibility (multimediality) dataflow parallelism highlighting performances (high efficiency) dataflow modularity (VTL) code reusability (fast evolution) perfect matching, but what happens if the design complexity grows? 8

20 Generation of Multi-Dataflow Graphs (2) Challenges of the modern electronic devices design: resource sharing low area and power (portability) CG reconfiguration flexibility (multimediality) dataflow parallelism highlighting performances (high efficiency) dataflow modularity (VTL) code reusability (fast evolution) perfect matching, but what happens if the design complexity grows? 8

21 Generation of Multi-Dataflow Graphs (2) Challenges of the modern electronic devices design: resource sharing low area and power (portability) CG reconfiguration flexibility (multimediality) dataflow parallelism highlighting performances (high efficiency) code reusability (fast evolution) need of an automated design flow dataflow modularity (VTL) perfect matching, but what happens if the design complexity grows? 8

22 Introduction Problem Statement Two Step Problem Solving Outline Step 1: Coarse-Grained Reconfigurability Step 2: Dataflow Model of Computation and RVC-CAL Generation of Multi-Dataflow Graphs Automated Design Flow Composition: the Multi-Dataflow Composer Optimization: TURNUS Co-Exploration Framework RTL Generation: Xronos High Level Synthesis Tools Integration Experimental Results An MPEG-4 SP Decoder Use Case Synthesis Results Performance Results Conclusions 9

23 Automated Design Flow Functionalities required by the automated design flow: 10

24 Automated Design Flow Functionalities required by the automated design flow: multi-dataflow network composition A C D B B E D A B C E D 10

25 Automated Design Flow Functionalities required by the automated design flow: multi-dataflow network composition dataflow network buffers optimization A C D B B E D A C B D E A B A B C E C E D D 10

26 Automated Design Flow Functionalities required by the automated design flow: multi-dataflow network composition dataflow network buffers optimization A C D B B E D A C B D E A B A B C E C E D D multi-dataflow corresponding RTL generation A C A B D B E C E clock D 10

27 Composition: the Multi-Dataflow Composer (1) ORCC back-ends front-end C Java LLVM Open RVC-CAL Compiler (ORCC) is a framework able to generate, from an RVC-CAL specification, the corresponding source code for different target platforms (hardware, software or mixed). 11

28 Composition: the Multi-Dataflow Composer (1) RVC-CAL specification ORCC CAL Actors back-ends front-end XDF Graph C Java LLVM Open RVC-CAL Compiler (ORCC) is a framework able to generate, from an RVC-CAL specification, the corresponding source code for different target platforms (hardware, software or mixed). 11

29 Composition: the Multi-Dataflow Composer (1) RVC-CAL specification ORCC CAL Actors back-ends front-end Intermediate Representation XDF Graph C Java LLVM Open RVC-CAL Compiler (ORCC) is a framework able to generate, from an RVC-CAL specification, the corresponding source code for different target platforms (hardware, software or mixed). 11

30 Composition: the Multi-Dataflow Composer (1) RVC-CAL specification 1:1 ORCC CAL Actors back-ends front-end Intermediate Representation XDF Graph C Java LLVM Open RVC-CAL Compiler (ORCC) is a framework able to generate, from an RVC-CAL specification, the corresponding source code for different target platforms (hardware, software or mixed). Source Code 11

31 Composition: the Multi-Dataflow Composer (1) front-end ORCC back-ends C Java LLVM 11

32 front-end back-end Composition: the Multi-Dataflow Composer (1) ORCC back-ends front-end C Java LLVM MDC MDC exploits the ORCC frontend to generate, from a set of RVC-CAL specifications, the hardware description of a reconfigurable platform. 11

33 front-end back-end Composition: the Multi-Dataflow Composer (1) RVC-CAL specifications CAL Actors XDF Graphs ORCC back-ends front-end C Java LLVM MDC MDC exploits the ORCC frontend to generate, from a set of RVC-CAL specifications, the hardware description of a reconfigurable platform. 11

34 front-end back-end Composition: the Multi-Dataflow Composer (1) RVC-CAL specifications CAL Actors XDF Graphs ORCC back-ends front-end Intermediate Representation C Java LLVM MDC MDC exploits the ORCC frontend to generate, from a set of RVC-CAL specifications, the hardware description of a reconfigurable platform. 11

35 front-end back-end Composition: the Multi-Dataflow Composer (1) RVC-CAL specifications CAL Actors XDF Graphs ORCC back-ends front-end Intermediate Representation C Java LLVM Multi- Dataflow XDF Graph MDC MDC exploits the ORCC frontend to generate, from a set of RVC-CAL specifications, the hardware description of a reconfigurable platform. 11

36 front-end back-end Composition: the Multi-Dataflow Composer (1) RVC-CAL specifications n:1 ORCC CAL Actors back-ends front-end Intermediate Representation XDF Graphs C Java LLVM Multi- Dataflow XDF Graph MDC HW Reconfigurable Platform (HDL) HDL Components Library MDC exploits the ORCC frontend to generate, from a set of RVC-CAL specifications, the hardware description of a reconfigurable platform. 11

37 Composition: the Multi-Dataflow RVC-CAL dataflow specifications A dataflow α C D B dataflow β B E D Composer (2) 12

38 MDC front-end Composition: the Multi-Dataflow RVC-CAL dataflow specifications A dataflow α C D Composer (2) multi-dataflow specification A C B dataflow β B s0 s1 D B E D E 12

39 MDC front-end Composition: the Multi-Dataflow RVC-CAL dataflow specifications A dataflow α C D Composer (2) multi-dataflow specification A C B dataflow β B s0 s1 D B E D E MDC back-end A B 0 1 s0 HW CG reconfigurable platform C E s1 0 1 clock D config LUT α β s1 0 1 s

40 Optimization: TURNUS Co-Exploration Framework TURNUS front-end back-end TURNUS is a design space exploration framework for heterogeneous parallel systems. It provides high-level modeling and simulation methods and tools for system level performances estimation and optimization. 13

41 Optimization: TURNUS Co-Exploration Framework TURNUS front-end back-end It provides the execution causation traces for a given dataflow specification in relation to a particular input stimulus. The causation traces are graphs describing the dependencies among the actions executed during the input stimulus processing. 13

42 Optimization: TURNUS Co-Exploration Framework RVC-CAL specification CAL Actors XDF Graph Input stimulus TURNUS front-end back-end It provides the execution causation traces for a given dataflow specification in relation to a particular input stimulus. The causation traces are graphs describing the dependencies among the actions executed during the input stimulus processing. 13

43 Optimization: TURNUS Co-Exploration Framework RVC-CAL specification CAL Actors XDF Graph Input stimulus TURNUS front-end Simulation back-end It provides the execution causation traces for a given dataflow specification in relation to a particular input stimulus. The causation traces are graphs describing the dependencies among the actions executed during the input stimulus processing. 13

44 Optimization: TURNUS Co-Exploration Framework RVC-CAL specification CAL Actors XDF Graph Input stimulus TURNUS front-end Simulation back-end It provides the execution causation traces for a given dataflow specification in relation to a particular input stimulus. The causation traces are graphs describing the dependencies among the actions executed during the input stimulus processing. Execution Causation Traces 13

45 Optimization: TURNUS Co-Exploration Framework TURNUS front-end back-end The causation traces postprocessing analyses the causation traces along with given action weights (latency of the actions for a specific target platform) in order to optimize the size of the FIFO memories in the dataflow network through a Design Space Exploration. Execution Causation Traces 13

46 Optimization: TURNUS Co-Exploration Framework Actions weights TURNUS front-end back-end The causation traces postprocessing analyses the causation traces along with given action weights (latency of the actions for a specific target platform) in order to optimize the size of the FIFO memories in the dataflow network through a Design Space Exploration. Execution Causation Traces 13

47 Optimization: TURNUS Co-Exploration Framework Actions weights TURNUS front-end Design Space Exploration back-end The causation traces postprocessing analyses the causation traces along with given action weights (latency of the actions for a specific target platform) in order to optimize the size of the FIFO memories in the dataflow network through a Design Space Exploration. Execution Causation Traces 13

48 Optimization: TURNUS Co-Exploration Framework Actions weights Execution Causation Traces TURNUS front-end Design Space Exploration back-end Optimal FIFO Sizes The causation traces postprocessing analyses the causation traces along with given action weights (latency of the actions for a specific target platform) in order to optimize the size of the FIFO memories in the dataflow network through a Design Space Exploration. 13

49 RTL Generation: Xronos High Level Synthesis (1) Xronos front-end back-end Xronos is a framework for the generation of RTL descriptions from dataflow or sequential applications. It supports three basic data types (int, uint and bool), flow control statements (branches, loops, parallel blocks) and procedural abstractions (sequences of statements) called tasks. 14

50 RTL Generation: Xronos High Level Synthesis (1) RVC-CAL specification CAL Actors Xronos front-end back-end XDF Graph Xronos is a framework for the generation of RTL descriptions from dataflow or sequential applications. It supports three basic data types (int, uint and bool), flow control statements (branches, loops, parallel blocks) and procedural abstractions (sequences of statements) called tasks. 14

51 RTL Generation: Xronos High Level Synthesis (1) RVC-CAL specification CAL Actors Xronos front-end Intermediate Representation back-end XDF Graph Xronos is a framework for the generation of RTL descriptions from dataflow or sequential applications. It supports three basic data types (int, uint and bool), flow control statements (branches, loops, parallel blocks) and procedural abstractions (sequences of statements) called tasks. 14

52 RTL Generation: Xronos High Level Synthesis (1) RVC-CAL specification 1:1 CAL Actors Xronos Actors.v front-end Intermediate Representation back-end Top.vhd XDF Graph Test.v Xronos is a framework for the generation of RTL descriptions from dataflow or sequential applications. It supports three basic data types (int, uint and bool), flow control statements (branches, loops, parallel blocks) and procedural abstractions (sequences of statements) called tasks. 14

53 RTL Generation: Xronos High Level Synthesis (2) RVC-CAL dataflow specification A A HW platform C D C D B B clock 15

54 RTL Generation: Xronos High Level Synthesis (2) RVC-CAL dataflow specification A A HW platform C D C D B B clock queue_actor_x_in1 in_data in_send in_ack in_rdy in_count out_data out_send out_ack out_count in1_data in1_send in1_ack in1_count Actor_X out1_data out1_send out1_ack out1_rdy out1_count fanout_actor_x_out1 in_data in_send in_ack in_rdy in_count out_data out_send out_ack out_rdy out_count queue_actor_x_inn in_data in_send in_ack in_rdy in_count out_data out_send out_ack out_count inn_data inn_send inn_ack inn_count outm_data outm_send outm_ack outtm_rdy outm_count fanout_actor_x_outm in_data in_send in_ack in_rdy in_count out_data out_send out_ack out_rdy out_count 15

55 front-end back-end Tools Integration XDF CAL RVC-CAL specifications ORCC front-end IR back-ends XDF multi dataflow MDC START: MDC compeses the multi-dataflow network 16

56 front-end back-end Tools Integration TRACES TURNUS Co- Exploration Framework XDF CAL RVC-CAL specifications ORCC front-end IR back-ends XDF multi dataflow MDC STEP 1: TURNUS generates the execution causation traces 16

57 front-end back-end Tools Integration TRACES TURNUS Co- Exploration Framework WEIGHTS XRONOS High Level Synthesis XDF front-end CAL RVC-CAL specifications ORCC IR back-ends XDF multi dataflow MDC STEP 2: Xronos generates the actions weights 16

58 front-end back-end Tools Integration TRACES TURNUS Co- Exploration Framework WEIGHTS FIFO SIZES XRONOS High Level Synthesis XDF front-end CAL RVC-CAL specifications ORCC IR back-ends XDF multi dataflow MDC STEP 3: TURNUS generates the FIFO optimal sizes 16

59 front-end back-end Tools Integration TRACES TURNUS Co- Exploration Framework WEIGHTS FIFO SIZES XRONOS High Level Synthesis HDL Components Library HW CG Reconfigurable Platform (with SBox queues/fanouts) XDF front-end CAL RVC-CAL specifications ORCC IR back-ends XDF multi dataflow MDC STEP 4: Xronos generates the RVC compliant reconfigurable hardware platform 16

60 front-end back-end Tools Integration TRACES TURNUS Co- Exploration Framework WEIGHTS FIFO SIZES XRONOS High Level Synthesis HDL Components Library HW CG Reconfigurable Platform (with SBox queues/fanouts) XDF front-end CAL RVC-CAL specifications ORCC IR back-ends STEP 5: MDC generates the optimized reconfigurable hardware platform XDF multi dataflow MDC opt HW CG Reconfigurable Platform (without Sbox queues/fanouts) 16

61 Introduction Problem Statement Two Step Problem Solving Outline Step 1: Coarse-Grained Reconfigurability Step 2: Dataflow Model of Computation and RVC-CAL Generation of Multi-Dataflow Graphs Automated Design Flow Composition: the Multi-Dataflow Composer Optimization: TURNUS Co-Exploration Framework RTL Generation: Xronos High Level Synthesis Tools Integration Experimental Results An MPEG-4 SP Decoder Use Case Synthesis Results Performance Results Conclusions 17

62 An MPEG-4 SP Decoder Use Case (1) TEX Y MOT Y input stream PARSER TEX U MOT U MERGER 420 video output TEX V MOT V intra 18

63 An MPEG-4 SP Decoder Use Case (1) TEX Y MOT Y input stream PARSER TEX U MOT U MERGER 420 video output PARSER: syntactical parser variable length coding TEX V MOT V intra 18

64 An MPEG-4 SP Decoder Use Case (1) TEX Y MOT Y input stream PARSER TEX U MOT U MERGER 420 video output TEX V MOT V intra TEX (residual decoding): AC-DC prediction inverse scan inverse quantization IDCT 18

65 An MPEG-4 SP Decoder Use Case (1) TEX Y MOT Y input stream PARSER TEX U MOT U MERGER 420 video output TEX V MOT V intra MOT (motion compensation): framebuffer interpolation residual error addition 18

66 An MPEG-4 SP Decoder Use Case (1) TEX Y MOT Y input stream PARSER TEX U MOT U MERGER 420 video output TEX V MOT V intra MERGER 420: 420 decoded components merging 18

67 An MPEG-4 SP Decoder Use Case (2) Different designs composition in terms of functionality and role of the involved actors. design ordinary* SBox number of actors not shared** shared** overall intra full parallel reconf opt_reconf * computational actors (not SBoxes). ** referred only to the computational actors (not to SBoxes). 19

68 An MPEG-4 SP Decoder Use Case (2) Different designs composition in terms of functionality and role of the involved actors. design ordinary* SBox number of actors not shared** shared** overall intra full parallel reconf opt_reconf * computational actors (not SBoxes). ** referred only to the computational actors (not to SBoxes). 19

69 An MPEG-4 SP Decoder Use Case (2) Different designs composition in terms of functionality and role of the involved actors. design ordinary* SBox number of actors not shared** shared** overall intra full parallel reconf opt_reconf * computational actors (not SBoxes). ** referred only to the computational actors (not to SBoxes). 19

70 An MPEG-4 SP Decoder Use Case (2) Different designs composition in terms of functionality and role of the involved actors. design ordinary* SBox number of actors not shared** shared** overall intra full parallel reconf opt_reconf * computational actors (not SBoxes). ** referred only to the computational actors (not to SBoxes). 19

71 An MPEG-4 SP Decoder Use Case (2) Different designs composition in terms of functionality and role of the involved actors. design ordinary* SBox number of actors not shared** shared** overall intra full parallel reconf opt_reconf * computational actors (not SBoxes). ** referred only to the computational actors (not to SBoxes). 19

72 resource Synthesis Results (1) Results retrieved from the Xilinx Synthesis Technology tool targeting a Xilinx Virtex FPGA board. design parallel reconf Δ% opt_reconf Δ% Slices Slice Regs Slice LUTs LUT-FF pairs BRAMs DSPs Max freq [MHz] 25,43 25, ,38 0 Δ% percentage increment/reduction between the parallel and the reconfigurable designs. 20

73 resource Synthesis Results (1) Results retrieved from the Xilinx Synthesis Technology tool targeting a Xilinx Virtex FPGA board. design parallel reconf Δ% opt_reconf Δ% Slices Slice Regs Slice LUTs LUT-FF pairs BRAMs DSPs Max freq [MHz] 25,43 25, ,38 0 Δ% percentage increment/reduction between the parallel and the reconfigurable designs. 20

74 resource Synthesis Results (1) Results retrieved from the Xilinx Synthesis Technology tool targeting a Xilinx Virtex FPGA board. design parallel reconf Δ% opt_reconf Δ% Slices Slice Regs Slice LUTs LUT-FF pairs BRAMs DSPs Max freq [MHz] 25,43 25, ,38 0 Δ% percentage increment/reduction between the parallel and the reconfigurable designs. 20

75 resource Synthesis Results (1) Results retrieved from the Xilinx Synthesis Technology tool targeting a Xilinx Virtex FPGA board. design parallel reconf Δ% opt_reconf Δ% Slices Slice Regs Slice LUTs LUT-FF pairs BRAMs DSPs Max freq [MHz] 25,43 25, ,38 0 Δ% percentage increment/reduction between the parallel and the reconfigurable designs. 20

76 resource power Synthesis Results (2) Results retrieved from the XPower Analyzer tool targeting a Xilinx Virtex FPGA board for a QCIF video sequence decoding. design parallel reconf Δ% opt_reconf Δ% Clock 0,382 0, , Logic 0,045 0, , Signals 0,050 0, , BRAMs 0,090 0, , TOT 0,567 0, , Δ% percentage increment/reduction between the parallel and the reconfigurable designs. 21

77 resource power Synthesis Results (2) Results retrieved from the XPower Analyzer tool targeting a Xilinx Virtex FPGA board for a QCIF video sequence decoding. design parallel reconf Δ% opt_reconf Δ% Clock 0,382 0, , Logic 0,045 0, , Signals 0,050 0, , BRAMs 0,090 0, , TOT 0,567 0, , Δ% percentage increment/reduction between the parallel and the reconfigurable designs. 21

78 resource power Synthesis Results (2) Results retrieved from the XPower Analyzer tool targeting a Xilinx Virtex FPGA board for a QCIF video sequence decoding. design parallel reconf Δ% opt_reconf Δ% Clock 0,382 0, , Logic 0,045 0, , Signals 0,050 0, , BRAMs 0,090 0, , TOT 0,567 0, , Δ% percentage increment/reduction between the parallel and the reconfigurable designs. 21

79 video sequence resolution Performance Results Results are given in frames per second (fps) and are obtained as the average of fps for the intra and the full decoder configurations. design parallel reconf Δ% opt_reconf Δ% QCIF CIF Δ% percentage increment/reduction between the parallel and the reconfigurable designs. 22

80 video sequence resolution Performance Results Results are given in frames per second (fps) and are obtained as the average of fps for the intra and the full decoder configurations. design parallel reconf Δ% opt_reconf Δ% QCIF CIF Δ% percentage increment/reduction between the parallel and the reconfigurable designs. 22

81 Introduction Problem Statement Two Step Problem Solving Outline Step 1: Coarse-Grained Reconfigurability Step 2: Dataflow Model of Computation and RVC-CAL Generation of Multi-Dataflow Graphs Automated Design Flow Composition: the Multi-Dataflow Composer Optimization: TURNUS Co-Exploration Framework RTL Generation: Xronos High Level Synthesis Tools Integration Experimental Results An MPEG-4 SP Decoder Use Case Synthesis Results Performance Results Conclusions 23

82 Conclusions Challenge of modern electronic systems development: coupling portability, flexibility and efficiency with the minimum design effort. 24

83 Conclusions Challenge of modern electronic systems development: coupling portability, flexibility and efficiency with the minimum design effort. A solution is possible by exploiting the dataflow programming paradigm along with the coarse-grained reconfigurability. 24

84 Conclusions Challenge of modern electronic systems development: coupling portability, flexibility and efficiency with the minimum design effort. A solution is possible by exploiting the dataflow programming paradigm along with the coarse-grained reconfigurability. An automated design flow has been assembled, by the integration of different RVC-CAL tools (MDC, TURNUS, Xronos). 24

85 Conclusions Challenge of modern electronic systems development: coupling portability, flexibility and efficiency with the minimum design effort. A solution is possible by exploiting the dataflow programming paradigm along with the coarse-grained reconfigurability. An automated design flow has been assembled, by the integration of different RVC-CAL tools (MDC, TURNUS, Xronos). The proposed design flow has been validated on a real use case involving two configurations of the MPEG-4 Simple Profile decoder. Results highlighted the effectiveness of the approach by achieving more than 25% of saving in terms of resource utilization and more than 20% of saving in terms power consumption. The generated reconfigurable designs present a very small performance penalty (5-6%) with respect to the original decoder designs. 24

86 Acknowledgements The research leading to these results has received funding from: the Region of Sardinia L.R.7/2007 under grant agreement CRP [RPCT Project]. the Region of Sardinia, Young Researchers Grant, POR Sardegna FSE , L.R.7/2007 Promotion of the scientific research and technological innovation in Sardinia 25

87 XIV International Conference on Embedded Computer and Systems: Architectures, MOdeling and Simulation SAMOS XIV July 14 th - Samos Island (Greece) Carlo Sau DIEE Università degli Studi di Cagliari carlo.sau@diee.unica.it Automated Design Flow for Coarse-Grained Reconfigurable Platforms: an RVC-CAL Multi-Standard Decoder Use-Case