Design of efficient, virtual non-blocking optical switches

Transcription

1 Desig of efficiet, virtual o-blockig otical switches Larry F. Lid, Michael Sratt Mobile Systems ad Services Laboratory HP Laboratories Bristol HPL March 3 th, 2002* otical switchig, switch desig Large otical switches are made by coectig smaller switch arrays together, usually as three stage etworks. This letter shows how three stage efficiecy ca be further imroved, by allowig a egligible amout of blockig to exist. A simle desig algorithm is also develoed, which removes the eed for log simulatios. * Iteral Accessio Date Oly Aroved for Exteral Publicatio Uiversity of Esse, Esse, Germay Coyright Hewlett-Packard Comay 2002

2 Desig of efficiet, virtual o-blockig otical switches L F Lid ad M P Sratt Idexig terms: Otical switchig, Switch desig Abstract: Large otical switches are made by coectig smaller switch arrays together, usually as three stage etworks. T his letter shows how three stage efficiecy ca be further imroved, by allowig a egligible amout of blockig to exist. A simle desig algorithm is also develoed, which removes the eed for log simulatios. Itroductio: There is widesread iterest these days i a all-otical core etwork layer for high seed data trasmissio. Such a layer could rovide a world-wide backboe for a all-ip etwork, or for SDH ad SONET based etworkig. This would eable high seed commuicatio, oeratig i the 0s of Terrahertz rage []. A major comoet i this etwork is the otical cross-coect switch. Efficiet three stage (Clos) switches ca be desiged [2] which are comletely o-blockig. However, extra savigs i terms of the umber of switch elemets ca be achieved by a iteral routig algorithm which, although ot comletely o-blockig, will exeriece blockig so ifreuetly that the effect ca be igored (virtual o-blockig). A 3 stage switch has the toology of Fig. The oututs of the to iut array are each coected to a searate stage 2 array, etc. For this desig to be strictly o-blockig, the Clos coditio 2- [2] must be satisfied, where ad are defied i Fig.. However, by allowig a extremely small amout of blockig, the umber of stage 2 switches ca be reduced, imrovig efficiecy ad reducig etwork cost. A major outcome was the develomet of a mathematical model, which removed the ecessity for extremely log simulatio rus at etwork deloymet. Simulatio: A test case was ru, with = 6, = 6. Radom traffic was itroduced o a radom basis, usig a discretised trucated Poisso model. The hold time for a call was chose from a trucated gaussia distributio, such that the switch was loaded to about 95% caacity. A ew call was always routed through the available stage 2 array earest the to of the stage 2 stack of arrays (referred to as switch ackig). 2

3 The simulatio was moitored with varyig values of (with = 3 ecessary for Clos oblockig). Startig with = 22, the blockig robability Pb() was calculated, allowig for about 50 blockig evets to occur. The was icreased (otig each P b ) util P b () < 0-5. Theory: Whe P b () < 0-5, the simulatio ru time will be very log, ad so a theory was develoed for these cases of iterest. Whe Pb() 0-5 or lower, it was foud that whe a switch ackig blockage occurred, the bottom stage 2 array had oly oe coectio ath through it. This is because the ackig strategy tries to use the to stage 2 array first for a ew call, the the ext array dow, ad so o. If the umber of stage 2 arrays is icreased by oe, a blockage will still imly that the bottom array has oly oe o-zero etry. So the blockig robability P b (i+) of i+ stage 2 arrays ca be related to the blockig robability P b (i) by a recurrece relatio: Pb(i+) = Pb(i)[P(c)P(f )] () where P b (i) is the switch blockig robability of i stage 2 arrays, P(c) is the blockig robability of the bottom stage 2 array that already has oe call i rogress, ad P(f ) is the coditioal robability that the bottom stage 2 array will have oe call i rogress. P(c) ca be foud by a combiatorial calculatio, ad P(f ) by a iteratio of (). For examle, the simulatio foud P b (23) =.9e-4 ad P b (24) = 4.0e-6. Also, a calculatio gave P(c) = 0.2. The () gives P(f ) = With P(c) ad P(f ) established, reeated use of () redicts the results show i Table. These values would be difficult to fid by simulatio, because of the very log ru times ivolved. A six day simulatio for v = 25 was ru as a check. It gave P b (25) = 8.72e-8, which is close to the iterative result. Table shows that virtual o-blockig ca be achieved with 25 stage 2 arrays, whereas 3 arrays would be eeded to satisfy the Clos coditio. Assumig a rate of call coectio er day, there would be about 3,000 years betwee blocked calls. For this slight blockage, the desig has reduced the umber of stage 2 arrays by 9%. Coclusio: The desig cosists of two arts. First, simulatio rus are erformed for a varyig umber of stage 2 arrays, util the blockig robability reduces to say 0-5. With moder PCs, this art ca be erformed i a few miutes. It has bee observed that whe this level of blockig exists, the bottom stage 2 array is lightly loaded, ad ormally is hadlig just oe call. The ext art uses a 3

4 simle iterative euatio to redict blockig robability, usig arameters gaied from the simulatio ad combiatorial calculatio. The iterative results show a regio of virtual o-blockig for the switch, which uses fewer arrays tha the classic Clos result. The etwork desiger ca the choose the miimum switch size that will satisfy a realistic blockig robability secificatio. Refereces. Dettmer, R. 'Photos ad etabits', IEE Review, July 2000, Clos, C., 'A study of o-blockig switchig etworks', Bell System Techical Joural, March 953, L F Lid (Deartmet of Electroic Systems Egieerig, Uiversity of Essex, Wivehoe Park, Colchester CO4 3SQ) M P Sratt (Hewlett-Packard Laboratories, Filto Road, Stoke Gifford, Bristol BS34 8QZ) 4

5 stage stage 2 stage 3 Fig.. The structure of a efficiet three stage Clos switch v = Pb(v) = 8.4e-8.8e-9 3.8e- Table. Blockig robabilities for the examle, as the umber of secod stage arrays is icreased. 5