UNIVERSITY OF MORATUWA

Transcription

1 UNIVERSITY OF MORATUWA FACULTY OF ENGINEERING DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING B.Sc. Egieerig 2014 Itake Semester 2 Examiatio CS2052 COMPUTER ARCHITECTURE Time allowed: 2 Hours Jauary 2016 ADDITIONAL MATERIAL: Noe INSTRUCTIONS TO CANDIDATES: 1. This paper cosists of 4 questios i 5 pages. 2. Aswer ALL questios. 3. Applicable Assembly istructios are give as Aex. 4. Start aswerig each of the mai questios o a ew page. 5. For MCQ ad True/False questios, select the most appropriate aswer, ad write the correspodig sub-questio umber ad the aswer umber i your aswer book. 6. The maximum attaiable mark for each questio is give i brackets. 7. This examiatio accouts for 60% of the module assessmet. 8. This is a closed book examiatio. NB: It is a offece to be i possessio of uauthorised material durig the examiatio. 9. Oly calculators approved by the Faculty of Egieerig are permitted. 10. Assume reasoable values for ay data ot give i or with the examiatio paper. Clearly state such assumptios made o the script. 11. I case of ay doubt as to the iterpretatio of the wordig of a questio, make suitable assumptios ad clearly state them o the script. 12. This paper should be aswered oly i Eglish.

2 Immediate value Register Eable Istructio Bus Load select Abb/Sub select Register check for jump Overflow Questio 1 Figure 1 shows the block diagram of a simple microprocessor (a.k.a. ao-processor). Aswer followig questios based o Figure 1. Register Bak Register 23 Register Data Bus Register 2 Register 1 Clock Register 0 k-to-32 Decoder 32-way 16-bit Mux 32-way 16-bit Mux k Mux 5Register select 5 16-bit Add/Sub Uit Istructio Decoder Jump Flag Address to jump +1 Program ROM ROM 49 ROM 48 m -bit Adder ROM 3 2-way -bit Mux ROM 1 ROM 0 Memory select Reset Program Couter Figure 1 High-level diagram of the microprocessor. This microprocessor desig is based o the Vo Neuma architecture. [1 mark] True False What is the size of the Program Couter (i.e., umber of bits i Figure 1)? [2 marks] a) 4.52 bits b) 5 bits c) 5.61 bits d) 6 bits Page 2 of 5

3 How may bits are required to select a register from the Register Bak (i.e., umber of bits k i Figure 1)? [2 marks] a) 4.52 bits b) 5 bits c) 5.61 bits d) 6 bits Oe of the istructios supported by the microprocessor ca be defied as follows: Istructio SUB R1, R2 Descriptio Subtract registers R 1 ad R 2 ad store results o R 1, i.e., R 1 R 1 R 2. R 1, R 2 [0, 31] m-bit istructio k-bits to idicate Register R 1 k-bits to idicate Register R 2 x x x (iv) What is the word legth of a istructio? [2 marks] (v) a) 10 bits b) 14 bits c) 16 bits d) 18 bits If the Program ROM ca store 50 such istructios, what is the total capacity of the Program ROM i bytes? [2 marks] a) 100 bytes b) 113 bytes c) 800 byes d) 900 bytes (vi) Above 16-bit Add/Subtract uit caot be built usig: [2 marks] a) 16 Full Adders b) Four 4-bit RCAs c) 15 Full Adders ad 1 Half Adder d) 32 Half Adders (vii) Write the machie code for the followig istructio. [3 marks] (viii) SUB 0x12, 0x07 Briefly explai how the above istructio ca be implemeted o the microprocessor. Clearly idetify what compoets to activate ad how to activate them. [7 marks] (ix) Briefly discuss to whether we ca exted the proposed microprocessor to have a 2- stage pipelie with istructio fetch ad istructio execute stages. [4 marks] Questio 2 Show the schematic diagram of a 1-to-8 demultiplexer built usig two 1-to-4 demultiplexers ad other basic logic compoets. [3 marks] A 3-bit couter has the followig state trasitios: Show the schematic diagram of this couter built usig T Flip Flops. Your aswer should iclude the truth table, Karaugh Maps, ad schematic diagram. [11 marks] Usig the 2 s Complemet calculate Note that registers are 8-bit. [3 marks] (iv) Represet usig Sigle Precisio, IEEE Floatig Poit stadard. [4 marks] Page 3 of 5

4 (v) Hit: Sigle Precisio stadard has a 23-bit matissa, 8-bit expoet, ad 1-bit sig. The expoet is calculated as E = e For a give applicatio, 40% of the istructios require memory access. Istructio miss rate is 2% ad data miss rate is 4%. A istructio ca be executed i 1 clock cycle. L1 cache access time is approximately 5 clock cycles while the L1 miss pealty is 64 clock cycles. 1. What is the average memory access time for istructios? [2 marks] a) 1.28 clock cycles b) 5 clock cycles c) 6.28 clock cycles d) 64 clock cycles 2. What is the average memory access time for data? [2 marks] a) clock cycles b) 2 clock cycles c) clock cycles d) 5 clock cycles Questio 3 Give two itegers x ad y, write a Assembly program to idetify the miimum value, i.e., mi(x, y). For example, if x = 3 ad y = 7 a desigated register should cotai 3. Provide commets for your code. [13 marks] Assume microprocessor has 20, 8-bit geeral purpose registers labelled as R1, R2, R20. x, y [1, 127]. It is ok to assume x ad y are already stored i two of the geeral purpose registers. Use oly the istructio set give as Aex. Briefly discuss which I/O techique amog Poolig, Iterrupt Drive, or Direct Memory Access (DMA) is most suitable for the followig applicatios. [4 x 2 marks] 1. Whe you order food at a fast food restaurat you are give a umber. Orders are processed o the First Come First Serve (i.e., FIFO) basis. The oce your order is ready, your order umber is to be displayed usig a couter that uses three 7-segemet displays. Whe your umber is displayed you go ad pick up the food. You are required to desig a simple embedded system to cotrol this couter, which typically eeds a icremet butto ad a reset butto. 2. A Time ad Attedace (T&A) system to be developed to record the arrival ad leavig time of employees. Whe a employee arrives, he/she eters the 4-digit employee ID (via a key pad) ad press the arrive butto. Whe he/she leaves, agai the 4-digit ID is etered followed by the leave butto. Rest of the time the T&A system is expected to update relevat database records such as whether a employee is preset o a give day, how may hours he/she worked, umber of leaves take, ad calculate overtime. How would you improve the followig program to beefit from spatial ad/or temporal locality i cachig? Discuss while presetig a optimized program. A ad b are two matrices. Memory layout is row major. for (i= 0; i < ; i++) for (j = 0; j < ; j++) a[j][i] = b[j][i] + 2 [4 marks] Page 4 of 5

5 Questio 4 Suppose, just after graduatio you were hired by Itel Ic. Your team is resposible for desigig the 6 th geeratio of Itel Core processors. Itel is hopig that the chips will kill off the tablet tred ad persuade cosumers to ivest i hybrid or all-i-oe Widows-based devices istead. 6 th geeratio of Itel Core processors are expected to be capable of startig up i 0.5 secods ad have 2.5 times the performace of previous geeratios. It is also possible that devices ruig o the chip will offer users up to 3x more battery life tha what they are curretly used to. Part of the write up is extracted from Briefly explai what type of a desig you would recommed for each of the followig items. Provide at least 2 justificatios for each of your selectios. 1. Number of processig elemets (e.g., sigle core or multi core). [3 marks] 2. No of pipelie stages. [3 marks] 3. Memory hierarchy (e.g., umber of levels, cache size, ad cache associativity). [4 marks] 4. What is the expected performace-to-power gai? [2 marks] Based o performace tests it has bee idetified that the memory sub-system o the 5 th geeratio Itel Core processors is a major performace bottleeck. This is due to memory system ot beig able to provide the required badwidth whe each CPU core is ruig at its full speed. Waitig time for memory was 65% of the total time. Therefore, oe of your team members suggested that by further icreasig the memory badwidth, it would be possible to gai the desired overall speedup of How much speed up i the memory sub-system will be required to achieve the desired overall speed up? [ 3 marks] You may use the Amdahl s law give below for the calculatio: Speedup Overall = (1 Fractio Ehaced 1 Fractio ) + Speedup Ehaced Ehaced 2. Do you agree with your team member s idea of gaiig such a speedup by improvig oly the badwidth of the memory sub-system? Explai. [3 marks] 6 th geeratio processor will be desiged for Solid State Disk (SSD) based systems. Will this improve the overall performace ad eergy efficiecy? Discuss. [4 marks] (iv) 6 th geeratio processor to have eve more I/O pis supportig more Parallel Coectios amog compoets o a motherboard such as RAM, video card, ad etwork card. This will further speed up the system. Do you agree or disagree with this suggestio? Briefly discuss. [3 marks] END OF THE PAPER Page 5 of 5