STM32F446-ARM Nucleo Board User's Manual D.K. Blandford August, 2017

Transcription

1 STM32F446-ARM Nucleo Board User's Manual D.K. Blandford August, 2017 Updated November 3, 2017

2 Table of Contents Contents Section 1 Introduction, features and preliminaries... 1 Features... 1 Section 2 Keil Development System... 4 Keil µvision 5 Setup... 4 Section 3 Quirks, clocks, and details Naming Conventions Architectural Features and Quirks System Clock Barrel Shifter Phase Locked Loop Flash Memory access On-Chip Interconnect via a Crossbar Switch Processor Block Diagram Section 4 Programming Details Assembly Language Programmer's Model Memory Mapping Memory map details Pin Assignments GPIO Pins Addressing ports Include files Assembly code C-Code traditional style C-Code CMSIS style Easy Guide to Assembly Code Instructions Assembler Directives Addressing modes Programming in Assembly Code Writing an Assembler function in a C-Code program Writing stand-alone assembly code Programming in C Section 5 Programming Examples Assembly Language Examples Example 1 Writing bits Example 2 Loops Example 3 Logic... 43

3 Example 4 GPIO Example 5 D to A conversion C-Code Examples Example 1 GPIO Example 2 A to D and D to A Conversion Example 3 Polled timer Example 4 Timer interrupt Example 5 Real Time Clock Example 6 Pulse Width Modulation Example 7 UART Example 8 Clock frequency... 56

4 Section 1 Introduction, features and preliminaries Features The ARM Nucleo board is shown in Figure 1.1. The board has the following features: STM32F446RET6 microcontroller with the following features: LWFP64 package Floating point unit with frequencies up to 180 MHz. 512 kb of Flash memory plus 128 KB of SRAM Dual mode Quad SPI interface 1.7 V to 3.6 V application supply and I/Os 4-to-26 MHz crystal oscillator Internal 16 MHz factory-trimmed RC (1% accuracy) Internal 32 khz RC with calibration Three 12-bit, 2.4 MSPS ADC: 16 channels Two 12-bit D/A converters General-purpose DMA 14 timers SWD & JTAG interfaces Board power supply: through USB bus or from an external 5V supply voltage External application power supply: 3V and 5V ST MEMS motion sensor, 3-axis digital output accelerometer ST MEMS audio sensor Audio DAC with integrated class D speaker driver Eight LEDs (4 for user) Two pushbuttons (user and reset) USB micro-ab connector for connection to a mouse or other USB peripheral. USB mini-b connector for programming directly from the Keil µvison 5 development system. 50 GPIO ports with interrupt capability (most are 5 V tolerant) Four I 2 C interfaces Four USARTs and two UARTs Four SPIs Two SAI (serial audio interface) Two CAN (2.0B Active) SDIO interface Consumer electronics control (CEC) I/F Advanced connectivity 8- to 14-bit parallel camera interface up at 54 Mbytes/s The STM32F446RE is an ARM Cortex M4 processor. The M4 is identical to the M3 but it has an additional DSP engine added on. The ARM Cortex M3 and M4 processors are RISC machines with a 3 stage pipe (Fetch, Decode, and Execute) see Figure 1.2. The M3 and M4 processors execute the Thumb2 instruction set which consists of 50, 16-bit instructions and 6, 32-bit instructions. -1-

5 Figure 1.1 The ARM Nucleo board. The USB port at the top of the board (mini-b) is the programming port.[3] -2-

6 Figure 1.2 The ARM Cortex M3, M4 pipeline. [4] -3-

7 Section 2 Keil Development System Keil µvision 5 Setup The free version of the Keil Development system for the ARM board is available from Under Software Downloads click on Product Downloads MDK-ARM v5 and fill out the registration form. Keil will download the compiler and send you a license file via . Open the development system and select File New project. Create a new folder for your project and give your project a name. In Figure 2.1 the project is named STMF446Template and is in a new folder by the same name. Click on Save. Figure 2.1 Create a New Project screen. Once the project is saved you will get a screen requiring you to choose a target. Locate STMicroelectronics and find STM32F446RETx as shown in Figure 2.2. Click on OK. You will be asked to select the run-time environment as shown in Figure 2.3. There is a pull-down menu at the top center of the screen. Pull this down and click on NUCLEO-F446RET. You will also need to click on CMSIS Core and click the checkbox and on Device Startup and click that checkbox as shown in Figure

8 Figure 2.2 Select STM32F446RETx for the target device. Figure 2.3 Selecting the run-time environment. Click on the pull-down menu and select NUCLEO-F446RE. Click on CMSIS Core and click the checkbox and on Device Startup and click that checkbox. Then click OK. This completes the setup of an empty project. The next step adds the necessary files to the project. You will need to add two files to your project. A) You main c-code file B) A supporting dot-h file named stm32f446.h. -5-

9 To add your main c-code, in Keil, click on File New. This will create a file in Keil on a tab named Text1. Click on File Save as and save this file as STMF446Template.c. You can name it whatever you want but you need to use a dot c extension. The file stm32f446.h is available on the class website. Download it and place it in the project folder. The files we need are in the project directory but they have not been added to the project. To do this right click on Source Group 1 (under Target) and select Add Existing Files to Source Group 1 (See Figure 2.4) Select the c-code file and click on Add. It's not necessary to add the dot-h file the c-code which uses it will find it in the directory (you can add it if you want). If you have done this successfully you can expand the source group in the project window and see the files that are in the project. This should look like that shown in Figure 2.5. Figure 2.4 Add files to source group 1 Figure 2.5 The project column with the files added to the project. Note that the DSP libraries are not needed for EE

10 At this point we are ready to enter the c-code for the project. Click on the tab for your c-code. In this example the tab is titled stmf446template.c. Enter the following program. #include "stm32f446.h" /*stm446template.c July 1, 2017 This program toggles a bit on PA7 as fast as possible */ int main() {int tmp; //Clock bits RCC_AHB1ENR = 1; //Bit 0 is GPIOA clock enable bit //I/O bits GPIOA_MODER = 0x4000; //Bits = 01 for digital output on PA7 //OTYPER register resets to 0 so it is push/pull by default GPIOA_OSPEEDER = 0xC000; //Bits = 11 for high speed on PA7 //PUPDR defaults to no pull up no pull down //Main program loop tmp = 0; while(1) {GPIOA_ODR = tmp; tmp = ~tmp; //Only PA7 is set up for output so other bits // have no effect. After entering the c-code click on Project Build Target to save and compile your code. If you have been living a virtuous life your code will compile with no errors and no warnings. (You may get a warning about needing a blank line as the last line in the code. This means a blank line with no spaces. You can add it or just ignore the warning.) You are now ready to load the project code onto the Nucleo board or to do a simulation. The simulation is a software simulation and no board is needed. It has some limitations in that all of the peripherals are not simulated but you can at least see what is in the registers and the memory including the I/O ports. Debugging on the board includes loading and running the code on the Nucleo board via a USB cable. It is often easier to track down a hardware problem by running the code on the board itself. The set up loading the project on the Nucleo board is rather involved but you only need to do it once. We will do the simulation set up first it is easy. Using the Simulator The simulator is all software based so it needs to know in advance what memory you are using. This is done by creating an initialization file which typically has a.ini extension but is otherwise a simple text file. After you have compiled your program successfully, click on file new. The μvision environment will open a new file for you. Enter a mapping function given by MAP 0x , 0x READ WRITE Save the file with the name Debug.ini. See Figure

11 Figure 2.6 The Debug.ini file. This allows the simulator to read and write to simulated memory at 0x to 0x which covers most of the memory area where the processor maps its I/O ports. After creating Debug.ini and saving it, right click on Target1 in the project window and select Options for Target 1. In the screen that appears select the Debug tab as shown in Figure 2.7. Figure 2.7 Right click on Target 1 in the Project window and select Options for Target 1. Select the Debug tab to get this screen. Click on the "Use Simulator" radio button and browse to the debug.ini file for the Initialization File. In Figure 2.7 select "Use Simulator" and on the left side panel click on the box with three dots ( ) in the Initialization file. This will allow you to browse out to locate the Debug.ini file you created earlier. When you select Debug.ini the Initialization file window will look like that shown in Figure 2.7. Click on OK and we are ready to do our simulation. Click on Debug Start/Stop Debug Session or click on the red button at the top of the screen: -8-

12 When you start the debugger you will get a message saying that you are in the "Evaluation mode" with a code size limit of 32K. If you are using the professional version of μvision 5 this message will not appear. For this class the student version is adequate for all assignments. Figure 2.8 shows the debugger screen for this project. Figure 2.8 The initial debugger screen. If your debugger screen does not have all of these components you can use the view menu to get them. The program that we are debugging uses port A for output. This is called GPIOA (General Purpose I/O port A). Click on Peripherals System Viewer GPIOA to show the registers in GPIO port A. See Figure 2.9 Figure 2.9 The registers in GPIOA as seen in the debugger. Click on the + sign to expand the register to see the bits. -9-

13 Figure 2.10 Menu buttons for controlling the debugger. These are located on the Debug Toolbar at the top of the screen. If these are not present on your screen you can find them on the view menu. To run the program and do the simulation click on the Run button on the Debug Toolbar. (See Figure 2.10). For this program you will see the Output Data Register (ODR) on GPIOA change from FFFFFFFF to since the program writes all ones and all zeros to the port continuously. Notice also that at the bottom of the Register window the number of simulated seconds is also changing. (This time will not be accurately simulated unless you have correctly set the crystal speed before you entered the debugger. To do this right click on Target 1 in the Project windows and select Options for Target 1. Choose the Target tab and set the crystal speed to match that on your board.) You can stop the program at any point by pushing the stop button on the Debug Toolbar. You can also single step through your program using the Step into button. You can stop debugging and go back to the main program screen by clicking on Debug Start/Stop Debugging. If while debugging you find an error it is tempting to change the code in the debugger to fix the problem. Such changes will not be effective. If you make any changes to the code they will not go into effect until you have again recompiled the program. Loading the project on the Nucleo Board 1. You will need a USB cable that has a Type A/mini-B connector for the board and a standard USB connector to plug into your computer. This is the same cable that you use to charge your phone. This USB cable plugs into CN1 on the Nucleo board. If your computer does not locate the driver you will have to locate the driver and install it. The driver is at c:\keil\arm\stlink\usbdriver if you need it. If after installing the USB driver you may also need the upgrade utility which is at c:\keil\arm\stlink. 2. With your board plugged in we will need to change the project options to use STLink. Click once on Target in the project pane and then click on Project Options for Target 1 or click or Alt F7. Under the Target tab set the crystal speed to 8.0 MHz 3. Under the Debug tab click on the pull down menu on the right and choose STLink Debugger. Also click on the radio button labeled Use so that the Use Simulator button is not chosen. See Figure

14 Figure 2.11 The Debug options. 4. After you have selected the STLink Debugger click on the Settings button next to it. The setting should look like that shown in Figure If not, be sure your board is plugged in and that you have the Debug options set up as shown in Figure Figure 2.12 The Debug settings options. You will have to change the port setting to SW. 8. Click on OK for the target options and get back to the window with the c-code in it. At this point you are ready to upload your code to the board and run your program. To do this click on the Debug button or, click on Debug Start/Stop Debug Session. The program -11-

15 will be downloaded to your board. Click on Debug Run to start the program running. With an oscilloscope you will see a square wave at about 1.33 MHz. You can alter the code by adding an empty delay loop like this: int main() {int i, tmp; //Clock bits RCC_AHB1ENR = 1; //Bit 0 is GPIOA clock enable bit //I/O bits GPIOA_MODER = 0x4000; //Bits = 01 for digital output on PA7 //OTYPER register resets to 0 so it is push/pull by default GPIOA_OSPEEDER = 0xC000; //Bits = 11 for high speed on PA7 //PUPDR defaults to no pull up no pull down //Main program loop tmp = 0; while(1) {GPIOA_ODR = tmp; tmp = ~tmp; for(i=0;i<10000;i++); //Empty for loop for time delay In this case the square wave on PA7 runs at about 160 Hz. //Only PA7 is set up for output so other bits // have no effect. For future projects, in order not to have to run through the tedious STLink set up, you can create a new project folder on your computer and download STM446Template.zip to that folder. Unzip the project and delete the main c-file (named STM446Template.c). Open the project by double clicking on STM446Template.uvproj, add you own c-code to the file, and run it as usual. -12-

16 Section 3 Quirks, clocks, and details Naming Conventions STMicroelectronics uses the naming convention shown in Figure 3.1 for microcontrollers in this series. Figure 3.1 Part naming conventions[5] Architectural Features and Quirks In order to get a microcontroller to run at 180 MHz using relatively slow flash memory it is necessary to have some architectural creativity. For the STM32 M3 and M4 processors this includes a phase locked loop, an Adaptive Real-Time (ART) memory accelerator, and a Multi- Advanced High-speed Bus (AHB) switching Matrix. All of these things run from a rather complex system clock. The following discussion gives an overview of how this works. -13-

17 System Clock The STM32 has four clock lines from three sources which can be used to provide the system clock. The sources are: the High-Speed External (HSE) oscillator, the High-Speed Internal (HIS) Oscillator, or the Phase Locked Loop clock (PLL). The HSE clock is driven by an external oscillator. This allows several processors to run from a single external clock. The HSI clock is driven by a 16 MHz internal RC oscillator. Its frequency is approximate but may be calibrated by the user. The PLL can by driven by an external crystal or by the HSI clock. An external 8 MHz crystal can be used by the PLL to provide a 180 MHz internal system clock. In addition to driving the system clock the PLL also provides a second output at 48 MHz to drive the USB and a third output to drive I2S1 and I2S2 clocks for serial communication. The HSE clock can be driven by an external crystal or from an external clock signal. On the Discovery board the HSE oscillator has an 8 MHz external crystal. The HSE clock can be used to drive the Phase-Locked Loop to get an internal clock to 168 MHz. The HSI clock is driven from an internal RC oscillator and runs at approximately 16 MHz. There is also a Low-Speed Internal (LSI) clock which runs from an internal RC oscillator at KHz. It is typically used to drive a watchdog timer that runs independently from the system clock. If the KHz from the RC oscillator is not precise enough for real-time application the LSE clock can be used with an external crystal. Figure 3.2 shows the clock logic diagram. Note that by default the Nucleo board uses the internal 16 MHz RC circuit for an oscillator. To run at the rated 180 MHz it is necessary to phase lock loop and clock control registers. Peripheral Clock The peripheral clock for the GPIO ports, the A/D and D/A converters, the timers, and the high speed busses are derived from the system clock by way of a pre-scaler which can be modified by the user. Several pre-scalers are used to configure the Advanced High-speed Bus (AHB) frequency, the Advanced Peripheral Busses: high-speed APB (APB2) and low-speed APB (APB1). The maximum frequency of the AHB is 180 MHz. The maximum allowed frequency of the highspeed APB2 is 90 MHz. The maximum allowed frequency of the low-speed APB1 is 45 MHz. When the processor resets the system clock is set to the 16 MHz internal RC oscillator and the bus pre-scalers are all set to "no scaling" so that APB2, APB1, and AHB all run at 16 MHz. Barrel Shifter A barrel shifter is a combinational logic block which uses multiplexors to shift bit positions as data is copied from one location to another. For a normal shift register it takes n clock cycles to shift n places left or right. The barrel shifter on the Cortex-M4 makes it possible to do up to a 32-bit shift left or right in a single clock cycle. -14-

18 Figure 3.2 Clock generation for the STM32 processor[1]. -15-

19 Phase Locked Loop Internally the STM version of the ARM Cortex M4 processor runs at 180 MHz which is a cycle time of just nsec. This would imply that a very fast external interface bus would be needed to communicate with the outside world. For many embedded controller systems this high speed interface is unnecessary. The solution to this problem is to add a phase locked loop into the hardware which allows the CPU to run at 180 MHz and to simultaneously communicate with a synchronized 8 MHz system on the outside. Thus, the STM32F446 requires only an 8 MHz crystal and from the outside, the user sees it as an 8 MHz system although inside it is actually executing instructions at 180 MHz. A system diagram for a phase locked loop (PLL) is shown below. An 8 MHz crystal oscillator runs the external system busses and clocks. Internally a voltage controlled oscillator runs at about 180 MHz. Figure 3.3 shows how this is done. The 8 MHz oscillator is first divided by 8 to get a stable 1 MHz clock. The 1 MHz clock from the crystal is compared to the 1 MHz signal from the divided voltage controlled oscillator. The error signal is fed back to adjust the frequency of the VCO. Effectively, the PLL acts as a frequency multiplier. Figure 3.3 System diagram for a phase locked loop. Flash Memory access Flash memory has a read access time of a few tens of nano-seconds per byte after the first byte. For a processor running with a clock period of about 6 nano-seconds this is much too slow. An obvious solution is to add an SRAM cache memory to the chip. This means that the instructions in the flash memory would be loaded into the cache before being delivered to the processor. Since the data is present on the chip is in two places and the cache requires some considerable hardware overhead for its operation this is inefficient. Instead of adding a cache, the STM32 organizes the flash memory into 128-bit words. Each access produces a single 128-bit word which can consist of eight 16-bit Thumb instructions. Organizing the flash memory into 128-bit words effectively speeds up the access time by a factor of 8 for Thumb instruction access. However, is a conditional branch is taken, the next instruction in the 128-bit word may not be the one that is needed. To address this problem the STM32 has an Advanced Real-Time (ART) accelerator module which can store sixty-four 128 bit sequences. Each time a branch occurs the instructions at the target location are saved in the -16-

20 ART so that the next time the branch is taken the instructions are saved and ready for execution. Figure 3.4 shows schematically how this is done. Figure 3.4 Advanced Real-Time (ART) Accelerator to speed up effective flash memory access time[6]. On-Chip Interconnect via a Crossbar Switch The STM32 M3 and M4 processors have a number of items which connect to the processor and must share data and address busses. If this is done on a single bus there would be some interference and wait times for various devices. The STM 32 M3 and M4 processors instead us an on-board crossbar switch which is shown schematically in Figure 3.5. This allows, for example, the processor to be running out of flash memory at the same time that a DMA channel is transferring data to SRAM. Figure 3.5 The onboard crossbar switch[1]. -17-

21 Processor Block Diagram A block diagram of the STM32F446RET6 processor is shown in Figure 3.6. For the Nucleo board the STM32F446RET6 has 512 KB of flash memory and 128 K of RAM. Figure 3.6 Block diagram of STM32F446RET6 processor.[5] -18-

22 Section 4 Programming Details Assembly Language Programmer's Model Figure 4.1 shows the internal registers accessible to the assembly language programmer. The top three registers have special functions: R13 is the stack pointer; R14 is the link register; R15 is the program counter. Figure 4.1 Assembly language programmer's model[7]. The normal 32-bit ARM instruction can access all of the registers. The Thumb and most of the Thumb2 instructions are only 16-bit instructions and have access only to R0-R7 as general purpose registers. For the Thumb instructions only the MOV instruction has access to all of the general purpose registers. The link register R14 is a special one-level stack. When a subprogram call is made from a main program the return address goes into R14. If the subprogram makes further calls the return address goes onto the stack in memory. The assembly language instruction BLX (Branch and Link) automatically uses this register. Register R13 is the stack pointer. The lower two bits of this register is always zero since it accesses the stack on 32-bit word boundaries. Normal operations always use SP_main but for thread mode the processor can be configured to use SP_process. Register R15 is the program counter. It is 32-bits long and there is a linear address space from 0 to Bit 0 of this register is always 0 so that instructions are aligned on 16-bit boundaries. -19-

23 The CPU flags are stored in the program status register. There are three program status registers called Application Program Status Register (APSR), Interrupt Program Status Register (IPSR), and the Execution Program Status Register (EPSR). These three status registers have mutually exclusive bit fields and can be combined and read as a single register called the Program Status Register (PSR). Figure 4.2 shows these registers. Figure 4.2 The three program status registers can be read a single register called PSR with bit fields as shown 2. Bits 27 to 31 are the condition codes or CPU flags. The definition for these is shown in Figure 4.3. Figure 4.3 Definition of the condition code bits[2]. In addition to the normal CPU flags in Figure 4.3, the Program Status Register has three other fields with status information. These are the Greater than or Equal (GE) field, the Interrupt Continuable/If Then (ICI/IT) field, and the Interrupt Service Routine (ISR) number. The GE field holds information that can be used by the SEL and SIMD assembly language instruction for -20-

24 certain conditions. See [8] pp The ICI/IT field holds information for conditional execution (if-then) assembly language instructions. The ISR number field holds the exception number currently being executed. Memory Mapping The ARM has a 32-bit address and in hex addresses range from to FFFF FFFF. This is a linear address space and there are no I/O instructions since all ports are mapped from memory. Figure 4.3 gives an overview of the memory mapping. Refer to the User's manual for the address of specific peripheral registers. Memory map details All of the I/O ports are mapped into the 4 GByte memory space. From Figure 4.3 we see that the peripherals are mapped to the address range 0x to 0x5FFF FFFF. Table 1 gives the addresses of the most common registers for the I/O devices. This list is incomplete. See Table 1 in the STM32 Reference Manual [1] for a more complete list of register boundary addresses and links to specific register addresses. Addresses for the interrupt system are not in the Reference Manual. You can find these in the Programmer's Manual [2]. -21-

25 Note: AHB Advanced High-performance Bus, APB Advanced Peripheral Bus, FSMC Flexible Static Memory Controller, Figure 4.3 Memory map for the ARM M4 processor.[5] -22-

26 Table 1 An abbreviated list of memory addresses for many I/O ports. //D to A Addresses //Clock addresses //Timer 6 addresses DAC_CR 0x RCC_CR 0x TIM6_CR1 0x DAC_SWTRIGR 0x RCC_PLLCFGR 0x TIM6_CR2 0x DAC_DHR12R1 0x RCC_CFGR 0x TIM6_SR 0x DAC_DOR1 0x C RCC_CIR 0x C TIM6_DIER 0x C //GPIO Port A Addresses RCC_APB1ENR 0x TIM6_CNT 0x GPIOA_MODER 0x RCC_AHB1ENR 0x TIM6_PSC 0x GPIOA_PUPDR 0x C RCC_APB2ENR 0x TIM6_ARR 0x C GPIOA_OSPEEDER 0x TIM6_EGR 0x GPIOA_OTYPER 0x //Flash Memory //Interrupt controller GPIOA_IDR 0x FLASH_ACR 0x40023C00 NVICISER0 0xE000E100 GPIOA_ODR 0x NVICISER1 0xE000E104 GPIOA_BSRR 0x //A to D Addresses NVICICER0 0xE000E180 GPIOA_AFRL 0x ADC_SR 0x NVICICER1 0xE000E184 GPIOA_AFRH 0x ADC_CR1 0x //USART1 Registers //GPIO Port B Addresses ADC_CR2 0x USART1_SR 0x GPIOB_MODER 0x ADC_SQR1 0x C USART1_DR 0x GPIOB_PUPDR 0x C ADC_SQR2 0x USART1_BRR 0x GPIOB_OSPEEDER 0x ADC_SQR3 0x USART1_CR1 0x C GPIOB_OTYPER 0x ADC_DR 0x C USART1_CR2 0x GPIOB_IDR 0x ADC_CCR 0x USART1_CR3 0x GPIOB_ODR 0x //Timer 2 addresses USART1_GTPR 0x GPIOB_BSRR 0x TIM2_CR1 0x //USART4 Registers GPIOB_AFRL 0x TIM2_CR2 0x USART4_SR 0x40004C00 GPIOB_AFRH 0x TIM2_SR 0x USART4_DR 0x40004C04 //GPIO Port C Addresses TIM2_DIER 0x C USART4_BRR 0x40004C08 GPIOC_MODER 0x TIM2_EGR 0x USART4_CR1 0x40004C0C GPIOC_PUPDR 0x C TIM2_CNT 0x USART4_CR2 0x40004C10 GPIOC_OSPEEDER 0x TIM2_PSC 0x USART4_CR3 0x40004C14 GPIOC_OTYPER 0x TIM2_ARR 0x C USART4_GTPR 0x40004C18 GPIOC_IDR 0x //Timer 3 addresses //USART6 Registers GPIOC_ODR 0x TIM3_CR1 0x USART6_SR 0x GPIOC_BSRR 0x TIM3_CR2 0x USART6_DR 0x GPIOC_AFRL 0x TIM3_SR 0x USART6_BRR 0x GPIOC_AFRH 0x TIM3_DIER 0x C USART6_CR1 0x C TIM3_EGR 0x USART6_CR2 0x TIM3_CNT 0x USART6_CR3 0x TIM3_PSC 0x USART6_GTPR 0x TIM3_ARR 0x C -23-

27 Pin Assignments The microcontroller on the Nucleo board is the STM32F446RET6 which comes in a 64 pin LQFP 64 (Low profile Quad Flat Pack) package. The pin assignments are shown in Figure 4.4. Figure 4.4. The STM32F446RET6 IC Package with assigned pins[5] The Nucleo board has two connectors each consisting of two columns of pins. Connector CN7 is on the left in Figure 1.1 and CN10 is on the right. CN7 and CN10 each have 38 pins in two 19- pin columns for a total of 76 pins so that all pins of the LQFP 64 package are brought out along with multiple power and ground lines. A few pins have no connection (NC). See Table 29 in the User's Manual for a complete mapping of all of the package pins to the board pins at CN7 and CN10. For the I/O ports, Table 2 gives the pins are available for the Nucleo Board: -24-

28 Table 2 Pins available on Nucleo Board Port Pins on Nucleo Board PA PA0 to PA15 PB PB0 to PB10 plus PB12 to PB15 PC PC0 to PC15 PD PD2 PE None PF None PG None PH PH0-PH1 PI None Notes: 1. PB11 is not brought out to a board pin. 2. PA13 and PA14 are shared with the debug circuitry and should be avoided if possible. 3. A User LED (green) is connected to PA5 and is on when the pin is high. 4. A User push-button is connected to PC13. GPIO Pins Each of the GPIO ports on the ARM Cortex M4 processor has ten 32-bit registers that are used to configure the port and get information in and out. Table 3 defines these registers. Table 3 GPIO Port control and information registers Reg name Function Comment GPIOx_MODER Mode register Input, output, alternate function 1, or analog GPIOx_OTYPER Type register Allows push/pull or open drain GPIOx_OSPEEDR Speed register Allows low, medium, fast or high speed GPIOx_PUPDR Pull up/pull down register Allows pull up, pull down, or no pull up or pull down GPIOx_IDR Input data register Stores data for reading from outside GPIOx_ODR Output data register Stores data for writing to outside GPIOx_BSRR Bit Set/Reset register Writing a 1 to a bit in this register allows the user to set or reset a bit in the ODR GPIOx_LCKR Lock register Allows the user to lock a pin so that its value cannot be changed. GPIOx_AFRH Alt function register high GPIOx_AFRL Alt function register low Note 1: alternate function include timers, UARTs, CAN, Ethernet, I2C, and SPI to be attached to a port pin. Figure 4.5 shows a schematic of the typical I/O pin circuity. -25-

29 Figure 4.5 Typical electrical diagram for a GPIO pin [1]. Notice that on the output control there is a P-MOS/N-MOS push pull circuit which can be turned on or off using the OTYPER register. There is also a pull up/pull down configuration on the I/O line at the pin. This is set up by the PUPDR register. The protection diodes allow all of the I/O pins to be 5 volt tolerant. The input has a Schmitt trigger which is bypassed for analog input. Each GPIO pin can source or sink up to 25 ma [5]. However, care must be taken so that the total current going into or out of the chip does not exceed 120 ma. Exceeding this value may result in overheating. Addressing ports Include files Assembly code The ARM processor is mostly a RISC machine with a load and store architecture. Since all of the ports are memory mapped, reading/writing to a port is the same as reading/writing to a memory location. For example the following assembly code reads GPIOA to a register: ;From Table 1 the address of GPIOA_ODR is 0x ldr r4, =0x ; address of Port A ldr r3, [r4]; Copy port to r3 To copy data to GPIOA we could use the following: ldr r4, =0x ; address of Port A str r3, [r4]; Store r3 in port A Notice that the load instruction has data flowing from right to left but the store instruction has data flowing from left to right. In both cases, the square brackets around r4 indicate that it holds a register indirect address. -26-

30 C-Code traditional style In traditional C-code we create an include file which allows us to define register names for the register memory addresses. Typical define statements in such an include file for the GPIOA input and output data registers might look like this: #define GPIOA_IDR (*((volatile unsigned long *) 0x )) //GPIO A Input Data reg #define GPIOA_ODR (*((volatile unsigned long *) 0x )) //GPIO A Output Data reg In the line for GPIOA_IDR the code (volatile unsigned long *) 0x Does a cast making the hexadecimal number 0x a pointer type. The * in front of this dereferences this pointer allowing us to get the data that address. In C-code we can write: GPIOA_ODR = 0x ; //Make bit 7 a 1 OR we could write: GPIOA_ODR = (1 << 7); //Also makes bit 7 a 1 The file stm32f446.h is an include file which has most of the registers for the ARM Cortex defined in this manner. This file is available in the template program for the Keil V5 programming environment on the course web site. C-Code CMSIS style The Cortex Microcontroller Software Interface System (CMSIS) is a standardized, vendor independent software interface for the Cortex M-series processors. In addition to a number of libraries to interface code to peripherals, it provides register definitions that allow access by way of c-code. These register definitions make use of the typedef structure and pointers and provides a uniform access path for the peripherals and registers on all of the ARM Cortex processors. In c-code the typedef statement allows the user to rename a variable type. For example I can enter: typdef int weight; //Rename int to weight weight w1, w2; //Declare w1 and w2 as ints You can extend this to arrays. For example typedef float height[50]; //Rename float as an array named height height men; //Create men[50] as floats The typedef declaration can also be used with the struct declaration. Consider this example: typedef struct //rename a struct as record {int age; float height; float weight; record; record john, mary; //john and mary are now structs The user has access to the variables in the struct by means of the dot operator. john.age = 22; -27-

31 If we look at the include files for the ARM processor using CMSIS we find definitions for structs that might look like the following: /*!< Peripheral memory map */ #define PERIPH_BASE ((uint32_t)0x ) #define APB1PERIPH_BASE PERIPH_BASE #define APB2PERIPH_BASE (PERIPH_BASE + 0x ) #define AHB1PERIPH_BASE (PERIPH_BASE + 0x ) #define AHB2PERIPH_BASE (PERIPH_BASE + 0x ) /*!< AHB1 peripherals */ #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000) #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400) #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800) #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00) #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000) #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400) #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800) #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00) #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000) From these declarations we see that, for example, the GPIOA_BASE address is at 0x and GPIOG_BASE is at 0x A typedef for a struct is defined to gain access to the port registers. typedef struct { IO uint32_t MODER; //Address offset: 0x00 IO uint32_t OTYPER; //Address offset: 0x04 IO uint32_t OSPEEDR; //Address offset: 0x08 IO uint32_t PUPDR; //Address offset: 0x0C IO uint32_t IDR; //Address offset: 0x10 IO uint32_t ODR; //Address offset: 0x14 IO uint32_t BSRR; //Address offset: 0x18 IO uint32_t LCKR; //Address offset: 0x1C IO uint32_t AFR[2]; //Address offset: 0x20-0x24 */ GPIO_TypeDef; Finally we can define the individual port pointers. #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) -28-

32 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE) We see that (GPIO_TypeDef *) is defining a pointer to struct. For example, after these declaration, GPIOA will be a pointer to GPIOA_BASE which is the base address of the registers associated with GPIOA. To access one of the registers, say the output data register, we can use the following: (*GPIOA).ODR = 0; In this notation the *GPIOA dereferences the pointer and dot operator allows access to a member or the struct. But this is a bit unwieldy so there is a replacement notation. GPIOA -> 0; This notation uses the arrow operator to access a struct member. To summarize the following three lines to the same thing set bit PA7 to 0 using different notation. The first uses a define statement that makes the address of the output data register on GPIO port A a dereferenced pointer. It uses #include "stm32f446.h" which is an include file from the course web site. The second and third use #include "stm32f446xx.h" which is an include file that comes from the vendor (STM) and is part of the installation of Keil µvision 5 when you use the Nucleo Board. For the second and third the GPIOA term is a pointer to a structure that defines the registers for the port with offsets from a base address. GPIOA_ODR &= ~(1 << 7); //PA7 to 0 GPIOA -> ODR &= ~(1 << 7); //PA7 to 0 (*GPIOA).ODR &= ~(1 << 7); //PA7 to 0 Easy Guide to Assembly Code In general, for the ARM processors you can add an s to an instruction and it will alter the flags. Using the same instruction without an s will not alter the flags. For the compiler/assembler that we have this is often not an option and you are forced to use one or the other. Note also that the assembler is not case sensitive so that R0 is the same as r0 and you can use whatever you want although you should be consistent for readability. This particular assembler is sensitive to spaces. All labels must begin in column 1 and no assembly mnemonic is allowed to begin in that column. Instructions Loading immediate data into a register: ldr R3, =0x000003FF; Loads the 32 bit hex number into R3 ldr R2, =41; Loads 41 base 10 into R2 Store a register into a memory: str R2, [R1]; Stores R2 into the memory whose address is in R1 Copy one register into another: -29-

33 movs R2, R3; Copies R3 into R2 movs R2, #0xFF; Copies 255 into R2. Immediate limited to 0 to 255 Add: adds R2, R3; adds R10, R11; Note: Flags are set only if registers are R0 to R7 adcs R2, R3; Add R2 + R3 and puts result in R2 (flags set) R10 = R10 + R11 but flags not set R2 = R2 + R3 + carry Note: Can be used only with registers are R0 to R7 Subtract: subs R1, R2; subs R1, R2, R3; R1 = R1 R2 R1 = R2 R3 Note: Can be used only with registers are R0 to R7 sbcs R1, R2; Note: Can be used only with registers are R0 to R7 R1 = R1 R2 and accounts for carry flag (borrow) Multiply and Divide muls R1, R2; R1 = R1*R2 The mul instruction is for signed multiplication. You can also do unsigned multiply with umul. sdiv R0, R1; R0 = R0/R1 The sdiv instruction is for signed division. There is also a udiv for unsigned division. Note: Can be used only with registers are R0 to R7 Compare: cmp R2, R10; cmp R1, #0x20; Note: for immediate operand value must be 0 to 255. Logical AND, OR, and Exclusive OR ands R1, R2; orrs R1, R2; eors R1, R2; Subtracts R10 from R2, discards result and sets flags Subtracts 0x20 from R1, discards result and set flags R1 = R1 AND R2 R1 = R1 OR R2 R1 = R1 Ex Or R2 Note: Can be used only with registers are R0 to R7 Negation and Inverse: neg R2, R2; neg R2, R3; mvn R0, R1; R2 = -R2 twos complement R2 = -R3 twos complement R0 = inverse of R1 Setting a bit: ORR R0, #(1<<7); Sets bit 7 of R0 to 1 Clearing a bit: BIC R0,#(1<<7); BIC is Bit Clear instruction. Clears bit 7 Toggling a bit: EOR R0, #(1<<7); Exclusive OR to toggle bit 7 Left and Right Shift -30-

34 lsls R2, R3, #5; lsls R2, R3; lsrs R2, R3, #5; lsrs R2, R3; asrs R2, R3, #5; asrs R2, R3; shift left R3 5 times and store in R2 shift left R2, R3 value times. If R3 is 31, R2 is cleared, if R3 > 31 R2 and carry are cleared. shift right R3 5 times and store in R2 shift right R2, R3 value times. If R3 is 31, R2 is cleared, if R3 > 31 R2 and carry are cleared. arithmetic shift right R3 5 times and store in R2 arithmetic shift right R2, R3 value times. If R3 is 31, R2 is cleared, if R3 > 31 R2 and carry are cleared. Note that because shifting is done with the barrel shifter you can add a shift operation to the second source operand for most instructions. For example: add R1, R0, R0, lsl #3; R1 = R0 + R0 << 3 Branch instructions B Target; unconditional branch to target within ±2K (10 bits) B{Cond Target; conditional branch to target within -252 to +258 BL{Cond Target; Branch and link. Stores return address in R14 and conditionally branches to target. To return from subroutine move R14(link reg) into R15(PC) BX {Cond Rm; Branches indirect to address in Rm. BLX {Cond Rm; Branches indirect to address in Rm and stores return in R14 (link reg). Table 4 Condition codes for the branch instructions Condition Flags Explantion EQ Z set equal NE Z clear not equal CS/HS C set unsigned higher or same CC/LO C clear unsigned lower MI N set negative PL N clear positive or zero VS V set overflow VC V clear no overflow HI C set and Z clear unsigned higher LS C clear or Z set unsigned lower or same GE N equals V signed greater or equal LT N not equal to V signed less than GT Z clear AND (N equals V) signed greater than LE Z set OR (N not equal to V) signed less than or equal AL (ignored) always (usually omitted) Push and Pop push {R1, R2; push {R1-R5; Pushes R1 and R2 on the stack Pushes R1, R2, R3, R4, and R5 on the stack -31-

35 push {R1, R2, LR; pop {R1, R2; pop {R1-R5; pop {R1, R2, LR; Pushes R1, R2, and the link register on the stack Pops R1 and R2 on the stack Pops R1, R2, R3, R4, and R5 from the stack Pops R1, R2, and the link register from the stack Note: Can be used only with registers are R0 to R7 and the link register. Calling functions There are no call instructions in ARM assembly language. In place of an explicit call you use the BL instruction which is a Branch and Link. BL branches to the function but it also saves the return address in the link register (r14). To return from a function you use B lr (or BX lr) which branches to the address in the link register. If a function calls another function it must save the link register before doing a branch and link otherwise the original link will be destroyed. You can do this by pushing the link register on the stack push lr. To return you can pop the link register and do a BX lr or you can simply pop the stack into the program counter. The sequence below shows how to call multiple functions in assembly code:... bl Sub1... Sub1... push lr bl Sub2 pop {pc Sub2... push lr bl Sub3 pop {pc Sub3... bx lr Assembler Directives An assembler directive is a command that tells the assembler what to do with some portion of your program. It is not an executable statement. A complete list of assembler directives is given in Chapter 6 of ARM Assembler Reference [9]. The most commonly used directives are listed in Table 5 along with a brief description of what they do. Directive ALIGN AREA DCD DCDU END ENTRY EQU EXPORT Table 5 A list of frequently used ARM assembler directives Description Addresses need to be aligned on a 4-byte boundary. Use ALIGN 4 after a thumb instruction to ensure four-byte alignment since many thumb instructions are just 2-bytes long. The AREA directive instructs the assembler to assemble a new code or data section. Sections are independent, named, indivisible chunks of code or data that are manipulated by the linker. For example, AREA Ex1, CODE, READONLY could be used for a new section named Ex1. The DCD directive allocates one or more words of memory, aligned on four-byte boundaries, and defines the initial runtime contents of the memory. & is a synonym for DCD. DCDU is the same, except that the memory alignment is arbitrary. This must be used at the end of all assembly code and should appear only once in a module. Declares the entry point of a program The EQU directive gives a symbolic name to a numeric constant, a register-relative value or a PC-relative value. * is a synonym for EQU. For example Addr1 EQU 0x allows you to use Addr1 in place of the hex constant in a program. The EXPORT directive declares a symbol that can be used by the linker to resolve symbol references in separate object and library files. -32-

36 FUNCTION ENDFUNCTION IMPORT EXTERN MACRO MEND The FUNCTION directive marks the start of a function. PROC is a synonym for FUNCTION. Every FUNCTION must have a matching ENDFUNCTION and every PROC must have a matching ENDPROC These directives provide the assembler with a name that is not defined in the current assembly. The linker matches import and export names. The MACRO directive marks the start of the definition of a macro. Macro expansion terminates at the MEND directive Addressing modes The addressing modes include immediate addressing, register addressing, register indirect addressing, Pre-Indexed addressing, and PC-relative addressing. We present here an explanation of each with examples of how they are written in assembly code. Immediate addressing In this mode the operand is a value which gets loaded or stored to another location. Unfortunately, the immediate data field is only 12-bits long and this has been divided into an 8- bit value field and a 4-bit rotate field. The actual number in the immediate field evaluates to the value rotated right 2 times the number in the rotate field. Here are some examples: mov r1, #77; This works since 77 < 255 mov r1, #0101B; Move binary data to r1 mov r2, #0xF3; This is OK since F316 < mov r0, #0xF ; This is OK since we can rotate right ; F3 twice mov r1, #0x0F300000; Rotate right F3 three times mov r0, #0x0F030000; This is illegal since F0316 > The rotate would at first, appear to require several cycles but the ARM Cortex processors does this with a barrel shifter so a rotation can be done in a single cycle whether it is one bit or 16 bits. Register addressing In register addressing the operand is a direct address of a register and since there are only a few registers the direct address is much shorter than for a memory address. The ARM processor has 16 registers (r0 to r15) but since we are using the Thumb2 instruction set with 16-bit instructions instead of the full 32-bit ARM instructions, there is not room in the 16-bit format for a 4-bit register address. As a consequence most instructions can address only registers r0 to r7. Of the 56 or so instructions, only these seven have access to r8 to r12. (r12 is the stack pointer, r14 is the link register, and r15 is the program counter.) add r8, r9, r10; r8 <- r9 + r10 cmp r8, r9; subtract r8 r9 and set flags mov r8, r9; r8 <- r9 bx r9; branch to addr in r9 blx r9; branch to addr in r9 and save link msr psr, r9; prog status register <- r9 mrs r8, psr; r8 <- prog status register -33-

37 Register indirect addressing In this addressing mode a register operand holds the address of the data. Since you cannot directly address memory, you need to put an address in a register and use register indirect addressing to get at the data. ldr r0, [r1]; r0 <- data from M at address in r1 You can also do register indirect addressing with an offset as in this instruction. ldr r0, [r1, 1000]; r0 <- data from M at address r In this case the data is in memory at the address which is the sum of the data in r1 and the offset of The r1 register remains unchanged. The offset can also be a register or a shifted register as in this instruction. ldr r0, [r1, r2]; r0 <- data in M at address r1 + r2 ldr r0, [r1, r2, lsl #2]; r0 <- data in M at address r1 + r2 shifted ; left twice. In register indirect addressing the register which holds the address of the data is not changed. Pre-Indexed addressing Pre-indexed addressing the same as register indirect addressing with the exception that the register holding the address is modified with the offset. An exclamation point is used to designate this addressing mode. Here is an example of an instruction using pre-indexed addressing: ldr r0, [r1, #-255]!; r0 <- data from M at address r1 + offset ; offset ranges from -255 to For this instruction the offset (-255) is added to r1 and r1 is modified. This sum is used as the memory address of where to find the data. Post-Indexed addressing Post-indexed addressing is the same as indexed addressing except that the offset is added to the index register after the load. ldr r0, [r1], #-255; r0 <- data from M at address r1. Offset ; is added to r1 after load In this example, the data at the memory whose address is in r1 is loaded into r0. After this load r1 is modified to the sum of r1 and the offset. PC-relative addressing In PC-relative addressing the program counter plus an offset form the address of the data in memory which can be loaded into a register. ldr r0, [pc+15]; r0 <- data from M at address pc + 15 While you can use this explicitly the assembler also uses it implicitly in place of direct addressing. If you write ldr r0, =0x ; The assembler converts this to something like this: ldr r0, [pc+23]; and it stores the number 0x along with the program at the location pc+23. This makes it appear as if you can load an immediate value into a register with the ldr instruction. You can do something similar by creating your own data area in memory. -34-

38 AsmLoopExmp PROC push {r0-r5;... ldr r0, =Data ldr r1, [r0]; ldr r2, [r0, #4];... pop {r0-r5; bx lr; ENDP save the registers Restore the registers Data DCD 0x , 0x The term DCD is an assembler directive to create storage for a 32-bit word or multiple words. Data is a label at the location of the two words created. The instruction ldr r0, =Data appears to load the address of Data into r0 as an immediate operand. But in fact, the assembler converts this sequence to PC-relative addressing: ldr r0, [pc+24]; where the assembler has calculated that the label Data is 24 bytes ahead of its present location. You could do the same thing by hand but this notation makes it much easier. Programming in Assembly Code There are two methods that can be used to write assembly code in Keil µvision 5. The first is to write a function in assembly code and incorporate that function in a main program written in C. The second is to write the assembly code directly. Writing an Assembler function in a C-Code program To use this method you write a main program in C-code and use the C-code to call the assembler function. You will need to use a function prototype and it can have a return value and a parameter list. The first four parameters are passed in the registers R0, R1, R2, and R3. If there are more than four parameters the remainder are passed on the stack. The return value always comes back in R0. The sample code in Figure 4.6 shows a c-program which called an assembler function called Add2 and passes it two integer parameters. The function adds the two parameters which it catches in R0 and R1 and returns the sum in R