Specifying time in VHDL

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1 Computer System Structures cz:struktury počítačových systémů Lecturer: Richard Šusta Version: 1.0 ČVUT-FEL in Prague, CR subject A0B35SPS Specifying time in VHDL Picture: ECE 545 Introduction to VHDL 1

2 Unit Base Unit fs Derived Units ps ns us ms sec min hr Definition femtoseconds (10-15 seconds) picoseconds (10-12 seconds) nanoseconds (10-9 seconds) microseconds (10-6 seconds) miliseconds (10-3 seconds) seconds minutes (60 seconds) hours (3600 seconds) Units of time 3 Physical data types TIME is the only predefined physical data type, Note: Types representing physical quantities, such as time, voltage, capacitance, etc. are referred in VHDL as physical data types. Value of the physical data type is called a physical literal and it can be an integer or a floating point number. Numeric value and dimension MUST be separated by a space. Numeric value of time is optional. If not given, 1 is implied. Smallest available resolution in VHDL is 1 fs. 4 2

3 Examples 7 ns 1 min min us 978 fs Numeric value Space Unit of time (dimension) 5 Arithmetic operations on TIME Examples: 7 ns + 10 ns = 17 ns 1.2 ns 12.6 ps = fs 5 ns * 4.3 = 21.5 ns 20 ns / 5ns = 4 6 3

4 ECE 545 Introduction to VHDL "Sensitivity list" "wait on! process(a,b) -- some statements, e.g. y<=a and b; process -- some statements, e.g. y<=a and b; end process; a b y wait on a, b; end process; Function Until a or b inputs are unchanged, y remains the same <- the property of combinational circuits 8 4

5 Quartus Assembling the circuit from the code is not an easy task, so synthesis tools allow only a subset of VHDL. Quartus here requires sensitivity list - but remember that sensitivity lists are not analogous to parameters of functions, but only another form how to specify waiting condition for signal changes, clearer relocations of "wait on" statements to the ning of processes. process(a,b) -- some statements, e.g. y<=a and b; end process; process -- some statements, e.g. y<=a and b; wait on a, b; end process; 9 VHDL Wait Statements in simulation Four possible kinds of wait-statements: wait on signal list; wait until signal changes; e.g.: wait on a; wait until condition; wait until condition is met; e.g.: wait until c='1'; wait for duration; wait for specified amount of time; e.g.: wait for 10 ns; wait; suspend indefinitely 10 5

6 Example variable - signals ECE 545 Introduction to VHDL Design AND gate that can be switched by input isnand to NAND. Example: a b isnand='0' y a b isnand='1' y SPS 12 6

7 Solution P The task can be solved easily a) e.g. by equation: y <= (a and b) xor isnand; b) or by multiplexer: y <= a and b when isnand='0' else not (a and b); but student PAT has decided to use process to test it. Picture: SPS 13 Entity definition library ieee; use ieee.std_logic_1164.all; entity n2and is port (a, b, isnand: in std_logic; end entity; y : out std_logic); n2and a b isnand inst y SPS 14 7

8 architecture dataflow of n2and is P-solution with variable process(a,b, isnand) variable tmp : std_logic; tmp:=a and b; if isnand='1' then tmp:=not tmp; end if; y<=tmp; end process; end architecture; SPS 15 P-result Principle schema a b tmp~0 tmp~1 0 1 isnand y Comment: Quartus convert multiple assignment of variables to unique assignments by introducing auxiliary internal variables tmp~ 0 and tmp~1. Appendix: Character ~ is reserved only for names generated by the compiler, it cannot be used in code. SPS 16 8

9 Simulation and nand SPS 17 Variables Eng: VHDL reference: The immediate assignment, notion : =, takes effect immediately without any time dimension (i.e. without propagation delay). The behavior of variable assignments are just like that of a regular variable assignments used in traditional programming languages. Consequence: The value that you assign to variables in the code of a process we can immediately read.. SPS 18 9

cz/ SPS 19 Wrong solution- the circuit got MAT architecture dataflow of n2and is signal tmp :

10 Řešení M Mat did not like Pat's solution and he has reorganized the code using signals. Signal - it does sound better than some variable :-) Picture: SPS 19 Wrong solution- the circuit got MAT architecture dataflow of n2and is signal tmp : std_logic; process(a,b, isnand) tmp<=a and b; if isnand='1' then tmp<=not tmp; end if; y<=tmp; end process; end architecture; SPS 20 10

11 Wrong result Warning (332125): Found combinational loop of 2 nodes Principle schema a b tmp~0 tmp~1 0 1 isnand y SPS 21 Simulation "Functional simulation" failed -> buffer overflow "Timing-simulation" with propagation delay of gate give result with oscilations y y Time SPS 22 11

12 Pat dicoved Assignments blocking := + non-blocking <= ECE 545 Introduction to VHDL George Mason University 2 Kinds of Assignments Variable assignments (blocking, immediate) Syntax: variable := expression; Signal assignments (non-blocking, delta-cycle) Syntax: signal <= expression; signal <= expression after delay; signal <= transport expression after delay; signal <= reject time inertial expression after delay; 24 12

13 Transport Delay signal <= transport expression after delay; This corresponds to models for simple wires Pulses will be propagated, no matter how short they are. 25 a b Example: a b a or b Transport Delay c <= transport a or b after 10 ns; 1 OR gate y y ns Pulse of 5 ns 26 13

14 Inertial Delay Suppression of all spikes shorter than the delay. By default, inertial delay is assumed as "after" parameter to model the behavior of gates. To switch state, gates require that input pulse cross a certain threshold and remain unchanged for a certain period of time (hold time). If the pulse is small, the gate will not change state. The minimum pulse width for an input pulse to cause a change in state for a gate is called the inertial delay of the gate 27 Example Inertial Delay c <= a or b after 10 ns; c <= INERTIAL a or b after 10 ns; c <= REJECT 10 ns INERTIAL a or b after 10 ns; equivalent a b a or b y ns 5 ns pulz is suppressed 28 14

15 Signals VHDL Reference: In contrast to variables, the values assigned to signals can be read back only after at least a delta cycle (δ) time, infinitesimally small advance in time - i.e. in reality, a signal is updated during the next evaluation of the process. SPS 29 Delta Delay If we write statement output <= 0 ; it will be processed as output <= 0 after δ; In the code for the synthesis, the after keyword can never appear - The exact time delay cannot be realized. Compiler however will assemble all "<=" assignments as equivalents after δ; where delta represents an infinitesimal delay. Note: δ represents an imaginary internal compiler symbol, a user's code cannot use it 30 15

16 Signaly You can imagine situation as a circuit, where signals (wires) contain input values of the circuit and we only assign them new output values. x_signal our code new value propagation delay of a circuit If a signal is only used within a process and it is not read by any other process, it can be replaced by a variable. Variable have advantage of limited (localized) scope, which in general is a good thing. Remember that signals are only one reasonable way for interconnecting more processes or circuits, i.e. transfer values from one process or circuit to another. SPS 31 Pat made finally this correction architecture dataflow of n2and is signal tmp : std_logic; process(a,b, isnand) tmp<=a and b; if isnand='1' then tmp<=not (a and b); end if; y<=tmp; end process; end architecture; P-code does not use the value assigned to tmp signal inside of the process - the new value appears with delay. SPS 32 16

17 Result is again correct SPS 33 How it will write others? For example by this way - that is multiplexer architecture dataflow of n2and is process(a, b, isnand) if isnand='1' then y<=not (a and b); else y<= a and b; end if; end process; end architecture; SPS 34 17

18 Simulation in VHDL better understanding of code and time saving ECE 545 Introduction to VHDL George Mason University TESTING OUR DESIGN by d o w n l o ading our d e s i g n i n t o m a c h i n e s Vladimít Wagner, Ocelové město,

19 Testbench for Errors Simulator Not Found Found Our intentions Our design Testing our design by TESTBENCHES IN VHDL 37 Testing & simulation Formal Verification Test vectors Design Under Test Patterned vectors Test properties e.g. hazard... System Model Find counter-example Test results True or False Cannot cover all possible cases Possibility of surviving subtle (corner case) bugs Equivalent to simulating all cases in simulation No bug according to the specified property It is always possible Sometimes it is possible 38 19

20 inputs inputs outputs outputs Simulation of PAT 39 Testbench stimuli by force commands (analogy to Vector Wave Form file) Our design graph vhdl Testbench stimuli written in vhdl code Our design We can automatically compare results with required values. stimulus, pl. stimuli (from Latin stilus, stylus->style) - something that rouses the mind or spirits or incites to activity - cz: podnět, stimul SPS 40 20

21 Keyword after in simulation z <= 1, 0 after 5 ns, 1 after 10 ns; key0 <= 0, 1 after 30 ns; -- inicialization clk <= not clk after 5 ns; -- clocks z key0 signal clk : std_logic:='0'; signal z, key0 : std_logic; Note Initialized signals (wires), are synthesized very difficult. Quartus often refuses and writes about it just a warning. Suitable only in simulation!! clk ns 41 library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity tb0 is end entity; -- entity for testbench does not contain declarations architecture testbench of tb0 is component n2and is port ( a, b, isnand : in std_logic; y : out std_logic ); end component; signal x: unsigned(2 downto 0) := "000"; signal y, stop : std_logic; -- statements of architecture end architecture; testbench for Pat's program 42 21

22 x<= x+1 after 10 ns; -- x: unsigned(2 downto 0) := "000"; stop<='0', '1' after 320 ns; -- stop : std_logic; in2and : n2and port map( x(0), x(1), x(2), y ); -- (a,b,isnand,y) assert stop /= '1' report "Done!" severity failure; end architecture; 43 tb0 ekvivalent is Quartus functional simulation for 320 ns and nand - in reality, Quartus performs simulation by automatically created testbench from "Vector Wave Form file". 22

23 DEMONSTRATION OF MODELSIM ALTERA Result of ModelSim simulation 46 23

24 Asserts & Reports Fujita M: Introduction to VHDL, VDEC Tokyo Assert Assert is a non-synthesizable statement whose purpose is to write out messages on the screen when problems are found during simulation or synthesis. Depending on the severity of the problem, The simulator or compiler is instructed to continue or halt. Fujita M: Introduction to VHDL, VDEC Tokyo

25 Assert - syntax ASSERT condition [REPORT "message"] [SEVERITY severity_level ]; The message is written when the condition is FALSE. Severity_level can be: Note, Warning, Error (default), or Failure. Fujita M: Introduction to VHDL, VDEC Tokyo Assert - Examples assert initial_value <= max_value report "initial value is too large" severity error; assert packet_length > 0 report "Code defines empty packet length" severity warning; assert false report "Initialization complete" severity note; Fujita M: Introduction to VHDL, VDEC Tokyo

26 Report - syntax REPORT "message" [SEVERITY severity_level ]; The message is always written. Severity_level can be: Note (default), Warning, Error, or Failure. Fujita M: Introduction to VHDL, VDEC Tokyo Report - Examples report "Initialization complete"; report "Current time = " & time'image(now); report "Incorrect branch" severity error; Fujita M: Introduction to VHDL, VDEC Tokyo

27 yrow xcolumn VGA register Simulation of VGA inputs easy outputs difficult 53 Inputs and outputs of VGA Setting 10 or 8 bit colors constant size generator Clk AClrn 25 MHz 2 task 2 DisplayLogic Logic functions of colors Generator of VGA synchronization VGA_ CLK VGA_HS VGA_SYNC VGA_BLANK VGA_VS VGA_ CLK 10/8 10/8 10/8 VGA_R VGA_G VGA_B VGA_HS VGA_SYNC VGA_BLANK VGA_VS VGA_ CLK Storage of result into file SPS 54 27

28 Inputs -- Tested the size input of our DisplayLogic, -- change from "00" to "11" constant SIZE_SWITCH : std_logic_vector(1 downto 0) := "10"; Possible solutions depended on the initialization of signal signal CLK_25MHz175 : std_logic := '0'; constant CLOCK_PERIOD : time := ns; CLK_25MHz175 <= not CLK_25MHz175 after CLOCK_PERIOD / 2; SPS 55 Better CLK_25MHz175 signal CLK_25MHz175 : std_logic; constant CLOCK_PERIOD : time := ns; clk_process : process --for 50 % of CLK_25MHz175 period is'0'. CLK_25MHz175 <= '0'; wait for CLOCK_PERIOD/2; --for next 50% of CLK_25MHz175 period is '1'. CLK_25MHz175 <= '1'; wait for CLOCK_PERIOD/2; end process; SPS 56 28

29 Input ACLRN signal ACLRN_signal : std_logic; -- Clear process generates ACLRN for 1 CLOCK_PERIOD. clear_process :process ACLRN_signal <= '0'; wait for CLOCK_PERIOD; ACLRN_signal <= '1'; wait; -- wait forever => terminate process end process; SPS 57 DEMONSTRATION OF MODELSIM ALTERA 29

ECE 545 Lecture 4. Simple Testbenches. George Mason University

ECE 545 Lecture 4. Simple Testbenches. George Mason University ECE 545 Lecture 4 Simple Testbenches George Mason University Required reading P. Chu, RTL Hardware Design using VHDL Chapter 2.2.4, Testbenches 2 Testbenches ECE 448 FPGA and ASIC Design with VHDL 3 Testbench