Outline of this Introduction to VHDL

Transcription

1 Outline of this Introduction to VHDL 1) Formal Construction of VHDL Models 2) Test Environments, Test Benches VHDL models providing input signals (stimuli) to verify (test) the correct function (and timing) of a model 3) Timing Models in VHDL Simulation of the timing behavior of the modeled hardware 4) Modeling of Finite State Machines in VHDL Systematic approach to describe digital systems 1

2 Timing Models in VHDL Timing Models in VHDL 2

3 Signal Assignments Signal assignment statements update the values of signals: SUM <= A + B; This statement describes the function of an adder. The expression to the right of the <= symbol is evaluated, its resulting data type must match the signal s data type. Signal assignments are similar to variable assignments, except that they cause the signal s value to be updated at some future time. Because in hardware circuits the output does not change immediately after a changing input signal, its model can contain an optional delay time: CARRY <= A and B after 7 ns; In (analog) electronic circuits capacitances and inductances cause transient effects, which are abstracted by means of a lumped delay in the digital model. 3

4 Waveforms & Delay Mechanisms A waveform describes a sequence of values in chronological order: CLK <= '1' after PulsWidth, '0' after 2*PulsWidth; All times refer to the actual simulation time, i.e. the time when the signal assignment statement is executed. Because signal values are updated at some future time a new transaction must be merged with pending transactions. The way this is done depends on the optional delay mechanism. Default is the inertial mechanism. SUM <= transport A + B after 12 ns; 4

5 Process Statements There are two (equivalent) forms to describe processes: Processes without a sensitivity list (containing wait statements): Statements in the process body are executed in sequence. After the last statement the first statement is executed next without updating the simulation time. Wait statements are used to suspend processes. To avoid infinite loops at least one wait statement must exist. Processes with a sensitivity list (containing no wait statements): The sensitivity list is a list of signal names. A process is activated when at least one of these signals changes its value. This process form is equivalent to a process with a wait-onsignal statement before the end-process statement. This type of process must not contain wait statements. 5

6 Wait Statements A wait statement causes the process that executes the statement to suspend execution. Four variants exist: wait on CLK_SIGNAL, ENABLE; sensitivity clause The process resumes execution, when at least one of the named signals changes its value. wait until CLOCK='1'; condition clause The Boolean expression must be true for the process to resume. wait for 1 ms; wait for 2*ClockPeriod; time-out clause The process resumes execution after the given delay time. wait; The process executes exactly once during initialization and remains inactive afterwards. 6

7 Example: Clock Generator (1) signal CLK: bit:='0'; constant PulsWidth: time:=20 ns; -- physical type ClockGen1: process(clk) if CLK='0' then CLK <= '1' after PulsWidth, '0' after 2*PulsWidth; -- waveform end if; end process ClockGen1; 1 0 Activation ns

8 Example: Clock Generator (2) signal CLK: bit:='0'; constant PulsWidth: time:=20 ns; -- physical type ClockGen2a: process CLK <= '1' after PulsWidth, '0' after 2*PulsWidth; wait until CLK='0'; -- i.e. wait until -- CLK changes to '0' end process ClockGen2a; ClockGen2b: process CLK <= '1' after PulsWidth, '0' after 2*PulsWidth; wait for 2*PulsWidth; -- i.e. wait for -- this time interval end process ClockGen2b; 8

9 Example: Clock Generator (3) signal CLK: bit:='0'; constant PulsWidth: time:=20 ns; -- physical type ClockGen3: process CLK <= '0'; wait for PulsWidth; CLK <= '1'; wait for PulsWidth; end process ClockGen3; ns 9

10 Example: 2-Input Multiplexer (1) entity MUX2 is port(a, B, SEL: in bit; Z: out bit); end MUX2; SEL architecture behavior_1 of MUX2 is constant prop_delay: time := 2 ns; MUX2_V1: process(a, B, SEL) -- value changes of A, B, or SEL can -- result in value changes at output Z! case SEL is when '0' => Z <= A after prop_delay; when '1' => Z <= B after prop_delay; end case; end process MUX2_V1; end behavior_1; A B 0 1 Z 10

11 Example: 2-Input Multiplexer (2) architecture behavior_2 of MUX2 is constant prop_delay: time := 2 ns; MUX2_V2: process case SEL is when '0' => Z <= A after prop_delay; wait on SEL, A; -- The process does not wait for B, -- if A is selected! when '1' => Z <= B after prop_delay; wait on SEL, B; end case; end process MUX2_V2; end behavior_2; A B 0 1 SEL Z 11

12 Dataflow Models Dataflow models (or functional models) are behavioral models, where the operation to be described is a simple combinational transformation of inputs to an output. VHDL provides some useful shorthand notations, the concurrent signal assignment statements. Conditional signal assignment (e.g. 2-Input multiplexer): Z <= A after DELAY when SEL='0' else B after DELAY when SEL='1'; Selected signal assignment (e.g. 2-Input multiplexer): with SEL select Z <= A after DELAY when '0', Z <= B after DELAY when '1'; Dataflow models can be used for automatic synthesis of the circuit s structure on gate level. 12

13 Dataflow Model of a 2x4 Decoder entity DEK2X4 is port (A, B, EN: in bit; D: out bit_vector(0 to 3)); end DEK2X4; architecture DATAFLOW of DEK2X4 is signal AQ, BQ: bit; -- 6 concurrent signal assignments -- The sequence of the statements is irrelevant D(3) <= not(a and B and EN); -- (1) D(0) <= not(aq and BQ and EN); -- (2) BQ <= not B; -- (3) D(2) <= not(a and BQ and EN); -- (4) AQ <= not A; -- (5) D(1) <= not(aq and B and EN); -- (6) end DATAFLOW; 13

14 Dataflow Model of a 2x4 Decoder entity DEK2X4 is port (A, B, EN: in bit; D: out bit_vector(0 to 3)); end DEK2X4; architecture DATAFLOW of DEK2X4 is signal AQ, BQ: bit; -- 6 concurrent signal assignments -- A value change (event) at input B is assumed D(3) <= not(a and B and EN); -- (1) D(0) <= not(aq and BQ and EN); -- (2) BQ <= not B; -- (3) D(2) <= not(a and BQ and EN); -- (4) AQ <= not A; -- (5) D(1) <= not(aq and B and EN); -- (6) end DATAFLOW; 14

15 Dataflow Model of a 2x4 Decoder entity DEK2X4 is port (A, B, EN: in bit; D: out bit_vector(0 to 3)); end DEK2X4; architecture DATAFLOW of DEK2X4 is signal AQ, BQ: bit; -- 6 concurrent signal assignments -- Events occur at signals D(3), BQ, and D(1) D(3) <= not(a and B and EN); -- (1) D(0) <= not(aq and BQ and EN); -- (2) BQ <= not B; -- (3) D(2) <= not(a and BQ and EN); -- (4) AQ <= not A; -- (5) D(1) <= not(aq and B and EN); -- (6) end DATAFLOW; 15

16 Simulation of the 2x4 Decoder Time Events Actions T input B Triggering statements (1), (3), and (6), Evaluation of the statement s right hand sides, Scheduling of value assignments to signals D(3), BQ, and D(1) T 1 >T D(3), BQ, D(1) Assignment of values to signals D(3), BQ, and D(1), Triggering statements (2) und (4), Evaluation of their right hand sides, Scheduling of value assignments to signals D(0) and D(2) T 2 >T 1 D(0), D(2) Assignment of values to D(0) and D(2) 16

17 Circuit Analysis: Simulation & Verification Circuit designs must be evaluated (tested) to eliminate as many design errors as possible, before the expensive production of the circuit is started. Circuit simulation means, that for a set of input signals (stimuli) specified circuit properties are determined over some time interval and compared with the expected values. To allow the simulation of very large circuits simulators must be extremely efficient. For digital circuits this can be achieved by event-driven simulation. The idea behind this approach is, that the circuit s components are (in contrast to analog simulation) evaluated only if a value change (event) occurs at one or more component inputs. Circuit verification is a formal method, to verify the correctness of a design by exact mathematical methods (proofs). A mathematical statement of the function of the system (using temporal logic, e.g.) is thus required. 17

18 Transactions & Events The term simulation time refers to the time, in which the circuit being modeled is deemed to operate. Simulation time is measured starting from zero at the start of execution and increasing in discrete steps as events occur in the model. That is why this is called discrete event simulation. Simulation time is distinct from execution time of the VHDL model running on a host computer. When executing a signal assignment statement a transaction is scheduled for later execution. A transaction is stored as a pair of values (new_signal_value, simulation_time). When at simulation time of a transaction the new signal value differs from the previous value, we refer to this as the occurrence of an event. Processes react on events, not on transactions! 18

19 Signal Drivers A signal driver is a chronologically ordered list of all transactions scheduled for this signal, i.e. a list of value pairs (signal_value, simulation_time) = (V i,t i ). Every driver contains at least one entry, the current signal value (V 0,T 0 ), at the start of simulation the initialized value: (V 0,T 0 ), (V 1,T 1 ), (V 2,T 2 ), (V 3,T 3 ),... V 1 V 2 V 3 T 1 T 2 T 3 A driver is a data source, which stores/provides values for future assignments to a signal. A process defines a driver for a signal name, when there exists at least one assignment for the signal in the process. Basically only one driver per signal is allowed. If a signal is driven by more than one source (e.g. bus, wired OR) a resolution function must be specified to define the resulting signal value. 19

20 Simulation Cycle (1) Event-driven simulation exploits the observation, that the outputs of a circuit component must be computed only, when a value change (event) occurs at one or more input ports. This is implemented by the following simulation cycle: Initialization Phase The initial values are assigned to all variables and signals. The simulation time is set to 0 fs. All processes are activated, their statements executed and on a wait statement suspended again. Then Signal Update Phase Process Execution Phase 20

21 Simulation Cycle (2) Initialization Phase Signal Update Phase - Advance the simulation time to the earliest time at which a transaction (or process timeout) is scheduled - Execution of all transactions stored for the current time. Process Execution Phase - Processes, which have events on signals of their sensitivity list, resume execution. Possible consequence: New transactions for the same or a later time. 21

22 Simulation of a Signal Assignment Let us assume the assignment statement DATA <= X"00" after DELAY; is executed at simulation time T. A transaction of the hexadecimal value X"00" is scheduled for signal DATA at simulation time T+DELAY. The value of signal DATA is not yet updated. All active processes continue execution. After all processes have been suspended, the next simulation cycle is started and the simulation time advanced. When the simulator reaches simulation time T+DELAY, the scheduled value X"00" is assigned to signal DATA and all processes sensitive to DATA are started. 22

23 Delta Delays Signal delay times can be optionally specified in a signal assignment statement. If no delay is given, 0 fs are assumed. When executing an assignment only a transaction is scheduled for the signal. Thus, even with a delay of 0 fs no immediate change of the signal value occurs and the process does not notice the value change until its next execution (during the next simulation cycle). Even with a delay of 0 fs a new simulation cycle is performed, although the simulation time does not change; this is called a delta delay (an infinitesimally small time step). The concept of delta delays guaranties the causality of the statements. Thus, a simulation is possible, even if no delays are known. 23

24 Implicit Generation of Edge-Controlled FlipFlops (1) library ieee; use ieee.std_logic_1164; entity ANDOR is port (A,B,C: in std_ulogic; CLK: in std_ulogic; Z: out std_ulogic); end ANDOR; A B & AND D Q architecture AAO1 of ANDOR is signal P: std_ulogic; AOprocess: process (CLK) if rising_edge(clk) then P <= A and B; Z <= P or C; end if; end process; end AAO1; P ANDOR C nq 1 OR D Q CLK nq Z 24

25 Implicit Generation of Edge-Controlled FlipFlops (2) library ieee; use ieee.std_logic_1164; entity ANDOR is port (A,B,C: in std_ulogic; CLK: in std_ulogic; Z: out std_ulogic); end ANDOR; A B & AND architecture AAO2 of ANDOR is AOprocess: process (CLK) variable P: std_ulogic; if rising_edge(clk) then P := A and B; Z <= P or C; end if; end process; end AAO2; P ANDOR C 1 OR D Q CLK nq Z 25

26 Simulation Cycle An Example architecture TestArch of TestEntity is signal A, B: integer := 0; A <= 1 after 3 ns, 2 after 7 ns; TestProcess: process(a) variable C: integer := -1; B <= A; -- Signal assignment (scheduled!) C := B; -- Variable assignment (immediate!) end process TestProcess; end TestArch; A B C 0 ns 26

27 Simulation Cycle An Example architecture TestArch of TestEntity is signal A, B: integer := 0; A <= 1 after 3 ns, 2 after 7 ns; TestProcess: process(a) variable C: integer := -1; B <= A; -- Signal assignment (scheduled!) C := B; -- Variable assignment (immediate!) end process TestProcess; end TestArch; 0 ns A 0 B 0 C 0 27

28 Simulation Cycle An Example architecture TestArch of TestEntity is signal A, B: integer := 0; A <= 1 after 3 ns, 2 after 7 ns; TestProcess: process(a) -- not activated! variable C: integer := -1; B <= A; -- Signal assignment (scheduled!) C := B; -- Variable assignment (immediate!) end process TestProcess; end TestArch; 0 ns 0 ns + A 0 0 B 0 0 C

29 Simulation Cycle An Example architecture TestArch of TestEntity is signal A, B: integer := 0; A <= 1 after 3 ns, 2 after 7 ns; TestProcess: process(a) variable C: integer := -1; B <= A; -- Signal assignment (scheduled!) C := B; -- Variable assignment (immediate!) end process TestProcess; end TestArch; 0 ns 0 ns + 3 ns A B C

30 Simulation Cycle An Example architecture TestArch of TestEntity is signal A, B: integer := 0; A <= 1 after 3 ns, 2 after 7 ns; TestProcess: process(a) - not activated! variable C: integer := -1; B <= A; -- Signal assignment (scheduled!) C := B; -- Variable assignment (immediate!) end process TestProcess; end TestArch; 0 ns 0 ns + 3 ns 3 ns + A B C

31 Simulation Cycle An Example architecture TestArch of TestEntity is signal A, B: integer := 0; A <= 1 after 3 ns, 2 after 7 ns; TestProcess: process(a) variable C: integer := -1; B <= A; -- Signal assignment (scheduled!) C := B; -- Variable assignment (immediate!) end process TestProcess; end TestArch; 0 ns 0 ns + 3 ns 3 ns + 7 ns A B C

32 Simulation Cycle An Example architecture TestArch of TestEntity is signal A, B: integer := 0; A <= 1 after 3 ns, 2 after 7 ns; TestProcess: process(a) variable C: integer := -1; B <= A; -- Signal assignment (scheduled!) C := B; -- Variable assignment (immediate!) end process TestProcess; end TestArch; 0 ns 0 ns + 3 ns 3 ns + 7 ns 7 ns + A B C

33 How Does the Transport Delay Affect the Driver? Modeling the signal delay of an ideal circuit with unlimited bandwidth, even shortest pulses are transferred. Signal driver: (V 0,T 0 ), (V 1,T 1 ), (V 2,T 2 ),..., (V i,t i ),..., (V k,t k ) Rules for inserting a new transaction (V n,t n ): All transactions (V i,t i ) with T n T i are deleted. The new transaction (V n,t n ) is appended to the end of the list. Only the delay influences the result, the signal value does not. 33

34 Example: Ideal Transmission Line signal LineIn, LineOut: bit := '0';... TransmissionLine: process(linein) LineOut <= transport LineIn after 50 ps; end process TransmissionLine; LineIn LineOut ps Driver for LineOut '1' 70 '1' 70 '0' 100 '1' 70 '0' 100 '0'

35 Example: Asymmetric Delay signal A, Z: bit := '0';... AsymDelay: process(a) if A='1' then Z <= transport A after 80 ps; else - A='0' Z <= transport A after 50 ps; end if; end process AsymDelay; A Z ps ps Driver for Z '1' 100 '0' 90 '1' 100 No Event! 35

36 How Does the Inertial-Delay Affect the Driver? Modeling of real circuits where electronic charge is moved around in the presence of capacitances and inductances. This gives the device some inertia. Inertial delay is the default. Signal driver: (V 0,T 0 ), (V 1,T 1 ), (V 2,T 2 ),..., (V i,t i ),..., (V k,t k ) Rules for inserting a new transaction (V n,t n ): All transactions (V i,t i ) with T n T i are deleted. The new transaction (V n,t n ) is appended to the end of the list. In the interval T 0 T i T n an uninterrupted sequence of transactions (V i,t i ),..., (V n,t n ) with V i = V n is maintained, all other transactions are erased. Delay and signal value influence the behavior. 36

37 Example: Inverter with Delay signal A: bit := '0'; signal Y: bit := '1';... INV: process(a) Y <= inertial not A after 3 ns; end process INV; A ns ns 37

38 Example: Inverter with Delay signal A: bit := '0'; signal Y: bit := '1';... INV: process(a) Y <= inertial not A after 3 ns; end process INV; A Y ns ns Driver for Y '0' 4 '0' 4 '1' 9 '1' 9 '0' 11 No Event! '0' 11 38

39 Example: 2-Input AND Gate library IEEE; use IEEE.std_logic_1164.all; entity And2 is port(a, B: in std_logic; Y: out std_logic); end And2; architecture And2_with_delay of And2 is signal AndOut: std_logic; And2_gate: process(a, B) - idealized AND Gate AndOut <= A and B; end process And2_gate; And2_delay: process(andout) if AndOut='1' then Y <= inertial '1' after 1.5 ns; elseif AndOut='0' then Y <= inertial '0' after 1.2 ns; else Y <= inertial 'X' after 0.5 ns; end if; end process And2_delay; end And2_with_delay; delay 39

40 Example: 2-Input AND Gate Waveforms A B ns 40

41 Example: 2-Input AND Gate Waveforms A 1 0 B 1 0 AndOut 1 0 uninit. 1 ns 1 ns Y 1 0 uninitialized ns '0' 2,2 '0' 2,2 '1' 7,5 '1' 7,5 Driver for Y '1' 3,5 '1' 3,5 '0' 4,2 '0' 4,2 41

42 Finite State Machines Finite State Machines 42

43 Finite State Machines abbreviated FSM Systematic method for describing and designing digital systems The realization of cyclic functional processes is facilitated, e.g. control of logic circuits synchronization of subsystems FSMs are synchronous sequential circuits, i.e. all functions are clocked by a periodic clock signal. FSMs are sequentially working logic circuits, which pass through a sequence of states controlled by a periodic clock signal. Basic types are the Moore type machine and the Mealy type machine. 43

44 Moore Type FSM The output signals of a Moore FSM are only a function of the current state of the FSM. The input signals can influence the output only via the state memory. E input signals A output signals Z current states Z + successor states next state state output A E logic Z + memory Z logic enable clock reset 44

45 Mealy Type FSM The output signals of a Mealy FSM are a function of the current FSM state and the input signals. E input signals A output signals Z current states Z + successor states next state state E logic Z + memory Z output A logic enable clock reset 45

46 FSM Properties Synchronous sequential circuit with three functional blocks: State memory N synchronously clocked flipflops 2 N states can be binary coded Every (positive) edge of the clock signal has the effect that the successor states Z + are stored as current states Z for one clock period With the enable signal the operation can be blocked With the reset signal the state memory can be initialized with an arbitrary bit pattern Next state logic combinatorial logic Output logic combinatorial logic 46

47 FSM Example: Recognition of Bit Patterns (1a) Recognition of three successive 2-bit patterns (01, 11, 10) at the two input ports Successful recognition is displayed with the output signal 1 The 1-signal of the output signal shall be displayed for one clock period State diagram (Moore): X Reset Z0 0 X0 01 Z1 0 X Z Z2 0 47

48 FSM Example: Recognition of Bit Patterns (1b) entity FSM_Moore is port(clock, Reset, Enable: in bit; E: in bit_vector(1 downto 0); A: out bit); end FSM_Moore; architecture Sequence of FSM_Moore is type States is (Z0, Z1, Z2, Z3); -- enumeration type signal State, NSt: States; StateMem: process(clock, Reset) if Reset='1' then State <= Z0 after 20 ns; elseif Clock='1' and Clock'event then if Enable='1' then State <= NSt after 20 ns; end if; end if; end process StateMem;... 48

49 FSM Example: Recognition of Bit Patterns (1c) NextStateLogic: process(e, State) case State is when Z0 => if E="01" then NSt <= Z1 after 20 ns; else NSt <= Z0 after 20 ns; end if; when Z1 => if E="11" then NSt <= Z2 after 20 ns; elseif E="01" then NSt <= Z1 after 20 ns; else NSt <= Z0 after 20 ns; end if; when Z2 => if E="10" then NSt <= Z3 after 20 ns; elseif E="01" then NSt <= Z1 after 20 ns; else NSt <= Z0 after 20 ns; end if; when Z3 => if E="01" then NSt <= Z1 after 20 ns; else NSt <= Z0 after 20 ns; end if; end case; end process NextStateLogic; 49

50 FSM Example: Recognition of Bit Patterns (1d)... OutputLogic: process(state) case State is when Z3 => A <= '1' after 20 ns; when others => A <= '0' after 20 ns; end case; end process OutputLogic; end Sequence; 50

51 FSM Example: Recognition of Bit Patterns (2a) Recognition of three successive 2-bit patterns (01, 11, 10) at the two input ports Successful recognition is displayed with the output signal 1 The 1-signal of the output signal shall be displayed for one clock period State diagram (Mealy): Reset X0/0 11/0 Z0 X0/0 01/0 01/0 Z1 00/0 11/0 10/1 01/0 11/0 Z2 51

52 FSM Example: Recognition of Bit Patterns (2b) entity FSM_Mealy is port(clock, Reset, Enable: in bit; E: in bit_vector(1 downto 0); A: out bit); end FSM_Mealy; architecture Sequence of FSM_Mealy is type States is (Z0, Z1, Z2); -- enumeration type signal State, NSt: States; StateMem: process(clock, Reset) if Reset='1' then State <= Z0 after 20 ns; elseif Clock='1' and Clock'event then if Enable='1' then State <= NSt after 20 ns; end if; end if; end process StateMem;

53 FSM Example: Recognition of Bit Patterns (2c) NextStateLogic: process(e, State) NSt <= Z0 after 20 ns; case State is when Z0 => if E="01" then NSt <= Z1 after 20 ns; end if; when Z1 => if E="11" then NSt <= Z2 after 20 ns; elseif E="01" then NSt <= Z1 after 20 ns; end if; when Z2 => if E="01" then NSt <= Z1 after 20 ns; end if; end case; end process NextStateLogic; OutputLogic: process(e, State) A <= '0' after 20 ns; if (State=Z2 and E="10") then A <= '1' after 20 ns; end if; end process OutputLogic; end Sequence; 53