Power Reduction through Software-Programmable Accelerators for ARM-based Subsystems

Transcription

1 Power Reduction through Software-Programmable Accelerators for ARM-based Subsystems Gert Goossens CEO Target Compiler Technologies Target Compiler Technologies 1

2 Low Power: Back to Basics Dynamic power P dyn = C (A f clock ) V dd 2 Locality of reference Avoid switching f-scaling Concurrency: task-, data-, instr.-level Low-V technology V-scaling Leakage power ["Moore's Law Meets Static Power", Computer, IEEE Comp. Soc., Dec. 2003] P leak = I leak V dd ~ (a -Vt N gates W dev ) V dd Multitreshold libraries Minimal logic Power gating 2012 Target Compiler Technologies 2

3 Heterogeneous Multicore SoC Dual and quad-core ARM Concurrency in control processing: task-level parallelism Big.LITTLE: minimal logic for given task; voltage and frequency scaling 2012 Target Compiler Technologies 3

4 Heterogeneous Multicore SoC Multiple ASIPs Application-Specific Instruction-set Processors Concurrency in data processing: task-, data-, instr.-level parallelism Minimal logic for given task: architectural specialization Locality of reference: local memories and interconnect Power gating of ASIPs when not in use 2012 Target Compiler Technologies 4

5 Heterogeneous Multicore SoC Hardwired datapath an endangered species? Except in a few cases, market dynamics require programmability ASIPs enable programmability and efficiency ARM & ASIPs offer a familiar software approach to SoC design: quick algorithm mapping from C/Matlab through SDK/debug tools 2012 Target Compiler Technologies 5

6 No MPSoC Design Without Tools Tools at IP level (ASIP cores) Architectural exploration SDK generation: C compiler, ISS, debugger RTL generation IP Designer Tools at IP subsystem level (multicore) Code parallelisation Communication and synchronization Multicore platform generation MP Designer 2012 Target Compiler Technologies 6

7 IP Designer Tool Suite 2012 Target Compiler Technologies 7

8 Architectural optimisation space ASIP architectural optimisation space Parallelism Specialisation Instructionlevel parallelism Datalevel parallelism Tasklevel parallelism App.- specific data types App.- specific instructions Pipeline Connectivity & storage matching application s data-flow Orthogonal instruction set (VLIW) Encoded instruction set Vector processing (SIMD) Multicore Multithreading Integer, fractional, floating-point, bits, complex, vector Distributed regs, sub-ranges Multiple mem s, sub-ranges nml and IP Designer Support a wide range of ASIP architectures Enable true architectural exploration Make ASIP design easy App.-spec. memory addressing Direct, indirect, postmodification, indexed, stack indirect App.-spec. data processing Any exotic operator Single or multi-cycle App.-spec. control processing Jumps, subroutines, interrupts, HW do-loops, residual control, predication Relative or absolute, address range, delay slots 2012 Target Compiler Technologies 8

9 IP Designer s C Compiler DSPstone benchmark on TI C55x Target s compiler TI s compiler Gain (Target vs TI) Cycles Code Size Cycles Code Size Cycles Code Size Small-scale examples FIR restrict % -5% Convolution repeat % -31% LMS original % 13% Matrix repeat % 13% IIR, N=4 restrict % 18% IIR, N=16 restrict % 18% 22% 4% Large-scale examples FFT bit reverse original % 0% FFT butterfly original % 6% ADPCM original % 9% 7% 5% Graph-based C compiler technology offers retargetability and efficiency at same time Compilable sub-set of TI C55x modelled in nml in 2.5 person-months Only few C code modifications made: repeat loop, restrict pointers 2012 Target Compiler Technologies 9

10 IP Designer s RTL Generator Example: audio DSP (90 nm, clock 220 MHz, 0.9V) Area (kgates) 0-60% A B C D E Power ( W/MHz) IP Designer configuration options A Standard RTL generation B Clock gating + operand isolation for functional units C Operand isolation for multiplexers D Latching of register addresses in instruction decoder E Manual design by customer Low-power optimisations yield 60% savings Low-power optimisations have small area cost Area and power within percentages from hand-optimized design 2012 Target Compiler Technologies 10

11 IP Designer Example Wolverine platform Ultra-low power multi-core platform, optimised for audio coding Used in hearing instruments and Bluetooth headsets 20-bit precision 4 micro-dsp VLIW-ASIPs + 4 filter accelerators + 1 micro-processor core 0.04 mw/m-mac, 42 MIPS at fclock = 2 MHz (0.13u CMOS) 2012 Target Compiler Technologies 11 Sound Design Technologies Reproduced with permission

12 IP Designer Example Reed-Solomon coding ASIP FEC for wireless link in personal health-care systems IEEE a, supports RS(63, 55) encoding/decoding Concurrency Data-level: 8 elements SIMD, 6-bit/element Instruction-level: 2 scalar + 2 vector issue slots Specialisation Data and instruction-level parallelism Hardware for finite-field multiplication and addition 2012 Target Compiler Technologies 12 IMEC Reproduced with permission

13 IP Designer Example Reed-Solomon coding ASIP Performance Gate count 2012 Target Compiler Technologies 13 IMEC Reproduced with permission

14 IP Designer Example Reed-Solomon coding ASIP Energy 2012 Target Compiler Technologies IMEC Reproduced with permission

15 TM IP Designer Market Adoption Medical Audio Video & imaging Wireless Wireline Network processing High-perf. computing Automotive Crypto & identification Shown are publicly announced IP Designer customers Estimate about 150 unique SoC products based on IP Designer in the market today 2012 Target Compiler Technologies 15

16 No MPSoC Design Without Tools Tools at IP level (ASIP cores) Architectural exploration SDK generation: C compiler, ISS, debugger RTL generation IP Designer Tools at IP subsystem level (multicore) Code parallelisation Communication and synchronization Multicore platform generation MP Designer 2012 Target Compiler Technologies 16

17 MP Designer Tool Suite 2012 Target Compiler Technologies 17

18 User-Guided Parallelisation Label C code blocks for parallelisation int main(int argc,char void main_encoder(struct *argv[]){ void image* process_du(sbyte* img) { CDU, int init_all(); vlc_init: { DCY=0;DCCb=0;DCCr=0; blk) { } parsection: { for (ypos=0..height) { jpg_open: { for (xpos=0...width) SWORD { DU[64]; jpg_fopen(jpg_filename); for (blk=0..5) { fdct_main: { writeword(0xffd8); SBYTE //SOI DU[64]; int* int_fdtbl = write_app0info(); loading: blk_fdtbl[blk]; } load_data_unit_from_rgb_buffer(img, fdct_and_quantization(cdu, main_encoder(&in_img); xpos, ypos, blk, int_fdtbl,du); process_du(du,blk); } jpg_close: { } writeword(0xffd9); } //EOI vlc_main: { jpg_fclose(); } //Encode ACs } vlc_fini: { // Bit-alignment while (i<=end0pos) of EOI marker {... } } if (bytepos>=0) { if (end0pos!=63) free(in_img.rgb_buffer); writebits((1<<(bytepos+1))-1, writebits(eob); bytepos+1); return 0; } } } } } } 2012 Target Compiler Technologies 18

19 User-Guided Parallelisation Parallelisation pragmas processor P0 type dlx processor P1 type dlx processor P2 type dlx parallel ParRegion lbl main::parsection task LOAD target P0 include lbl main_encoder::loading Sample parallelisation on 3-core architecture task DCT target P1 include lbl process_du::fdct_main task VLC target P2 include lbl main::jpg_open include lbl main_encoder::vlc_init include lbl process_du::vlc_main include lbl main_encoder::vlc_fini include lbl main::jpg_close 2012 Target Compiler Technologies 19

20 Exploration For each parallelisation, MP Designer shows task graph with estimated processor loads Tas k 0 " LOA D" Pro c 0 " P0" ( dlx) ma in_en code r::lo ading : 35.8 % IN: <no ne> par _reg ion [ b0] m ain_e ncod er() [b17 ] f or [b 18] for [b 19] OU T: <no ne> for [ b20] JPEG encoding on 3-DLX architecture [NC dep T0 -> b2 0] DU (64 ) [FF ] T ask 1 "DC T" P roc 1 "P1 " (dl x) p roce ss_d U::fd ct_m ain: 22.2 % p roce ss_d U::q uant_ main : 25.0 % * TOT AL* 47.1 % I N: i n_im g.hei ght i n_im g.wi dth p ar_r egion [b0 ] main _enc oder () [b 17] for [b18 ] for [b19 ] O UT: < none > fo r [b2 0] p roce ss_d U() [ b22] [NC dep T1 - > b 22] DU_ ZZ (1 28) [FF] en d0p os (4 ) Task 2 "V LC" Proc 2 "P 2" (d lx) main ::jpg _ope n: 0.0 % main _enc oder ::vlc_ init: 0.0 % proce ss_d U::v lc_m ain: 16.9 % main _enc oder ::vlc_ fini: 0.0 % main ::jpg _clos e: 0.0 % *TOT AL* 16.9 % IN: JPG_ filen ame SOF0 info.heig ht SOF0 info.wid th in_im g.he ight in_im g.w idth par_ regio n [b0 ] mai n_en code r() [b 17] for [b18 ] fo r [b1 9] OUT : <non e> f or [b 20] proce ss_d U() [b22 ] 2012 Target Compiler Technologies 20

21 Exploration T0 "bs" (dlx) bitstream_hdr:2.0 % bitstream_cfs: 8.2 % idct_p_inter: 8.8 % idct_b: 1.0 % make_p_mv: 0.2 % make_b_mv: 0.0 % *TOTAL* 20.4 % par_region [b0] initdec() [b11] while [b19] getpict() [b20] getmbs() [b23] while [b26] Task graph for H263 encoding on 8 cores [NC dep T0 -> b0] h+w (4) [NC dep T0 -> b11] h+w (4) [NC dep T0 -> b19] start (4) [NC dep T0 -> b23] MBAmax (4) [NC dep T0 -> b26] B_MV (16) [FF] P_MV (48) [FF] comm_mb (4) comm_pict_hdr (2) mvdbxy (4) T1 "recon" (dlx) rec_b: 3.1 % rec_p: 20.5 % *TOTAL* 23.7 % IN: framenum has_startcode par_region [b0] initdec() [b11] while [b19] getpict() [b20] getmbs() [b23] while [b26] [NC dep T0 -> b19] start (4) pb_frame (4) [NC dep T0 -> b23] MBA (4) MBAmax (4) [LC dep T0 -> b26] bx (4) by (4) pmvdbxy (4) [NC dep T0 -> b26] B_MV (16) [CF] Mode+pCBP+pCBPB+pCOD (4x4) pblk+bblk (768) [FF] trb+trd (2x4) [NC dep T0 -> b19] start (4) pb_frame (4) [NC dep T0 -> b23] MBAmax (4) [NC dep T1 -> b26] brec (384) [FC] prec (384) [FF] [NC dep T0 -> b26] comm_mb (4) err (4) pb_frame (4) [NC dep T0 -> b19] start (4) [NC dep T0 -> b23] MBAmax (4) T2 "addblock" (dlx) idct_p_intra: 2.8 % addblock_p_intra: 1.2 % addblock_p_inter: 3.8 % reconblock_b: 6.7 % addblock_b: 0.5 % *TOTAL* 14.9 % IN: framenum has_startcode refidct par_region [b0] while [b19] getpict() [b20] getmbs() [b23] while [b26] Global dependency analysis automatically ensures correct communication & synchronisation Manual design would be error-prone [NC dep T2 -> b26] brec (384) [CF] T3 "store_bmb" (dlx) store_mb_b: 15.1 % init_idct: 0.1 % *TOTAL* 15.3 % IN: framenum has_startcode refidct par_region [b0] initdec() [b11] while [b19] getpict() [b20] getmbs() [b23] while [b26] store_mb_b() [b72] [NC dep T2 -> b26] prec (384) [CF] [NC dep T3 -> b72] b_rgb_mb (884) [CF] T4 "out" (dlx) store_mb_p: 21.8 % mb_rgb_copyin: 1.6 % padding_mb: 2.5 % *TOTAL* 26.0 % IN: framenum has_startcode outputname par_region [b0] initdec() [b11] while [b19] getpict() [b20] getmbs() [b23] while [b26] store_mb_b() [b72] comm_mb (4) comm_pict_hdr (2) 2012 Target Compiler Technologies 21

22 Exploration JPEG encoding on multi-dlx architecture Algorithm # Cores Parallelisation Mcycles* seq par Speed up Load (%) P0 P1 P2 P3 P4 Efficiency (%) Original Original 2 ld+dct+q vlc Original 3 ld dct+q vlc Original 4 ld dct q vlc Optimised 2 ld+dct q+vlc Optimised 3 ld dct+q vlc Optimised 3 ld dct q+vlc Optimised 4 ld dct q vlc Split quant 3 ld dct+q0 q1+vlc Dual load 5 ld0 ld1 dct q vlc Entire exploration in only days of time * Cycles for 256x160-pixel image 2012 Target Compiler Technologies 22

23 Multicore SDK ISS Core-1 ISS Core-2 ISS Core-3 JTAG controller Multicore simulation Multicore on-chip debugging Debug controller HW Core-1 Debug controller HW Core-2 Debug controller HW Core Target Compiler Technologies 23

24 Conclusion ASIPs enable low-power, acceleration and programmability in ARM-based multicore SoCs No (efficient) multicore SoC design without tools Design and programming of individual ASIP cores Multicore parallelisation and platform generation Target can be your ASIP and multicore tools partner More information Come to our booth Brochure in your conference bag Target Compiler Technologies 24